From 64d71dcbc5fa6790385b288de25224d386b047b0 Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Wed, 24 Sep 2014 18:45:31 -0700 Subject: fpga: Multiple X300 FPGA bugfixes and enhancements - Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 --- fpga/usrp3/top/x300/.gitignore | 1 - fpga/usrp3/top/x300/Makefile | 35 +- fpga/usrp3/top/x300/Makefile.x300.inc | 45 +- fpga/usrp3/top/x300/coregen/.gitignore | 1 + fpga/usrp3/top/x300/coregen/Makefile.srcs | 38 +- .../usrp3/top/x300/coregen/axi64_4k_2clk_fifo.gise | 2 +- fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.ngc | 2 +- fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.v | 2 +- fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.veo | 2 +- fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xco | 4 +- .../usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xise | 10 +- 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fpga/usrp3/top/x300/gige_phy.v create mode 100644 fpga/usrp3/top/x300/gige_phy/README create mode 100644 fpga/usrp3/top/x300/gige_phy/gige_phy_mdio.v create mode 100644 fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_block.v create mode 100644 fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_reset_sync.v create mode 100644 fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_sync_block.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_transceiver.v create mode 100644 fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v delete mode 100644 fpga/usrp3/top/x300/gige_phy_mdio.v create mode 100644 fpga/usrp3/top/x300/ten_gige_phy/README create mode 100755 fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v create mode 100755 fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v create mode 100755 fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v create mode 100755 fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_block.v create mode 100755 fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_mod.v create mode 100644 fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf create mode 100644 fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v (limited to 'fpga/usrp3/top/x300') diff --git a/fpga/usrp3/top/x300/.gitignore b/fpga/usrp3/top/x300/.gitignore index 5e3b77dd5..77272171e 100644 --- a/fpga/usrp3/top/x300/.gitignore +++ b/fpga/usrp3/top/x300/.gitignore @@ -1,7 +1,6 @@ build* isim* fuse* -gen_ddrlvds_tb tmp* *.log *impact* diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile index dbe3bdd55..4d3e668e6 100644 --- a/fpga/usrp3/top/x300/Makefile +++ b/fpga/usrp3/top/x300/Makefile @@ -28,15 +28,22 @@ clean: print_report = \ echo "========================================================================"; \ - cat $(1) | grep "Design Summary:" -A 124; \ + cat $(1)/x300.syr | grep "Device utilization summary:" -A 30; \ echo "========================================================================"; \ echo "Timing Summary:\n"; \ - cat $(1) | grep constraint | grep met | grep -v "*"; \ + cat $(1)/x300.twr | grep constraint | grep met | grep -v "*"; \ echo "========================================================================"; +# ise_build($1=Device, $2=Definitions) +ifndef EXPORT_ONLY + ise_build = make -f Makefile.x300.inc bin NAME=$@ DEVICE=$1 $2 EXTRA_DEFS="$2" +else + ise_build = @echo "Skipping ISE build and exporting pre-built files."; +endif + # post_build($1=Device, $2=Flavor) post_build = \ - @$(call print_report,build-$(1)_$(2)/build.log) \ + @$(call print_report,build-$(1)_$(2)) \ mkdir -p build; \ echo "Exporting bitstream files..."; \ cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \ @@ -45,54 +52,54 @@ post_build = \ $(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \ cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \ echo "Exporting logs..."; \ - cp build-$(1)_$(2)/build.log build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).log; \ + cp build-$(1)_$(2)/x300.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).syr; \ cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \ echo "\nDONE ... $(1)_$(2)\n"; #1Gig on both ports X310_1G: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)" + $(call ise_build,XC7K410T,$(GIGE_DEFS)) $(call post_build,X310,1G) X300_1G: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)" + $(call ise_build,XC7K325T,$(GIGE_DEFS)) $(call post_build,X300,1G) #1Gig on port0, 10Gig on port1 X310_HG: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)" + $(call ise_build,XC7K410T,$(HYBRID_DEFS)) $(call post_build,X310,HG) X300_HG: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)" + $(call ise_build,XC7K325T,$(HYBRID_DEFS)) $(call post_build,X300,HG) #10Gig on both ports X310_XG: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)" + $(call ise_build,XC7K410T,$(XGIGE_DEFS)) $(call post_build,X310,XG) X300_XG: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)" + $(call ise_build,XC7K325T,$(XGIGE_DEFS)) $(call post_build,X300,XG) # 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's X310_HGS: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" + $(call ise_build,XC7K410T,$(HYBRID_SRAM_DEFS)) $(call post_build,X310,HGS) X300_HGS: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T FLOORPLAN=1 $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" + $(call ise_build,XC7K325T,$(HYBRID_SRAM_DEFS)) $(call post_build,X300,HGS) # 10Gig on both ports, SRAM Tx FIFO's X310_XGS: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" + $(call ise_build,XC7K410T,$(XGIGE_SRAM_DEFS)) $(call post_build,X310,XGS) X300_XGS: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" + $(call ise_build,XC7K325T,$(XGIGE_SRAM_DEFS)) $(call post_build,X300,XGS) diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc index 6e13e4fed..ef7cda0ec 100644 --- a/fpga/usrp3/top/x300/Makefile.x300.inc +++ b/fpga/usrp3/top/x300/Makefile.x300.inc @@ -65,12 +65,32 @@ capture_ddrlvds.v \ gen_ddrlvds.v \ radio.v \ bus_int.v \ -gige_phy.v \ -gige_phy_mdio.v \ x300.ucf \ stc3.ucf \ timing.ucf +ONE_GIG_SRCS = $(COREGEN_ONE_GIG_SRCS) \ +gige_phy/gige_phy_mdio.v \ +gige_phy/gige_sfp_mdio_block.v \ +gige_phy/gige_sfp_mdio_reset_sync.v \ +gige_phy/gige_sfp_mdio_sync_block.v \ +gige_phy/transceiver/gige_sfp_mdio_transceiver.v \ +gige_phy/transceiver/gige_sfp_mdio_gtwizard.v \ +gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v \ +gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v \ +gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v \ +gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v \ +gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v \ + +TEN_GIG_SRCS = $(COREGEN_TEN_GIG_SRCS) \ +ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v \ +ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf \ +ten_gige_phy/ten_gig_eth_pcs_pma_block.v \ +ten_gige_phy/ten_gig_eth_pcs_pma_mod.v \ +ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \ +ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \ + ifeq ($(FLOORPLAN), 1) ifeq ($(DEVICE), XC7K325T) TOP_SRCS+=floorplan_X300.ucf @@ -82,11 +102,11 @@ ifeq ($(FLOORPLAN), 1) endif ifdef BUILD_10G -ETH_SRCS+=$(TEN_GIG_SRCS) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf) +ETH_SRCS+=$(abspath $(TEN_GIG_SRCS)) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf) endif ifdef BUILD_1G -ETH_SRCS+=$(ONE_GIG_SRCS) $(abspath x300_1ge.ucf) +ETH_SRCS+=$(abspath $(ONE_GIG_SRCS)) $(abspath x300_1ge.ucf) endif ifdef ETH10G_PORT0 @@ -130,26 +150,23 @@ SYNTHESIZE_PROPERTIES = \ "Verilog Macros" "$(EXTRA_DEFS) $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" +"Macro Search Path" "$(shell pwd)/coregen" MAP_PROPERTIES = \ "Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ "Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE \ -"Optimization Strategy (Cover Mode)" Speed \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Enable Multi-Threading 2" \ -"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 )) -#"Map to Input Functions" 4 \ +"Register Duplication" On \ +"Placer Effort Level" High \ +"Placer Extra Effort" Normal \ +"Enable Multi-Threading" 2 \ +"Starting Placer Cost Table (1-100)" $(shell awk 'BEGIN{srand();printf("%d", (100*rand()%100)+1)}') PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High \ "Extra Effort (Highest PAR level only)" Normal \ -"Enable Multi-Threading 4" +"Enable Multi-Threading" 4 STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ diff --git a/fpga/usrp3/top/x300/coregen/.gitignore b/fpga/usrp3/top/x300/coregen/.gitignore index c9144ed1a..5cfc8bb32 100644 --- a/fpga/usrp3/top/x300/coregen/.gitignore +++ b/fpga/usrp3/top/x300/coregen/.gitignore @@ -1,4 +1,5 @@ _xmsgs *.log +*.ncf /bootram.ncf /bootram.xise diff --git a/fpga/usrp3/top/x300/coregen/Makefile.srcs b/fpga/usrp3/top/x300/coregen/Makefile.srcs index d70c89260..e35c7a08b 100644 --- a/fpga/usrp3/top/x300/coregen/Makefile.srcs +++ b/fpga/usrp3/top/x300/coregen/Makefile.srcs @@ -12,8 +12,11 @@ CG_BUILD_DIR = $(BUILD_DIR)/coregen COREGEN_SRCS = $(abspath $(addprefix $(CG_BUILD_DIR)/, \ input_sample_fifo.v \ input_sample_fifo.xco \ +axi64_4k_2clk_fifo.v \ axi64_8k_2clk_fifo.v \ fifo_4k_2clk.v \ +fifo_short_2clk.v \ +fifo_short_2clk.xco \ radio_clk_gen.v \ radio_clk_gen.xco \ bus_clk_gen.v \ @@ -39,45 +42,14 @@ chipscope_icon.v \ chipscope_icon.xco \ chipscope_icon_2port.v \ chipscope_icon_2port.xco \ -fifo_xlnx_16x40_2clk.v \ -fifo_xlnx_16x40_2clk.xco \ -fifo_short_2clk.v \ -fifo_short_2clk.xco \ )) -ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ +COREGEN_ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ gige_sfp_mdio.v \ -gige_sfp_mdio/example_design/gige_sfp_mdio_block.v \ -gige_sfp_mdio/example_design/gige_sfp_mdio_reset_sync.v \ -gige_sfp_mdio/example_design/gige_sfp_mdio_sync_block.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_transceiver.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \ -gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \ -gige_sfp.v \ -gige_sfp/example_design/gige_sfp_block.v \ -gige_sfp/example_design/gige_sfp_reset_sync.v \ -gige_sfp/example_design/gige_sfp_sync_block.v \ -gige_sfp/example_design/transceiver/gige_sfp_transceiver.v \ -gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v \ -gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v \ -gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v \ -gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v \ -gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v \ )) -TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ +COREGEN_TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ ten_gig_eth_pcs_pma.v \ -ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v \ -ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf \ -ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v \ -ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_mod.v \ -ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \ -ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ -ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \ )) #make rule to regenerate bootram when the coe file is changed diff --git a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.gise b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.gise index 9cef45499..80454225a 100644 --- a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.gise +++ b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.ngc b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.ngc index 3bc2a9caf..a217a522b 100644 --- a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.ngc +++ b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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7c?2:1bh84?::ke2?6=3`lj6=44o2;2>5<;:7>54;294~"4l>09o55G74`8L27>3An97)=88;1g2>"5m1087dj::188mc0=831bjl4?::m0=4<722wi8=;50;694?6|,:n<6?m7;I56f>N0901Ch?5+36:97a0<,;o36>5fd483>>oa>3:17dhn:188k6?62900qo:?4;290?6=8r.8h:4=c99K30d<@>;27Ej=;%142.9i54<;hf6>5<>i4180;66sm41194?2=83:p(>j8:3a;?M12j2B<=45Gd39'72>=;m<0(?k7:29j`0<722cm:7>5;hdb>5<1<7>t$2f4>7e?3A=>n6F8189K`7=#;>21?i84$3g;>6=nl<0;66gi6;29?l`f2900c>7>:188yg2293:187>50z&0`2<5k11C;8l4H63:?Mb53-9<47=k6:&1a=<43`n>6=44ig494?=nnh0;66a<9083>>{e<<:1<7:50;2x 6b02;i37E9:b:J45<=Ol;1/?:653e48 7c?2:1bh84?::ke2?6=3`lj6=44o2;2>5<?j7>54;294~"4l>09o55G74`8L27>3An97)=88;1g2>"5m1087dj::188mc0=831bjl4?::m0=4<722wi89k50;694?6|,:n<6?m7;I56f>N0901Ch?5+36:97a0<,;o36>5fd483>>oa>3:17dhn:188k6?62900qo:;d;290?6=8r.8h:4=c99K30d<@>;27Ej=;%142.9i54<;hf6>5<>i4180;66sm45a94?2=83:p(>j8:3a;?M12j2B<=45Gd39'72>=;m<0(?k7:29j`0<722cm:7>5;hdb>5<1<7>t$2f4>7e?3A=>n6F8189K`7=#;>21?i84$3g;>6=nl<0;66gi6;29?l`f2900c>7>:188yg26k3:187>50z&0`2<5k11C;8l4H63:?Mb53-9<47=k6:&1a=<43`n>6=44ig494?=nnh0;66a<9083>>{e<8h1<7:50;2x 6b02;i37E9:b:J45<=Ol;1/?:653e48 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6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm57d94?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=?o1<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm57f94?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=>;1<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm59194?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=181<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm59394?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=1:1<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm59694?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=8:1<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm51d94?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=9o1<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm51f94?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=8;1<7:50;2x 6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm53194?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e=;81<7:50;2x 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6b02:=27E9:b:J45<=#;121;k;4iea94?=nnl0;66g>i40>0;66sm53694?2=83:p(>j8:25:?M12j2B<=45+39:93c3>o4k00;66a<8683>>{e?j7E9:b:J45<=nlj0;66g<6g83>>i40>0;66sm4b:94?5=83:p(>j8:250?M12j2B<=45+2d:90g=n:m81<75f2e194?=h;1=1<75rb5f3>5<4290;w)=k7;56e>N0=k1C;<74iea94?=n;?l1<75`39594?=zj=hm6=4;:183!5c?39<56F85c9K34?>o4k00;66a<8683>>{em6F85c9K34?5<3290;w)=k7;14=>N0=k1C;<74iea94?=nnl0;66g>i40>0;66sm4b494?5=83:p(>j8:250?M12j2B<=45+2d:90g=n:m81<75f2e194?=h;1=1<75rb5af>5<4290;w)=k7;56e>N0=k1C;<74iea94?=n;?l1<75`39594?=zj=ho6=4;:183!5c?39<56F85c9K34?>o4k00;66a<8683>>{em6F85c9K34?5<3290;w)=k7;14=>N0=k1C;<74iea94?=nnl0;66g>i40>0;66sm4b694?5=83:p(>j8:250?M12j2B<=45+2d:90g=n:m81<75f2e194?=h;1=1<75rb5a`>5<4290;w)=k7;56e>N0=k1C;<74iea94?=n;?l1<75`39594?=zj=hi6=4;:183!5c?39<56F85c9K34?>o4k00;66a<8683>>{em6F85c9K34?5<3290;w)=k7;14=>N0=k1C;<74iea94?=nnl0;66g>i40>0;66sm4b094?5=83:p(>j8:250?M12j2B<=45+2d:90g=n:m81<75f2e194?=h;1=1<75rb5ab>5<4290;w)=k7;56e>N0=k1C;<74iea94?=n;?l1<75`39594?=zj=h26=4;:183!5c?39<56F85c9K34?>o4k00;66a<8683>>{em6F85c9K34?5<3290;w)=k7;14=>N0=k1C;<74iea94?=nnl0;66g>i40>0;66sm4b294?5=83:p(>j8:250?M12j2B<=45+2d:90g=n:m81<75f2e194?=h;1=1<75rb5d`>5<3290;w)=k7;0`<>N0=k1C;<74$3g;>6=nl<0;66gi6;29?l`f2900c>7>:188yg2aj3:187>50z&0`2<5k11C;8l4H63:?!4b0390ei;50;9jb3<722cmm7>5;n1:5?6=3th?jl4?:583>5}#;m=1>n64H67a?M1612.9i54<;hf6>5<>i4180;66sm4g;94?2=83:p(>j8:3a;?M12j2B<=45+2d:97>oc=3:17dh9:188mcg=831d?4?50;9~f1`?290?6=4?{%1g3?4d02B<9o5G70;8 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.v b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.v index b9e86d56b..f528c839a 100644 --- a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.v +++ b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.v @@ -22,7 +22,7 @@ * devices, or systems. Use in such applications are expressly * * prohibited. * * * -* (c) Copyright 1995-2013 Xilinx, Inc. * +* (c) Copyright 1995-2014 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // You must compile the wrapper file axi64_4k_2clk_fifo.v when simulating diff --git a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.veo b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.veo index 81b190ec8..15ce19971 100644 --- a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.veo +++ b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.veo @@ -22,7 +22,7 @@ * devices, or systems. Use in such applications are expressly * * prohibited. * * * -* (c) Copyright 1995-2013 Xilinx, Inc. * +* (c) Copyright 1995-2014 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ diff --git a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xco b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xco index 2cd991a9d..d10c9defe 100644 --- a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xco +++ b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version 14.4 -# Date: Fri Jan 25 04:53:45 2013 +# Xilinx Core Generator version 14.7 +# Date: Wed Sep 3 23:46:32 2014 # ############################################################## # diff --git a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xise b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xise index be9f25175..a87f60849 100644 --- a/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xise +++ b/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo.xise @@ -9,10 +9,10 @@ - + - + @@ -55,7 +55,7 @@ - + @@ -339,8 +339,8 @@ - - + + diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf deleted file mode 100644 index 3f2148f6a..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf +++ /dev/null @@ -1,4 +0,0 @@ -NET "*_resync*" TNM = FFS "axi_intercon_2x64_128_reset_resync"; -NET "*INTERCONNECT_ARESETN" TNM = FFS "axi_intercon_2x64_128_reset_resync"; -TIMESPEC "TS_axi_intercon_2x64_128_reset_resync" = TO "axi_intercon_2x64_128_reset_resync" TIG; - diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise index 822e58aee..bf9a586eb 100644 --- a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise +++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.gise b/fpga/usrp3/top/x300/coregen/axi_vfifo_64.gise deleted file mode 100644 index 965336e80..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.ngc b/fpga/usrp3/top/x300/coregen/axi_vfifo_64.ngc deleted file mode 100644 index f44c0ad6c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$3`b6~753-Xnzd}foo8#5+421).97 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3df2:oh7c8m9;18?j27k3:1(;ln:52a?k0e13:07b:?a;29 3df2=:i7c8m9;38?j2703:1(;ln:52a?k0e13807b:?7;29 3df2=:i7c8m9;18?j27>3:1(;ln:52a?k0e13>07b:?5;29 3df2=:i7c8m9;78?j27<3:1(;ln:52a?k0e13<07b:?3;29 3df2=:i7c8m9;58?j27:3:1(;ln:52a?k0e13207b:?1;29 3df2=:i7c8m9;;8?j2783:1(;ln:52a?k0e13k07b=if;29 3df2=:i7c8m9;`8?j5al3:1(;ln:52a?k0e13i07b=ic;29 3df2=:i7c8m9;f8?j5aj3:1(;ln:52a?k0e13o07b=ia;29 3df2=:i7c8m9;d8?j5a13:1(;ln:52a?k0e13;;76a!0ei3>;n6`9b8825>=h;o<1<7*9b`874g=i>k31=?54o2d6>5<#>kk18=l4n7`:>45<3f9m87>5$7`b>16e3g28=07b:>1;29 3df2=:i7c8m9;3;?>i3990;6)8ma;63f>h1j00:565`41d94?"1jh0?m;o4a=?7d32e?<44?:%4ae?27j2d=n44>d:9l7cc=83.=nl4;0c9m2g?=9l10c>h=:18'2gg=<9h0b;l6:0d8?j24:3:1(;ln:512?k0e13:07b:<0;29 3df2=9:7c8m9;38?j25m3:1(;ln:512?k0e13807b:=d;29 3df2=9:7c8m9;18?j25k3:1(;ln:512?k0e13>07b:=b;29 3df2=9:7c8m9;78?j25i3:1(;ln:512?k0e13<07b:=9;29 3df2=9:7c8m9;58?j2503:1(;ln:512?k0e13207b:=7;29 3df2=9:7c8m9;;8?j25>3:1(;ln:512?k0e13k07b:=5;29 3df2=9:7c8m9;`8?j25;3:1(;ln:512?k0e13i07b:=2;29 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2512=78:;h70f?6=3f<:?7>5;|`27`?=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;3d594?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:?h;50;094?6|,>9=68ji;I06af=O:3;29?xd6;m;1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24fd=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0b594?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68j91<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24f7=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0cd94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68kh1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24g?=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0c594?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68k;1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24d`=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0`f94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68h31<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24d1=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0`794?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68h;1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24<`=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0e;94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68m?1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24a5=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0e394?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:9=68ji;I06af=O:3;29?xd68jn1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24f?=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;0c194?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:=?;50;094?6|,>9=68ji;I06af=O:3;29?xd69;91<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2577=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;10d94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:=9=68ji;I06af=O:3;29?xd698h1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`254?=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;10594?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:=<;50;094?6|,>9=68ji;I06af=O:3;29?xd698;1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`255`=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;11f94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:==l50;094?6|,>9=68ji;I06af=O:3;29?xd69931<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2551=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;11794?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:===50;094?6|,>9=68ji;I06af=O:3;29?xd699;1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`24c`=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;12794?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:=>=50;094?6|,>9=68ji;I06af=O:3;29?xd69:;1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`257`=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;13f94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:=?l50;094?6|,>9=68ji;I06af=O:3;29?xd69;31<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2571=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;10194?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hk750;094?6|,>9=68ji;I06af=O:3;29?xd6lo=1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2`c3=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;dg194?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hk?50;094?6|,>9=68ji;I06af=O:3;29?xd6lll1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2a5d=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;e1;94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:i=950;094?6|,>9=68ji;I06af=O:3;29?xd6m9?1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2a55=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;e1394?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hkh50;094?6|,>9=68ji;I06af=O:3;29?xd6lon1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2`cd=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;db594?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hn;50;094?6|,>9=68ji;I06af=O:3;29?xd6lj91<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2`f7=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;dcd94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hi750;094?6|,>9=68ji;I06af=O:3;29?xd6lm=1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2`a3=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;de194?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hi?50;094?6|,>9=68ji;I06af=O:3;29?xd6ljl1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2`fb=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;db`94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:hn750;094?6|,>9=68ji;I06af=O:3;29?xd6k9>1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2g54=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;c1294?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:nkk50;094?6|,>9=68ji;I06af=O:3;29?xd6joi1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2fcg=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;c0494?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:o<:50;094?6|,>9=68ji;I06af=O:3;29?xd6k881<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2g46=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;c1g94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:o=m50;094?6|,>9=68ji;I06af=O:3;29?xd6k9k1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2g5>=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;c1494?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:ni<50;094?6|,>9=68ji;I06af=O:3;29?xd6jm:1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2ffc=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;bba94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:nno50;094?6|,>9=68ji;I06af=O:3;29?xd6jl>1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2f`4=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;bd294?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:nik50;094?6|,>9=68ji;I06af=O:3;29?xd6jmi1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2fag=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;be:94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:ni850;094?6|,>9=68ji;I06af=O:3;29?xd6jm>1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2==>=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;99494?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:55:50;094?6|,>9=68ji;I06af=O:3;29?xd61181<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2==6=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;96g94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:54o50;094?6|,>9=68ji;I06af=O:3;29?xd61021<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2=<0=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;98694?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:54<50;094?6|,>9=68ji;I06af=O:3;29?xd610:1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2==c=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;99a94?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:55o50;094?6|,>9=68ji;I06af=O:3;29?xd61<<1<7<50;2x 2512=78:;h70f?6=3f<:?7>5;|`2=02=8381<7>t$615>0ba3A8>in5G24c7?!3293<>7d;94094?4=83:p(:=9:4fe?M42mj1C>8o;;%765?023`?8n7>5;n427?6=3th:58>50;094?6|,>9=68ji;I06af=O:3;29?xd61=o1<7<50;2x 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8o;;|lb75`=83;pD?;n4:me677290:wE<:a59~jd5693:1=vF=5`68ykg49;0;6{ii:;?6=4>{I06e1=zfh9:97>51zJ11d2?7:182M42i=1vbl=>9;295~N5=h>0qco<1`83>4}O:5<6sA8>m95rn`12`?6=9rB99l:4}oc05`<728qC>8o;;|lb74`=83;pD?;n4:me647290:wE<:a59~jd5593:1=vF=5`68ykg4:;0;6{ii:8?6=4>{I06e1=zfh9997>51zJ11d2;4?:0yK60g33tdj??950;3xL73f<2wem><7:182M42i=1vbl==9;295~N5=h>0qco<2`83>4}O:5<6sA8>m95rn`11`?6=9rB99l:4}oc06`<728qC>8o;;|lb77`=83;pD?;n4:me657290:wE<:a59~jd54m3:1=vF=5`68ykg4;o0;6{ii:>:6=4>{I06e1=zfh9?>7>51zJ11d24?:0yK60g33tdj?9:50;3xL73f<2wem>:::182M42i=1vbl=;6;295~N5=h>0qco<4683>4}O:5<6sA8>m95rn`17e?6=9rB99l:4}oc00g<728qC>8o;;|lb71e=83;pD?;n4:me62c290:wE<:a59~jd53m3:1=vF=5`68ykg4{ii:?:6=4>{I06e1=zfh9>>7>51zJ11d24?:0yK60g33tdj?8:50;3xL73f<2wem>;::182M42i=1vbl=:6;295~N5=h>0qco<5683>4}O:5<6sA8>m95rn`16e?6=9rB99l:4}oc01g<728qC>8o;;|lb70e=83;pD?;n4:me63c290:wE<:a59~jd52m3:1=vF=5`68ykg4=o0;6{ii:<:6=4>{I06e1=zfh9=>7>51zJ11d24?:0yK60g33tdj?;:50;3xL73f<2wem>8::182M42i=1vbl=96;295~N5=h>0qco<6683>4}O:5<6sA8>m95rn`15e?6=9rB99l:4}oc02g<728qC>8o;;|lb73e=83;pD?;n4:me60c290:wE<:a59~jd51m3:1=vF=5`68ykg4>o0;6:1<7?tH37b0>{ii:=:6=4>{I06e1=zfh9<>7>51zJ11d24?:0yK60g33tdj?::50;3xL73f<2wem>9::182M42i=1vbl=86;295~N5=h>0qco<7683>4}O:5<6sA8>m95rn`14e?6=9rB99l:4}oc03g<728qC>8o;;|lb72e=83;pD?;n4:me61c290:wE<:a59~jd50m3:1=vF=5`68ykg4?o0;6{ii:2:6=4>{I06e1=zfh93>7>51zJ11d24?:0yK60g33tdj?5:50;3xL73f<2wem>6::182M42i=1vbl=76;295~N5=h>0qco<8683>4}O:5<6sA8>m95rn`1;e?6=9rB99l:4}oc08o;;|lb7=e=83;pD?;n4:me6>c290:wE<:a59~jd5?m3:1=vF=5`68ykg40o0;6{ii:3:6=4>{I06e1=zfh92>7>51zJ11d24?:0yK60g33tdj?4:50;3xL73f<2wem>7::182M42i=1vbl=66;295~N5=h>0qco<9683>4}O:5<6sA8>m95rn`1:e?6=9rB99l:4}oc0=g<728qC>8o;;|lb7m3:1=vF=5`68ykg41o0;6{ii:k:6=4>{I06e1=zfh9j>7>51zJ11d24?:0yK60g33tdj?l:50;3xL73f<2wem>o::182M42i=1vbl=n6;295~N5=h>0qco4}O:5<6sA8>m95rn`1be?6=9rB99l:4}oc0eg<728qC>8o;;|lb7de=83;pD?;n4:me6gc290:wE<:a59~jd5fm3:1=vF=5`68ykg4io0;6{ii:h:6=4>{I06e1=zfh9i>7>51zJ11d24?:0yK60g33tdj5ko50;3xL73f<2weml>9:182M42i=1vblo?8;295~N5=h>0qcl:4c83>4}O: ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb_2427 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2428 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o_2441 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11_2445 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o1_2446 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2481 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2483 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2488 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2489 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2502 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2508 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2509 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2510 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2511 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2512 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2513 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2514 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2515 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_2517 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_2518 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_2519 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_2520 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_2521 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_2522 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2536 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2548 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2552 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2553 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2579 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2580 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2581 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2582 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2583 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2584 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2585 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2586 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_2684 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_2685 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_2686 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_2687 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_2876 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_2877 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_2888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_2903 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_3029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_3032 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0_3046 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_3050 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_3133 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_73_o_arb_granularity[3]_equal_16_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_163_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_162_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_3147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_3148 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_3152 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_3216 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_3217 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_3218 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_3219 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_3220 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_3221 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_3222 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_3223 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_3224 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_3225 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_3226 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_3227 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_3228 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_3229 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<0>_3230 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_3232 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_3233 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_3234 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_3235 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_3236 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_3237 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_3238 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_3239 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_3240 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_3241 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_3242 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_3243 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_3244 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_3245 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<0>_3246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_3448 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_3452 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_3456 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_3460 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_3464 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3478 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_3485 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_3486 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_3487 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_3488 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_3489 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_3490 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_3491 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_3492 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_3500 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_3501 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_3512 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3563 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3564 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3574 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3575 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3585 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3586 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_3596 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_3691 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_34_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_3724 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_3731 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_3739 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_3740 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_3929 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_3932 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_3933 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_3934 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_3935 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_3936 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4071 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4072 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_4081 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_4082 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_4083 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_4084 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_4375 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_4376 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_4377 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_4378 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_4379 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_4380 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_4411 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4483 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4484 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_4493 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_4494 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_4497 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_4498 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_4660 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_4661 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_4662 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_4663 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_4754 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_4772 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_4912 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_4913 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_4914 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_4915 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5023 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5180 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5181 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5182 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5183 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5274 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5292 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5429 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5430 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5431 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5432 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5540 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5558 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_5588 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_5619 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_5620 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5814 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5823 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_5832 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_5833 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_5834 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_5835 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_5836 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_5837 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_5838 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_5839 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_5840 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_5841 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_5842 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_5843 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_5844 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_5845 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_5846 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_5847 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_5848 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_5849 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_5850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_282_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_5870 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_5871 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_5877 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_5878 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_5879 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_5880 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_5881 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_5882 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_5883 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_5884 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_5885 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_5886 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_5887 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_5888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_5889 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_303_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_5903 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_5904 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_5912 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_5913 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_5914 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_6150 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_6151 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_6152 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_6153 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_6154 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_6155 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_6156 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_6157 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_6158 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_6159 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_6160 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_6161 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_6162 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_6163 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_6164 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_6165 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_6166 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_6167 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_6168 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_61_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_6188 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_6189 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0>_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1<0>_inv ; - wire N2; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o1_6194 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6195 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o2_6196 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o3_6197 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o4_6198 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6199 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6200 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_6201 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_6202 ; - wire N4; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6205 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6207 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6208 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_6209 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6210 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6211 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6212 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6213 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6214 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6215 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6216 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6217 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6218 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6219 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6220 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_6221 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_6222 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6223 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6224 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6225 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6226 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6227 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6228 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6229 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire N6; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>1 ; - wire N10; - wire N12; - wire N14; - wire N16; - wire N22; - wire N24; - wire N26; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6243 ; - wire N28; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6248 ; - wire N30; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6251 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ; - wire N32; - wire N34; - wire N36; - wire N38; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6259 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6260 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6261 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6262 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6263 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6264 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6265 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6266 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6267 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6268 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6269 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6270 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6271 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6273 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6274 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6275 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6276 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6277 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6278 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6279 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6287 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6288 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6289 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6290 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6291 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6292 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6293 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6294 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6295 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6296 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6297 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6298 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6299 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6300 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6301 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6302 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6303 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6304 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6305 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6306 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6307 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6308 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6309 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6310 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6311 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6312 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6313 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6314 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6315 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6316 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6317 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6318 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6319 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6320 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6321 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6322 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6323 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6324 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6325 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6326 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_rt_6327 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_rt_6328 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_rt_6329 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_rt_6330 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_rt_6331 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_rt_6332 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_rt_6333 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_rt_6334 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_rt_6335 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_rt_6336 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_rt_6337 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_rt_6338 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_rt_6339 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_rt_6340 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_rt_6341 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_rt_6342 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_rt_6343 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_rt_6344 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_rt_6345 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_rt_6346 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_rt_6347 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_rt_6348 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_rt_6349 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_rt_6350 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_rt_6351 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_rt_6352 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_rt_6353 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_rt_6354 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6355 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6356 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6357 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6358 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6359 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6360 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6361 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6362 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6363 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6364 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6365 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6366 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6367 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6368 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6369 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6370 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6371 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6372 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6373 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6374 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6375 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6376 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6377 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6378 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6379 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6380 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6381 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6382 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6383 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6384 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<28>_rt_6385 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<27>_rt_6386 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<26>_rt_6387 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<25>_rt_6388 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<24>_rt_6389 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<23>_rt_6390 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<22>_rt_6391 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<21>_rt_6392 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<20>_rt_6393 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<19>_rt_6394 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<18>_rt_6395 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<17>_rt_6396 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<16>_rt_6397 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<15>_rt_6398 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<14>_rt_6399 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<13>_rt_6400 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<12>_rt_6401 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<11>_rt_6402 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<10>_rt_6403 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<9>_rt_6404 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<8>_rt_6405 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<7>_rt_6406 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<6>_rt_6407 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<5>_rt_6408 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<4>_rt_6409 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<3>_rt_6410 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<2>_rt_6411 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<1>_rt_6412 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6413 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6414 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6415 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6416 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6417 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6418 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6419 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6420 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6421 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6422 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6423 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6424 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6425 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6426 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6427 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6428 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6429 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6430 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6431 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6432 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6433 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6434 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6435 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6436 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6437 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6438 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6439 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6440 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6441 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6442 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<28>_rt_6443 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<27>_rt_6444 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<26>_rt_6445 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<25>_rt_6446 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<24>_rt_6447 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<23>_rt_6448 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<22>_rt_6449 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<21>_rt_6450 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<20>_rt_6451 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<19>_rt_6452 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<18>_rt_6453 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<17>_rt_6454 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<16>_rt_6455 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<15>_rt_6456 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<14>_rt_6457 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<13>_rt_6458 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<12>_rt_6459 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<11>_rt_6460 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<10>_rt_6461 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<9>_rt_6462 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<8>_rt_6463 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<7>_rt_6464 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<6>_rt_6465 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<5>_rt_6466 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<4>_rt_6467 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<3>_rt_6468 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<2>_rt_6469 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<1>_rt_6470 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6471 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6472 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6473 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6474 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6475 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6476 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6477 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6478 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6479 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6480 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6481 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6482 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6483 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6484 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6485 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6486 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6487 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6488 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6489 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6490 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6491 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6492 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6493 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6494 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6495 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6496 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6497 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6498 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6499 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6500 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6501 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6502 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6503 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6504 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6505 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6506 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6507 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6508 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6509 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6510 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6511 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6512 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6513 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6514 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6515 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6516 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6517 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6518 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6519 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6520 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6521 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6522 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6523 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6524 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6525 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6526 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6527 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6528 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6529 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6530 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6531 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6532 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6533 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6534 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6535 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6536 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6537 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6538 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6539 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6540 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6541 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6542 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6543 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6544 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6545 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6546 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6547 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6548 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6549 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6550 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6551 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6552 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6553 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6554 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6555 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6556 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6557 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6558 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6559 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6560 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6561 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6562 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6563 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6564 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6565 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6566 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6567 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6568 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6569 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6570 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6571 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6572 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6573 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6574 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6575 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6576 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6577 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6578 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6579 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6580 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6581 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6582 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6583 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6584 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6585 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6586 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28>_rt_6587 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_6588 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_6589 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6590 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6591 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6592 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6593 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_6594 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6595 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6596 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6597 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_6598 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_6599 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6600 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6601 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6602 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_6603 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_6604 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6605 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6606 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6607 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_6608 ; - wire N41; - wire N43; - wire N44; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_6612 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_6614 ; - wire N48; - wire N50; - wire N52; - wire N54; - wire N56; - wire N58; - wire N60; - wire N62; - wire N64; - wire N66; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_6625 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_6626 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_6627 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_6628 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_6629 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_6630 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_6631 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_6632 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_6633 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_6634 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_6635 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_6636 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_6637 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_6638 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_6639 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_6640 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_6641 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_6642 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_6643 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_6644 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_6645 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_6646 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_6647 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_6648 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_6649 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_6650 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_6651 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_6652 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_6653 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_6654 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_6655 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_6656 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_6657 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_6658 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_6659 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_6660 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31_909 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21_907 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_897 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_896 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_894 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_893 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_891 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_890 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_887 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_885 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_884 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_882 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_881 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_879 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_878 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_876 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_875 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_873 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_872 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_870 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_869 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_867 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_866 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_864 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_863 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_861 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_860 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_858 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_857 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_855 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_854 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_852 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_835 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_834 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_833 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_832 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_831 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_830 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1547 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1545 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1535 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1534 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1532 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1531 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1529 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1528 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1526 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1525 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1523 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1522 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1520 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1519 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1517 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1516 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1514 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1513 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1511 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1510 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1508 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1507 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1505 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1504 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1502 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1501 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1499 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1498 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1496 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1495 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1493 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1492 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1490 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1489 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1479 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1478 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1477 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1476 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1475 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DOUTB[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DOUTB[13] ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire [72 : 72] \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 ; - wire [0 : 0] \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL ; - wire [0 : 0] NlwRenamedSig_OI_m_axis_tstrb; - wire [65 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [44 : 13] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state/next_fwft_state ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [5 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [5 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [28 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [16 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [16 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i ; - wire [6 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload ; - wire [8 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly ; - wire [98 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg ; - wire [27 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [2 : 2] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr ; - wire [7 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg ; - wire [63 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [97 : 97] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 ; - wire [27 : 15] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly ; - wire [0 : 0] NlwRenamedSig_OI_m_axi_aruser; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r ; - wire [64 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ; - wire [9 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [9 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - assign - m_axi_awid[0] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40], - m_axi_awaddr[31] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39], - m_axi_awaddr[30] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38], - m_axi_awaddr[29] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37], - m_axi_awaddr[28] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36], - m_axi_awaddr[27] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35], - m_axi_awaddr[26] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34], - m_axi_awaddr[25] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33], - m_axi_awaddr[24] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32], - m_axi_awaddr[23] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31], - m_axi_awaddr[22] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30], - m_axi_awaddr[21] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29], - m_axi_awaddr[20] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28], - m_axi_awaddr[19] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27], - m_axi_awaddr[18] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26], - m_axi_awaddr[17] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25], - m_axi_awaddr[16] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24], - m_axi_awaddr[15] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23], - m_axi_awaddr[14] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22], - m_axi_awaddr[13] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21], - m_axi_awaddr[12] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20], - m_axi_awaddr[11] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19], - m_axi_awaddr[10] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18], - m_axi_awaddr[9] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17], - m_axi_awaddr[8] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16], - m_axi_awaddr[7] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15], - m_axi_awaddr[6] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14], - m_axi_awaddr[5] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13], - m_axi_awaddr[4] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12], - m_axi_awaddr[3] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11], - m_axi_awaddr[2] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10], - m_axi_awaddr[1] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9], - m_axi_awaddr[0] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8], - m_axi_awlen[7] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7], - m_axi_awlen[6] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6], - m_axi_awlen[5] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5], - m_axi_awlen[4] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4], - m_axi_awlen[3] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3], - m_axi_awlen[2] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2], - m_axi_awlen[1] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1], - m_axi_awlen[0] = \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0], - m_axi_awsize[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awsize[1] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awsize[0] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awburst[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awburst[0] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awlock[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awuser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_wdata[63] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [64], - m_axi_wdata[62] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [63], - m_axi_wdata[61] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [62], - m_axi_wdata[60] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [61], - m_axi_wdata[59] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [60], - m_axi_wdata[58] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [59], - m_axi_wdata[57] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [58], - m_axi_wdata[56] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [57], - m_axi_wdata[55] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [56], - m_axi_wdata[54] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [55], - m_axi_wdata[53] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [54], - m_axi_wdata[52] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [53], - m_axi_wdata[51] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [52], - m_axi_wdata[50] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [51], - m_axi_wdata[49] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [50], - m_axi_wdata[48] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [49], - m_axi_wdata[47] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [48], - m_axi_wdata[46] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [47], - m_axi_wdata[45] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [46], - m_axi_wdata[44] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [45], - m_axi_wdata[43] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [44], - m_axi_wdata[42] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [43], - m_axi_wdata[41] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [42], - m_axi_wdata[40] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [41], - m_axi_wdata[39] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40], - m_axi_wdata[38] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39], - m_axi_wdata[37] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38], - m_axi_wdata[36] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37], - m_axi_wdata[35] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36], - m_axi_wdata[34] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35], - m_axi_wdata[33] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34], - m_axi_wdata[32] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33], - m_axi_wdata[31] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32], - m_axi_wdata[30] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31], - m_axi_wdata[29] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30], - m_axi_wdata[28] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29], - m_axi_wdata[27] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28], - m_axi_wdata[26] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27], - m_axi_wdata[25] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26], - m_axi_wdata[24] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25], - m_axi_wdata[23] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24], - m_axi_wdata[22] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23], - m_axi_wdata[21] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22], - m_axi_wdata[20] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21], - m_axi_wdata[19] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20], - m_axi_wdata[18] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19], - m_axi_wdata[17] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18], - m_axi_wdata[16] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17], - m_axi_wdata[15] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16], - m_axi_wdata[14] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15], - m_axi_wdata[13] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14], - m_axi_wdata[12] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13], - m_axi_wdata[11] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12], - m_axi_wdata[10] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11], - m_axi_wdata[9] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10], - m_axi_wdata[8] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9], - m_axi_wdata[7] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8], - m_axi_wdata[6] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7], - m_axi_wdata[5] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6], - m_axi_wdata[4] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5], - m_axi_wdata[3] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4], - m_axi_wdata[2] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3], - m_axi_wdata[1] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2], - m_axi_wdata[0] = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1], - m_axi_wstrb[7] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[6] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[5] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[4] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[3] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[2] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wuser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arid[0] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40], - m_axi_araddr[31] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39], - m_axi_araddr[30] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38], - m_axi_araddr[29] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37], - m_axi_araddr[28] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36], - m_axi_araddr[27] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35], - m_axi_araddr[26] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34], - m_axi_araddr[25] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33], - m_axi_araddr[24] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32], - m_axi_araddr[23] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31], - m_axi_araddr[22] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30], - m_axi_araddr[21] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29], - m_axi_araddr[20] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28], - m_axi_araddr[19] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27], - m_axi_araddr[18] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26], - m_axi_araddr[17] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25], - m_axi_araddr[16] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24], - m_axi_araddr[15] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23], - m_axi_araddr[14] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22], - m_axi_araddr[13] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21], - m_axi_araddr[12] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20], - m_axi_araddr[11] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19], - m_axi_araddr[10] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18], - m_axi_araddr[9] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17], - m_axi_araddr[8] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16], - m_axi_araddr[7] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15], - m_axi_araddr[6] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14], - m_axi_araddr[5] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13], - m_axi_araddr[4] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12], - m_axi_araddr[3] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11], - m_axi_araddr[2] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10], - m_axi_araddr[1] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9], - m_axi_araddr[0] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8], - m_axi_arlen[7] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7], - m_axi_arlen[6] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6], - m_axi_arlen[5] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5], - m_axi_arlen[4] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4], - m_axi_arlen[3] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3], - m_axi_arlen[2] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2], - m_axi_arlen[1] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1], - m_axi_arlen[0] = \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0], - m_axi_arsize[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arsize[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arsize[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arburst[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arburst[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arlock[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_aruser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axis_tdata[63] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] , - m_axis_tdata[62] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] , - m_axis_tdata[61] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] , - m_axis_tdata[60] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] , - m_axis_tdata[59] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] , - m_axis_tdata[58] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] , - m_axis_tdata[57] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] , - m_axis_tdata[56] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] , - m_axis_tdata[55] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] , - m_axis_tdata[54] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] , - m_axis_tdata[53] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] , - m_axis_tdata[52] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] , - m_axis_tdata[51] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] , - m_axis_tdata[50] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] , - m_axis_tdata[49] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] , - m_axis_tdata[48] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] , - m_axis_tdata[47] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] , - m_axis_tdata[46] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] , - m_axis_tdata[45] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] , - m_axis_tdata[44] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] , - m_axis_tdata[43] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] , - m_axis_tdata[42] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] , - m_axis_tdata[41] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] , - m_axis_tdata[40] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] , - m_axis_tdata[39] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] , - m_axis_tdata[38] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] , - m_axis_tdata[37] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] , - m_axis_tdata[36] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] , - m_axis_tdata[35] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] , - m_axis_tdata[34] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] , - m_axis_tdata[33] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] , - m_axis_tdata[32] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] , - m_axis_tdata[31] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] , - m_axis_tdata[30] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] , - m_axis_tdata[29] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] , - m_axis_tdata[28] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] , - m_axis_tdata[27] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] , - m_axis_tdata[26] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] , - m_axis_tdata[25] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] , - m_axis_tdata[24] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] , - m_axis_tdata[23] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] , - m_axis_tdata[22] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] , - m_axis_tdata[21] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] , - m_axis_tdata[20] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] , - m_axis_tdata[19] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] , - m_axis_tdata[18] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] , - m_axis_tdata[17] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] , - m_axis_tdata[16] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] , - m_axis_tdata[15] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] , - m_axis_tdata[14] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] , - m_axis_tdata[13] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] , - m_axis_tdata[12] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] , - m_axis_tdata[11] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] , - m_axis_tdata[10] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] , - m_axis_tdata[9] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] , - m_axis_tdata[8] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] , - m_axis_tdata[7] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] , - m_axis_tdata[6] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] , - m_axis_tdata[5] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] , - m_axis_tdata[4] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] , - m_axis_tdata[3] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] , - m_axis_tdata[2] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] , - m_axis_tdata[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] , - m_axis_tdata[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] , - m_axis_tstrb[7] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[6] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[5] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[4] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[3] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[2] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tkeep[7] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] , - m_axis_tkeep[6] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] , - m_axis_tkeep[5] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] , - m_axis_tkeep[4] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] , - m_axis_tkeep[3] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] , - m_axis_tkeep[2] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] , - m_axis_tkeep[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] , - m_axis_tkeep[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] , - m_axis_tid[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] , - m_axis_tdest[0] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72], - vfifo_s2mm_channel_full[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [1], - vfifo_s2mm_channel_full[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [0], - vfifo_mm2s_channel_empty[1] = -\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q , - vfifo_mm2s_channel_empty[0] = -\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q , - vfifo_idle[1] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q , - vfifo_idle[0] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q , - m_axi_wlast = \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0], - m_axi_rready = NlwRenamedSig_OI_m_axi_rready, - m_axis_tvalid = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i , - m_axis_tlast = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] , - vfifo_mm2s_rresp_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR , - vfifo_s2mm_bresp_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR , - vfifo_s2mm_overrun_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ; - VCC XST_VCC ( - .P(NlwRenamedSig_OI_m_axis_tstrb[0]) - ); - GND XST_GND ( - .G(NlwRenamedSig_OI_m_axi_aruser[0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2077 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2071 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2084 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2086 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2087 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2089 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2090 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2084 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2148 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2087 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2088 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2090 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2091 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2148 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2085 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2086 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2089 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2085 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2149 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2191 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2070 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2198 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2200 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2201 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2203 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2204 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2198 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2262 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2201 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2202 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2204 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2205 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2262 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2199 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2200 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2203 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2199 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2263 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2300 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2313 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2315 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2316 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2318 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2319 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2313 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2410 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2316 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2317 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2319 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2320 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2410 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2314 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2315 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2318 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2314 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2411 ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0>_inv ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<4> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<5> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<6> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<7> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<8> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb_2427 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2410 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2428 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2078 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2192 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o_2441 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2335 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2489 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state/next_fwft_state [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ) - ); - RAM64X1D #( - .INIT ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1<0>_inv ), - .A1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .A2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .A3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .A4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .A5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_2876 ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .DPRA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .DPRA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .DPRA3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .DPRA4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .DPRA5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2481 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2514 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2488 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2510 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2513 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2489 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2514 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2509 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2508 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2512 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2511 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2515 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2489 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2510 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2509 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2513 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2512 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2515 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2553 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2536 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2548 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2585 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2552 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2581 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2584 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2553 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2585 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2580 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2579 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2583 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2582 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2586 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2553 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2581 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2580 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2584 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2583 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2586 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_2684 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_3032 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_2684 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_2685 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_3029 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_2685 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_2686 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_2686 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_2687 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_2687 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_3133 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_3148 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_162_o ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_163_o ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ) - ); - FD #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tid[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_73 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tkeep[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tlast), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdata[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ), - .D(s_axis_tdest[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_3148 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28>_rt_6587 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6307 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6307 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6308 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6308 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6309 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6309 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6310 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6310 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6311 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6311 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6312 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6312 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6313 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6313 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6314 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6314 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6316 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6316 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6317 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6317 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6318 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6318 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6319 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6319 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6320 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6320 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6321 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6321 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6322 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6322 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6323 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6323 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6324 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6324 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6325 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6325 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6326 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6326 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_3216 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<15> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_3217 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_rt_6327 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_3217 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_rt_6327 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_3216 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_3218 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_rt_6328 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_3218 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_rt_6328 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_3217 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_3219 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_rt_6329 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_3219 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_rt_6329 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_3218 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_3220 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_rt_6330 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_3220 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_rt_6330 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_3219 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_3221 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_rt_6331 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_3221 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_rt_6331 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_3220 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_3222 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_rt_6332 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_3222 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_rt_6332 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_3221 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_3223 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_rt_6333 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_3223 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_rt_6333 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_3222 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_3224 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_rt_6334 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_3224 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_rt_6334 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_3223 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_3225 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_rt_6335 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_3225 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_rt_6335 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_3224 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_3226 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_rt_6336 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_3226 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_rt_6336 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_3225 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_3227 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_rt_6337 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_3227 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_rt_6337 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_3226 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_3228 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_rt_6338 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_3228 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_rt_6338 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_3227 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_3229 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_rt_6339 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_3229 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_rt_6339 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_3228 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<0>_3230 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_rt_6340 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<0>_3230 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_rt_6340 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_3229 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<0>_3230 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_3232 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<15> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_3233 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_rt_6341 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_3233 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_rt_6341 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_3232 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_3234 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_rt_6342 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_3234 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_rt_6342 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_3233 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_3235 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_rt_6343 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_3235 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_rt_6343 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_3234 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_3236 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_rt_6344 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_3236 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_rt_6344 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_3235 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_3237 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_rt_6345 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_3237 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_rt_6345 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_3236 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_3238 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_rt_6346 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_3238 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_rt_6346 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_3237 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_3239 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_rt_6347 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_3239 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_rt_6347 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_3238 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_3240 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_rt_6348 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_3240 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_rt_6348 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_3239 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_3241 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_rt_6349 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_3241 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_rt_6349 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_3240 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_3242 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_rt_6350 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_3242 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_rt_6350 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_3241 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_3243 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_rt_6351 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_3243 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_rt_6351 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_3242 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_3244 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_rt_6352 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_3244 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_rt_6352 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_3243 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_3245 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_rt_6353 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_3245 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_rt_6353 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_3244 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<0>_3246 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_rt_6354 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<0>_3246 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_rt_6354 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_3245 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<0>_3246 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [12]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [1], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_3448 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_3452 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_3456 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_3460 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_3464 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3478 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_3485 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_3487 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_3488 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_3490 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_3491 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_3485 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_3501 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_3488 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_3489 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_3491 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_3492 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_3501 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_3486 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_3487 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_3490 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_3486 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_3500 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .A0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .A1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .A2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .A3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]), - .DPRA0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .DPRA1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .DPRA2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .DPRA3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .SPO -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ) -, - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0] -}), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED -}) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_3512 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2216 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2102 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_3501 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2262 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2186 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2148 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2072 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3563 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3564 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3574 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3575 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3585 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3586 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ), - .D(m_axi_rdata[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_76 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[0] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_66 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_3731 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<3> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [1]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<2> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<1> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [3]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<3> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<2> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [1]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [0]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_34_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]) - ); - FDSE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_34_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]) - ); - FDRE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_3731 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg_1 ( - .C(aclk), - .D(vfifo_mm2s_channel_full[1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg_0 ( - .C(aclk), - .D(vfifo_mm2s_channel_full[0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_3724 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [0]) - ); - FD #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[8].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[9].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[10].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[11].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[12].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[13].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[14].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_6588 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [31]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6355 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [30]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6355 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6356 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [29]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6356 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6357 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6357 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6358 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6358 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6359 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6359 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6360 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6360 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6361 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6361 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6362 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6362 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6363 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6363 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6364 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6364 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6365 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6365 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6366 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6366 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6367 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6367 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6368 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6368 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6369 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6369 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6370 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6370 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6371 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6371 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6372 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6372 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6373 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6373 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6374 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6374 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6375 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6375 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6376 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6376 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6377 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6377 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6378 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6378 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6379 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6379 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6380 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6380 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6381 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6381 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6382 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6382 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6383 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6383 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6384 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6384 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<28>_rt_6385 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<28>_rt_6385 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<27>_rt_6386 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<27>_rt_6386 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<26>_rt_6387 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<26>_rt_6387 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<25>_rt_6388 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<25>_rt_6388 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<24>_rt_6389 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<24>_rt_6389 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<23>_rt_6390 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<23>_rt_6390 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<22>_rt_6391 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<22>_rt_6391 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<21>_rt_6392 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<21>_rt_6392 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<20>_rt_6393 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<20>_rt_6393 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<19>_rt_6394 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<19>_rt_6394 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<18>_rt_6395 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<18>_rt_6395 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<17>_rt_6396 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<17>_rt_6396 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<16>_rt_6397 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<16>_rt_6397 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<15>_rt_6398 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<15>_rt_6398 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<14>_rt_6399 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<14>_rt_6399 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<13>_rt_6400 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<13>_rt_6400 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<12>_rt_6401 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<12>_rt_6401 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<11>_rt_6402 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<11>_rt_6402 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<10>_rt_6403 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<10>_rt_6403 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<9>_rt_6404 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<9>_rt_6404 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<8>_rt_6405 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<8>_rt_6405 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<7>_rt_6406 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<7>_rt_6406 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<6>_rt_6407 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<6>_rt_6407 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<5>_rt_6408 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<5>_rt_6408 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<4>_rt_6409 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<4>_rt_6409 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<3>_rt_6410 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<3>_rt_6410 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<2>_rt_6411 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<2>_rt_6411 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<1>_rt_6412 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<1>_rt_6412 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_3935 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_3929 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_3934 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_3935 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_3933 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_3934 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_3932 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_3933 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_3932 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_3936 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_4082 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4072 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_4081 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4071 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_4084 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_4082 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_4083 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_4081 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_4083 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_4084 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_98 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [98]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_97 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i [97]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [97]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_96 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [96]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_95 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [95]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_94 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [94]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_93 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [93]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_92 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [92]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_91 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [91]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_90 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [90]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_89 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [89]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_88 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [88]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_87 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [87]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_86 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [86]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_85 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [85]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_84 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [84]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_83 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [83]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_82 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [82]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_81 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [81]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_80 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [80]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_79 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [79]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_78 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [78]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_77 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [77]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_76 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [76]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [75]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [74]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_73 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [73]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [72]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [71]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [70]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [69]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [68]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [67]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_66 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [66]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [65]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [1], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [3], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [5], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [7], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [9], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [11], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [13], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [29], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[8].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[9].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[10].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[11].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[12].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[13].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[14].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [15]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms_O_UNCONNECTED ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [4]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [30]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [3]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [27]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [2]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [1]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [0]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [4]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [3]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [2]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [1]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_6589 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [31]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6413 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [30]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6413 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6414 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [29]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6414 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6415 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6415 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6416 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6416 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6417 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6417 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6418 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6418 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6419 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6419 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6420 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6420 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6421 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6421 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6422 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6422 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6423 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6423 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6424 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6424 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6425 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6425 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6426 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6426 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6427 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6427 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6428 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6428 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6429 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6429 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6430 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6430 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6431 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6431 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6432 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6432 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6433 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6433 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6434 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6434 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6435 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6435 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6436 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6436 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6437 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6437 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6438 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6438 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6439 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6439 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6440 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6440 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6441 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6441 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6442 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6442 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<28>_rt_6443 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<28>_rt_6443 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<27>_rt_6444 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<27>_rt_6444 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<26>_rt_6445 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<26>_rt_6445 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<25>_rt_6446 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<25>_rt_6446 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<24>_rt_6447 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<24>_rt_6447 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<23>_rt_6448 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<23>_rt_6448 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<22>_rt_6449 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<22>_rt_6449 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<21>_rt_6450 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<21>_rt_6450 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<20>_rt_6451 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<20>_rt_6451 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<19>_rt_6452 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<19>_rt_6452 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<18>_rt_6453 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<18>_rt_6453 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<17>_rt_6454 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<17>_rt_6454 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<16>_rt_6455 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<16>_rt_6455 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<15>_rt_6456 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<15>_rt_6456 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<14>_rt_6457 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<14>_rt_6457 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<13>_rt_6458 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<13>_rt_6458 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<12>_rt_6459 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<12>_rt_6459 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<11>_rt_6460 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<11>_rt_6460 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<10>_rt_6461 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<10>_rt_6461 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<9>_rt_6462 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<9>_rt_6462 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<8>_rt_6463 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<8>_rt_6463 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<7>_rt_6464 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<7>_rt_6464 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<6>_rt_6465 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<6>_rt_6465 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<5>_rt_6466 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<5>_rt_6466 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<4>_rt_6467 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<4>_rt_6467 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<3>_rt_6468 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<3>_rt_6468 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<2>_rt_6469 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<2>_rt_6469 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<1>_rt_6470 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<1>_rt_6470 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_4380 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_4379 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_4375 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_4378 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_4379 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_4377 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_4378 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_4376 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_4377 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_4376 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_31 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [31]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [31]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_30 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [30]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [30]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_29 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [29]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [29]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_28 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [28]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [28]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_27 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [27]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_26 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [26]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_25 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_24 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_23 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_22 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_21 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_20 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_19 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_18 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_17 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_16 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_31 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [31]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_30 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [30]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_29 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [29]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_28 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [28]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_27 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_26 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_25 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_24 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_23 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_22 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_21 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_20 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_19 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_18 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_17 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_16 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_4411 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_4494 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4484 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_4493 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4483 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_4498 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_4494 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_4497 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_4493 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_4497 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_4498 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6471 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6471 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6472 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6472 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6473 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6473 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6474 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6474 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6475 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6475 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6476 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6476 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6477 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6477 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6478 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6478 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6479 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6479 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6480 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6480 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6481 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6481 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6482 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6482 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6483 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6483 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6484 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6484 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6485 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6485 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6590 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6486 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6486 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6487 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6487 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6488 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6488 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6489 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6489 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6490 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6490 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6491 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6491 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6492 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6492 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6493 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6493 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6494 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6494 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6495 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6495 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6496 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6496 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6497 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6497 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6498 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6498 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6499 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6499 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_4660 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_4661 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_4661 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_4663 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_4660 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_4662 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_4663 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_4662 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_4772 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_2903 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_2876 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6500 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6500 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6501 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6501 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6502 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6502 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6503 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6503 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6504 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6504 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6505 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6505 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6506 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6506 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6507 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6507 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6508 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6508 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6509 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6509 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6510 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6510 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6511 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6511 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6512 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6512 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6513 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6513 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6514 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6514 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6591 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6515 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6515 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6516 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6516 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6517 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6517 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6518 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6518 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6519 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6519 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6520 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6520 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6521 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6521 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6522 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6522 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6523 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6523 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6524 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6524 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6525 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6525 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6526 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6526 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6527 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6527 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6528 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6528 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_4912 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_4913 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_4913 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_4915 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_4912 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_4914 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_4915 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_4914 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5041 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6529 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6529 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6530 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6530 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6531 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6531 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6532 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6532 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6533 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6533 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6534 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6534 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6535 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6535 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6536 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6536 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6537 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6537 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6538 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6538 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6539 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6539 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6540 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6540 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6542 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6542 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6543 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6543 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6592 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6544 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6544 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6545 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6545 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6546 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6546 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6547 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6547 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6548 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6548 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6549 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6549 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6550 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6550 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6551 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6551 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6552 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6552 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6553 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6553 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6554 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6554 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6555 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6555 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6556 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6556 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6557 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6557 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5180 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5181 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5181 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5183 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5180 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5182 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5183 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5182 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5292 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_2888 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_2877 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_2876 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6558 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6558 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6559 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6559 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6560 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6560 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6561 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6561 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6562 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6562 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6563 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6563 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6564 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6564 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6565 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6565 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6566 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6566 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6567 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6567 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6568 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6568 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6569 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6569 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6570 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6570 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6571 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6571 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6572 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6572 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6593 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6573 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6573 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6574 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6574 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6575 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6575 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6576 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6576 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6577 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6577 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6578 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6578 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6579 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6579 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6580 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6580 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6581 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6581 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6582 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6582 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6583 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6583 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6584 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6584 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6585 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6585 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6586 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6586 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5429 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5430 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5430 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5432 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5429 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5431 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5432 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5431 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5558 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [64]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [5]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [4]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [98]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_2903 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [96]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [31]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [95]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [30]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [94]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [29]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [93]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [28]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [92]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [27]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [91]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [26]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [90]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [25]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [89]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [24]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [88]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [23]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [87]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [22]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [86]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [21]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [85]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [20]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [84]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [19]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [83]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [18]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [82]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [17]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [81]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [16]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [80]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [15]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [79]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [14]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [78]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [13]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [77]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [12]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [76]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [11]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [75]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [10]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [74]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [9]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [73]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [72]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [71]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [70]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [69]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [68]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [67]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [66]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [65]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_2876 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .Q(\NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [65]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[14] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[12] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[11] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[10] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[9] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[8] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[7] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[6] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[5] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[4] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[3] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[2] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[0] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[0] ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - 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[0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<8> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<7> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<6> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<5> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<4> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<8> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<7> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<6> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<5> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<4> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<9> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_5833 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_5832 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_5835 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_5834 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_5835 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_5834 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_5833 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_5837 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_5836 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_5837 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_5836 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_5835 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_5839 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_5838 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_5839 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_5838 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_5837 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_5841 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_5840 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_5841 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_5840 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_5839 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_5843 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_5842 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_5843 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_5842 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_5841 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_5845 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_5844 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_5845 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_5844 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_5843 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_5847 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_5846 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_5847 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_5846 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_5845 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_5849 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_5848 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_5849 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0> ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_5848 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_5847 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_5850 ) -, - .S(NlwRenamedSig_OI_m_axi_aruser[0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_5849 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_9 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_8 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_7 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_5870 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_5871 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<5> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<4> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<3> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<2> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_5878 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_5877 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_5880 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_5879 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_5880 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_5879 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_5878 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_5882 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_5881 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_5882 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_5881 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_5880 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_5884 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_5883 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_5884 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_5883 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_5882 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_5886 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_5885 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_5886 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_5885 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_5884 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_5888 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_5887 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_5888 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_5887 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_5886 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_5889 ) -, - .S(NlwRenamedSig_OI_m_axi_aruser[0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_5888 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_5903 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_5904 ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1<0>_inv ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_5913 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_5912 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_5914 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_5913 ) - ); - FDP #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ) - ); - FDP \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/inverted_reset ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_5914 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [36], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [35]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [38], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [37]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [40], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [39]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [29]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [32], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [31]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [34], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [33]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [42], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [41]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [44], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [43]}), - .DIC({NlwRenamedSig_OI_m_axi_aruser[0], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0] -}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]}), - .DOC({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [23]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [25]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [27]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [17]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [19]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [21]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [13]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [15]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]}), - .DIC({NlwRenamedSig_OI_m_axi_aruser[0], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 }), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]}), - .DOC({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [1], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [2]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED }) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [64]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [63]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [62]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [61]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [60]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [59]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [58]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [57]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [56]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [55]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [54]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [53]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [52]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [51]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [50]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [49]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [48]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [47]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [46]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [45]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [44]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [43]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [42]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [41]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [40]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [39]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [38]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [37]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [36]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [35]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [34]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [33]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [32]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [31]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [30]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [29]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [28]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [27]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [26]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [25]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [24]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [23]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [22]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [21]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [20]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [19]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [18]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [17]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [16]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [15]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0]) - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<9> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_6151 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_6150 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_6153 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_6152 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_6153 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_6152 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_6151 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_6155 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_6154 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_6155 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_6154 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_6153 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_6157 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_6156 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_6157 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_6156 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_6155 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_6159 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_6158 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_6159 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_6158 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_6157 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_6161 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_6160 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_6161 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_6160 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_6159 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_6163 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_6162 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_6163 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_6162 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_6161 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_6165 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_6164 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_6165 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_6164 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_6163 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_6167 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_6166 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_6167 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_6166 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_6165 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_6168 ), - .S(NlwRenamedSig_OI_m_axi_aruser[0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_6167 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_9 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_8 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_7 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_6188 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_6189 ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2072 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2086 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2088 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2089 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2091 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2186 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2200 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2202 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2203 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2205 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2315 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2317 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2318 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2320 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_2004 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2428 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_18_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2086 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2087 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_18_o_MUX_3_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2089 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2090 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_18_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2200 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2201 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_18_o_MUX_3_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2203 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2204 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_18_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2315 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2316 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_18_o_MUX_3_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2318 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2319 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<8> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<7> ) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<2> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>12 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<6> ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<3> ) - ); - LUT6 #( - .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11 ) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<5> ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<4> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11_2445 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11_2445 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2481 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I3(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11_2445 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<6> ) - - ); - LUT3 #( - .INIT ( 8'hBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o11 ( - .I0(m_axi_bvalid), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o1_2446 ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_18_o_MUX_3_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2510 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2509 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_18_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2513 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2512 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_18_o_MUX_3_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2581 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2580 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_18_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2584 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2583 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ) - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .I2(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state/next_fwft_state [0]) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2510 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2508 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2513 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2511 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full<0><0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_2519 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_2521 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_2517 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [0]) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full<1><1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_2520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_2522 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_2518 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [1]) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_3029 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2536 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2581 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2579 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2584 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2582 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2097 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2326 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2502 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ) - ); - LUT3 #( - .INIT ( 8'h80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb1 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I2(m_axis_tready), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_mcdf_tvalid1 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(m_axis_tready), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [3]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [2]) - ); - LUT5 #( - .INIT ( 32'h3222F222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_3148 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_3133 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_73_o_arb_granularity[3]_equal_16_o ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_start_of_pkt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_3147 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [1]) - ); - LUT4 #( - .INIT ( 16'h8F88 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_73_o_arb_granularity[3]_equal_16_o ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_3133 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_73_o_arb_granularity[3]_equal_16_o<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_73_o_arb_granularity[3]_equal_16_o ) - ); - LUT3 #( - .INIT ( 8'h10 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_106_o ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ) - ); - LUT4 #( - .INIT ( 16'h2202 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o1 ( - .I0(s_axis_tvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_109_o ) - ); - LUT3 #( - .INIT ( 8'h51 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/s_ready_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .O(s_axis_tready) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_3152 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_111_o ) - ); - LUT6 #( - .INIT ( 64'h0000020000020202 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/valid_to_mtf_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hFD5DA808 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [24]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [10]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [12]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn210 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [11]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [13]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [14]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [15]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [16]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [17]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [19]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [18]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [20]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [21]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [22]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [23]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [26]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [25]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [27]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [28]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [29]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [30]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [3]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [4]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [5]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [6]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [7]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [8]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [9]) - ); - LUT3 #( - .INIT ( 8'hFD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [31]) - ); - LUT3 #( - .INIT ( 8'h2F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt1 ( - .I0(m_axi_bvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<10> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<12> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<14> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [15]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<10> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<12> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<14> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_5754_o_add_12_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_ar_txn11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_2907 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_arcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_bcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/s_axis_tready_arb_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ) - ); - LUT3 #( - .INIT ( 8'h51 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_valid_to_mpf_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_3448 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_3452 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_3456 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_3460 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_3464 ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_18_o_MUX_3_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_3490 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_3491 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_18_o_MUX_3_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_18_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_3487 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_3488 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_18_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_3487 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_3489 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_3490 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_3492 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT4 #( - .INIT ( 16'h0008 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_lut<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_lut<3> ) - - ); - LUT4 #( - .INIT ( 16'h0008 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ) - ); - LUT4 #( - .INIT ( 16'h0008 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [3]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[11] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[14] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ) - ); - LUT6 #( - .INIT ( 64'h8888888828888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<2> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [1]) - ); - LUT4 #( - .INIT ( 16'h96AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/Mxor_n0004_xo<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF01010155 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_34_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_3724 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_34_o ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<3> ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT<3> ) - ); - LUT4 #( - .INIT ( 16'h8288 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<1> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]) - ); - LUT4 #( - .INIT ( 16'h2888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<2> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]) - ); - LUT5 #( - .INIT ( 32'hAAAAAAAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_3740 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_3739 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_addr_gcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_3731 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [0]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_addr_mm2s_cnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_3731 ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ) - ); - LUT4 #( - .INIT ( 16'h8222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut [0]) - ); - LUT6 #( - .INIT ( 64'hAAAA6AAAAA6A6A6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1439_o_add_3_OUT_lut<0> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/Mmux_S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_3724 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<9>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [9]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<8>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [8]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<15>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [15]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<14>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [14]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<13>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [13]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<12>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [12]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<11>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [11]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<10>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [10]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [16]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [17]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [18]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [19]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [20]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [21]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [22]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [23]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [25]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [26]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [27]) - ); - LUT5 #( - .INIT ( 32'hCCCCFA50 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i<31:3>151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [21]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [24]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [25]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]) - ); - LUT5 #( - .INIT ( 32'hFFFFFB73 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int301 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int311 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int321 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4072 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4071 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4072 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4071 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4072 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4071 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4072 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4071 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) - - ); - LUT5 #( - .INIT ( 32'hFFFFFFFB )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_120_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<9>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [19]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [9]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<8>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [8]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<15>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [15]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<14>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [29]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [14]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<13>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [13]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<12>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [12]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<11>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [23]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [11]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<10>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [21]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [10]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>110 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>210 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [14]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [16]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [17]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [18]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [19]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [20]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [21]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [22]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [23]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [25]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [26]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [27]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [28]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [29]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [30]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [9]) - ); - LUT5 #( - .INIT ( 32'hCCCCFA50 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [21]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [24]) - ); - LUT4 #( - .INIT ( 16'hFFE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i<31:3>221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [31]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4484 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4483 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4484 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4483 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4484 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4483 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_4484 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_4483 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) - - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_148_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT4 #( - .INIT ( 16'hA820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT4 #( - .INIT ( 16'hA820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT4 #( - .INIT ( 16'hA820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int18 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'hA8ABA888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [15]) - ); - LUT4 #( - .INIT ( 16'h080C )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ) - ); - LUT5 #( - .INIT ( 32'h28280A28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_164_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT4 #( - .INIT ( 16'hA820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT4 #( - .INIT ( 16'hA820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT4 #( - .INIT ( 16'hA820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int18 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT4 #( - .INIT ( 16'hE400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'hA8ABA888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [15]) - ); - LUT4 #( - .INIT ( 16'h080C )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ) - ); - LUT5 #( - .INIT ( 32'h28280A28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_159_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_113_o ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [4]) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [5]) - ); - LUT3 #( - .INIT ( 8'h7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ) - ); - LUT5 #( - .INIT ( 32'hA9AAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [6]) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [3]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [3]) - ); - LUT6 #( - .INIT ( 64'h7DF5F5F5F5F5F5F5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ) - ); - LUT5 #( - .INIT ( 32'h8000FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [6]) - ); - LUT5 #( - .INIT ( 32'hA9AAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_5620 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]) - ); - LUT4 #( - .INIT ( 16'hFFEA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_5619 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ) - ); - LUT5 #( - .INIT ( 32'hFFFFFF80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_5620 ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n02851 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [2]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_176_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5814 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<6> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5814 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<7> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5814 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<8> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5823 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<6> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5823 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<7> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5823 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<8> ) - ); - LUT6 #( - .INIT ( 64'h0000000008000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_303_o_equal_7_o<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_303_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<3> ) - - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<5> ) - - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_7083_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_7083_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_7083_o_add_0_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/rstblk/Mmux_wr_rst_asreg_GND_10_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_5914 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_5913 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_5914 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_5912 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ) - ); - LUT6 #( - .INIT ( 64'h0727022202220222 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2428 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2411 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_2004 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb_2427 ) - ); - LUT6 #( - .INIT ( 64'hCEFF8AAA8AAA8AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2335 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2428 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_2004 ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .I5(N2), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o_2441 ) - ); - LUT5 #( - .INIT ( 32'hDDFDD0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_3029 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2536 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o1_6194 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o ) - ); - LUT6 #( - .INIT ( 64'h5C5C505000500050 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2552 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_3029 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2536 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6195 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o2_6196 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o3_6197 ) - - ); - LUT6 #( - .INIT ( 64'hCEFF8AAA8AAA8AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o2_6196 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o4_6198 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6199 ) - ); - LUT5 #( - .INIT ( 32'h00009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6200 ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_6201 ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_6202 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt2_SW0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .O(N4) - ); - LUT6 #( - .INIT ( 64'h00200222FFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I1(N4), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6205 ) - ); - LUT6 #( - .INIT ( 64'h0001000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6207 ) - ); - LUT6 #( - .INIT ( 64'h0004000455550004 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo13 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6207 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]) - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6208 ) - - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_6209 ) - - ); - LUT4 #( - .INIT ( 16'h22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6210 ) - - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6212 ) - - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6213 ) - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6214 ) - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6215 ) - ); - LUT4 #( - .INIT ( 16'h22F2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6216 ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6217 ) - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6218 ) - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6219 ) - ); - LUT4 #( - .INIT ( 16'h22F2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6220 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFAEAEFFAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_6209 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6208 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_6221 ) - - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_6222 ) - - ); - LUT5 #( - .INIT ( 32'h33B300B0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_6221 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_3500 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6223 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6224 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFAEAEFFAE )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6215 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6214 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6226 ) - ); - LUT5 #( - .INIT ( 32'h33B300B0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6226 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2186 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2263 ), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6225 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6227 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFAEAEFFAE )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6219 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6218 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6229 ) - ); - LUT5 #( - .INIT ( 32'h33B300B0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6229 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2072 ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2149 ), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6228 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT6 #( - .INIT ( 64'h444444444444444E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_read_fifo1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_3596 ), - .I2(N6), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[10] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[11] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[12] ), - .O(N10) - ); - LUT6 #( - .INIT ( 64'h0000000000000002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[8] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ), - .I5(N10), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_3596 ) - ); - LUT5 #( - .INIT ( 32'hFFFF6FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<1>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .O(N12) - ); - LUT6 #( - .INIT ( 64'h0041410000001111 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<1>1 ( - .I0(N12), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [1]) - ); - LUT5 #( - .INIT ( 32'hFFFFFF6F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<0>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(N14) - ); - LUT6 #( - .INIT ( 64'h0041410000001111 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<0>1 ( - .I0(N14), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFF6A6FFA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I5(N16), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_3691 ) - ); - LUT5 #( - .INIT ( 32'hFFFFFFF4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [24]), - .O(N22) - ); - LUT6 #( - .INIT ( 64'hFFFFAAAAFFFEAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [28]), - .I5(N22), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i<97>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(N24) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i<97> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(N24), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i [97]) - ); - LUT5 #( - .INIT ( 32'hFFFFFFF4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [24]), - .O(N26) - ); - LUT6 #( - .INIT ( 64'hFFFFAAAAFFFEAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [28]), - .I5(N26), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6243 ) - - ); - LUT4 #( - .INIT ( 16'hFDDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6243 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'h8D80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int7_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(N28) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h15FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6246 ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6246 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6248 ) - - ); - LUT4 #( - .INIT ( 16'hFDDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6248 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'h8D80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int7_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(N30) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h15FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6251 ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6251 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'hAAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_3050 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [97]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ) - ); - LUT2 #( - .INIT ( 4'h7 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .O(N32) - ); - LUT6 #( - .INIT ( 64'hAAAA6AAAFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(N32), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_5588 ) - ); - LUT6 #( - .INIT ( 64'h8808AAAAFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe [0]) - ); - LUT3 #( - .INIT ( 8'h8F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<0>2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<1>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .O(N34) - ); - LUT6 #( - .INIT ( 64'hAA2A2A2AFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<1> ( - .I0(N34), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [5]) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_282_o_equal_7_o<8>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .O(N36) - ); - LUT6 #( - .INIT ( 64'h0000000080000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_282_o_equal_7_o<8> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I5(N36), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_282_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_61_o_equal_7_o<8>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .O(N38) - ); - LUT6 #( - .INIT ( 64'h0000000080000000 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_61_o_equal_7_o<8> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]), - .I5(N38), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_61_o_equal_7_o ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6259 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6260 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6261 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6262 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_2518 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6263 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_2517 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6264 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_2520 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6265 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_2519 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6266 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_2522 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6267 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_2521 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6268 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6269 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6270 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_3152 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_3050 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6271 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_3152 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6273 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6274 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6275 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6276 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6277 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_3740 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6278 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_3739 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6279 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6287 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6288 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6290 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6292 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6293 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6294 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6295 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6296 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6297 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6298 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6299 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6300 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6301 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6302 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6303 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6304 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_5620 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6305 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6306 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_5619 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_2004 ) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [5]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [0]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6307 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6308 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6309 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6310 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6311 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6312 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6313 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6314 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6315 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6316 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6317 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6318 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6319 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6320 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6321 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6322 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6323 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6324 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6325 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6326 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<14>_rt_6327 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<13>_rt_6328 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<12>_rt_6329 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<11>_rt_6330 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<10>_rt_6331 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<9>_rt_6332 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<8>_rt_6333 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<7>_rt_6334 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<6>_rt_6335 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<5>_rt_6336 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<4>_rt_6337 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<3>_rt_6338 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<2>_rt_6339 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_cy<1>_rt_6340 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<14>_rt_6341 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<13>_rt_6342 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<12>_rt_6343 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<11>_rt_6344 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<10>_rt_6345 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<9>_rt_6346 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<8>_rt_6347 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<7>_rt_6348 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<6>_rt_6349 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<5>_rt_6350 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<4>_rt_6351 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<3>_rt_6352 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<2>_rt_6353 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_cy<1>_rt_6354 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6355 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6356 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6357 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6358 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6359 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6360 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6361 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6362 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6363 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6364 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6365 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6366 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6367 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6368 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6369 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6370 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6371 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6372 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6373 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6374 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6375 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6376 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6377 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6378 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6379 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6380 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6381 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6382 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6383 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6384 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<28>_rt_6385 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<27>_rt_6386 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<26>_rt_6387 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<25>_rt_6388 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<24>_rt_6389 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<23>_rt_6390 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<22>_rt_6391 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<21>_rt_6392 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<20>_rt_6393 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<19>_rt_6394 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<18>_rt_6395 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<17>_rt_6396 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<16>_rt_6397 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<15>_rt_6398 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<14>_rt_6399 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<13>_rt_6400 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<12>_rt_6401 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<11>_rt_6402 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<10>_rt_6403 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<9>_rt_6404 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<8>_rt_6405 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<7>_rt_6406 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<6>_rt_6407 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<5>_rt_6408 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<4>_rt_6409 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<3>_rt_6410 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<2>_rt_6411 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_cy<1>_rt_6412 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6413 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6414 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6415 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6416 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6417 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6418 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6419 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6420 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6421 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6422 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6423 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6424 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6425 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6426 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6427 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6428 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6429 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6430 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6431 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6432 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6433 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6434 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6435 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6436 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6437 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6438 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6439 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6440 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6441 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6442 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<28>_rt_6443 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<27>_rt_6444 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<26>_rt_6445 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<25>_rt_6446 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<24>_rt_6447 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<23>_rt_6448 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<22>_rt_6449 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<21>_rt_6450 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<20>_rt_6451 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<19>_rt_6452 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<18>_rt_6453 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<17>_rt_6454 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<16>_rt_6455 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<15>_rt_6456 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<14>_rt_6457 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<13>_rt_6458 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<12>_rt_6459 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<11>_rt_6460 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<10>_rt_6461 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<9>_rt_6462 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<8>_rt_6463 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<7>_rt_6464 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<6>_rt_6465 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<5>_rt_6466 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<4>_rt_6467 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<3>_rt_6468 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<2>_rt_6469 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_cy<1>_rt_6470 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6471 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6472 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6473 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6474 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6475 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6476 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6477 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6478 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6479 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6480 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6481 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6482 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6483 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6484 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6485 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6486 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6487 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6488 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6489 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6490 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6491 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6492 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6493 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6494 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6495 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6496 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6497 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6498 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6499 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6500 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6501 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6502 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6503 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6504 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6505 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6506 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6507 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6508 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6509 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6510 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6511 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6512 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6513 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6514 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6515 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6516 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6517 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6518 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6519 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6520 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6521 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6522 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6523 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6524 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6525 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6526 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6527 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6528 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<15>_rt_6529 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<14>_rt_6530 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<13>_rt_6531 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<12>_rt_6532 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<11>_rt_6533 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<10>_rt_6534 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<9>_rt_6535 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<8>_rt_6536 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<7>_rt_6537 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<6>_rt_6538 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<5>_rt_6539 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<4>_rt_6540 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<3>_rt_6541 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<2>_rt_6542 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy<1>_rt_6543 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6544 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6545 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6546 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6547 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6548 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6549 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6550 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6551 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6552 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6553 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6554 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6555 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6556 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6557 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<15>_rt_6558 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<14>_rt_6559 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<13>_rt_6560 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<12>_rt_6561 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<11>_rt_6562 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<10>_rt_6563 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<9>_rt_6564 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<8>_rt_6565 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<7>_rt_6566 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<6>_rt_6567 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<5>_rt_6568 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<4>_rt_6569 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<3>_rt_6570 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<2>_rt_6571 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy<1>_rt_6572 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6573 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6574 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6575 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6576 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6577 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6578 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6579 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6580 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6581 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6582 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6583 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6584 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6585 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6586 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28>_rt_6587 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_6588 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_6589 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6590 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6591 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6592 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_6593 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_6594 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_3147 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6595 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_3501 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6596 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2262 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6597 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2148 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2097 ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_6598 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_2888 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_6599 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_2877 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6600 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2553 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6601 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2489 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2502 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6602 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2410 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2326 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_6603 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ) - ); - FD \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_6604 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6605 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6606 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6607 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_6608 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6261 ) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [6]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [5]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [4]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [3]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [2]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [1]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [19]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [25]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [19]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [17]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int311 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [17]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F0FCB87430 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [21]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F0FCB87430 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [21]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [20]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [20]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [12]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [18]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27]) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int321 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'hFFFFFB73 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [18]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [12]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6281 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/n0174 [22]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int301 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [22]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_4477 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/n0075 [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT5 #( - .INIT ( 32'h22200200 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT5 #( - .INIT ( 32'h22200200 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT5 #( - .INIT ( 32'h22200200 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT5 #( - .INIT ( 32'h22200200 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT5 #( - .INIT ( 32'h22200200 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT5 #( - .INIT ( 32'h22200200 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT5 #( - .INIT ( 32'h0000C840 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT5 #( - .INIT ( 32'hA8ABA888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [15]) - ); - LUT5 #( - .INIT ( 32'hA8ABA888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [15]) - ); - LUT5 #( - .INIT ( 32'h0000008C )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data1 ( - .I0(m_axis_tready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT5 #( - .INIT ( 32'h81092103 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_5754_o_add_14_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF55575555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<0>1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(m_axi_bvalid), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .O(N41) - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<1>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .I2(m_axi_bvalid), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .O(N43) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF555D5555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<1>1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(m_axi_bvalid), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .O(N44) - ); - LUT6 #( - .INIT ( 64'hAA00BA10AA00AA00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(N43), - .I4(N44), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6273 ) - ); - LUT4 #( - .INIT ( 16'h0001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I3(N41), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_6612 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_cy ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_6612 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_cy1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_6614 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [0]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [10]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [11]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [12]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [13]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [14]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [1]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [2]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [3]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [4]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [5]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [6]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [7]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [8]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [9]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [0]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [10]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [11]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [12]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [13]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [14]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [1]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [2]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [3]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [4]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [5]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [6]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [7]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [8]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6285 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/wr_data_i [9]) - ); - LUT5 #( - .INIT ( 32'hFF3AFF00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'hFF3AFF00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'h45044444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2552 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_5870 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_5871 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_282_o_equal_7_o ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6600 ) - ); - LUT5 #( - .INIT ( 32'h45044444 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2411 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2326 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_6188 ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_6189 ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_61_o_equal_7_o ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6602 ) - ); - LUT5 #( - .INIT ( 32'hFFFF888A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6303 ) - ); - LUT6 #( - .INIT ( 64'hFFFF222A222A222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_2888 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_6598 ) - ); - LUT5 #( - .INIT ( 32'hF3FFA2AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_5620 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6304 ) - ); - LUT4 #( - .INIT ( 16'hCF8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_5619 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6306 ) - ); - LUT5 #( - .INIT ( 32'h45044444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_3500 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3563 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3564 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6595 ) - - ); - LUT5 #( - .INIT ( 32'h45044444 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2263 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3574 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3575 ), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6596 ) - ); - LUT5 #( - .INIT ( 32'h45044444 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2149 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2097 ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3585 ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3586 ), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_40_o_equal_7_o ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6597 ) - ); - LUT5 #( - .INIT ( 32'h45044444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2488 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2502 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_5903 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_5904 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_303_o_equal_7_o ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_6601 ) - ); - LUT6 #( - .INIT ( 64'hAA8AAA8AAADFAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6205 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6274 ) - ); - LUT4 #( - .INIT ( 16'h7D28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6295 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6296 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6297 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6298 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6299 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6300 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6301 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6302 ) - ); - LUT6 #( - .INIT ( 64'h7DDDDDDD6CCCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6289 ) - ); - LUT5 #( - .INIT ( 32'h6FAF6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6291 ) - ); - LUT4 #( - .INIT ( 16'h5410 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_5588 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6287 ) - ); - LUT4 #( - .INIT ( 16'h5410 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6288 ) - ); - LUT5 #( - .INIT ( 32'hFFFF8880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set ( - .I0(NlwRenamedSig_OI_m_axi_rready), - .I1(m_axi_rvalid), - .I2(m_axi_rresp[0]), - .I3(m_axi_rresp[1]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6259 ) - ); - LUT5 #( - .INIT ( 32'hDDDF8880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_2877 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_6599 ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_5846 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_6164 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_5844 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_6162 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_5842 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_6160 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_5840 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_5885 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_6158 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_5838 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_5883 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_6156 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_5836 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_5881 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_6154 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_5834 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_5879 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_6152 ) - - ); - LUT5 #( - .INIT ( 32'h0004FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .I1(m_axi_bvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_6614 ) - ); - LUT4 #( - .INIT ( 16'hBA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6606 ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_5832 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_5877 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_6150 ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set ( - .I0(s_axis_tvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6270 ) - ); - LUT5 #( - .INIT ( 32'hFFFF4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .I1(m_axi_bvalid), - .I2(m_axi_bresp[0]), - .I3(m_axi_bresp[1]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6260 ) - ); - LUT6 #( - .INIT ( 64'hBBABAAAA88A8AAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_2860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .I3(m_axi_bvalid), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2483 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_6603 ) - ); - LUT6 #( - .INIT ( 64'h0444044404441454 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I3(N48), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_3596 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_6604 ) - ); - LUT6 #( - .INIT ( 64'h2000FFFF20002000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(N50), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_3740 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6277 ) - ); - LUT6 #( - .INIT ( 64'hF444444444444444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_3739 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I5(N52), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6278 ) - ); - LUT6 #( - .INIT ( 64'hF3FF0C00FFAF0050 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>1 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]) - ); - LUT5 #( - .INIT ( 32'h80000080 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6199 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6200 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(N54) - ); - LUT6 #( - .INIT ( 64'hFFFF02FF22220222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2488 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o1_2446 ) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ), - .I5(N54), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT6 #( - .INIT ( 64'hE11E8778E11EE11E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .O(N56) - ); - LUT6 #( - .INIT ( 64'h0000000000004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I5(N56), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_3724 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_next_state1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .O(N58) - ); - LUT6 #( - .INIT ( 64'hFF88FF88FF887F88 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_next_state1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I5(N58), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ) - ); - LUT6 #( - .INIT ( 64'hE11E8778E11EE11E )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'hE11E8778E11EE11E )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAAAAAAAAA8A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2216 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6215 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6216 ), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2186 ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6214 ), - .O(N60) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAAAAAAAA8A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2102 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6219 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6220 ), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2072 ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6218 ), - .O(N62) - ); - LUT6 #( - .INIT ( 64'hFAFACC00FFFFCC00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>1 ) - ); - LUT6 #( - .INIT ( 64'hA5D2A5F0F0D2F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [7]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_5848 ) - - ); - LUT5 #( - .INIT ( 32'hA8FFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[4] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [5]) - ); - LUT5 #( - .INIT ( 32'hFEFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[4] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [1]) - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [2]) - ); - LUT5 #( - .INIT ( 32'hFDDDFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[4] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [3]) - ); - LUT3 #( - .INIT ( 8'hBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [4]) - ); - LUT4 #( - .INIT ( 16'h8FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [6]) - ); - LUT5 #( - .INIT ( 32'h80FFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[4] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[6] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [7]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h5551 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2102 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2078 ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2077 ), - .I3(m_axi_awready), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h5551 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2216 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2192 ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2191 ), - .I3(m_axi_arready), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_rom_rd_addr_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_addr_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h5551 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2335 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ), - .I3(m_axi_wready), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ) - ); - LUT5 #( - .INIT ( 32'hAAAAA8AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_161_o ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT5 #( - .INIT ( 32'h11015555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/s_ready_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(m_axis_tready), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ), - .O(NlwRenamedSig_OI_m_axi_rready) - ); - LUT4 #( - .INIT ( 16'h2888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [0]) - ); - LUT6 #( - .INIT ( 64'hA9AAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_5620 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [2]) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_6166 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_5887 ) - - ); - LUT5 #( - .INIT ( 32'h28888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_cy<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1439_o_add_5_OUT_lut<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [3]) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA00000008 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_3740 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ) - ); - LUT5 #( - .INIT ( 32'h44444044 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_143_o ) - ); - LUT6 #( - .INIT ( 64'hF7FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<6>11_2445 ) - - ); - LUT6 #( - .INIT ( 64'hF7FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5814 ) - - ); - LUT6 #( - .INIT ( 64'hF7FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<6>11_5823 ) - ); - LUT3 #( - .INIT ( 8'hFD )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ), - .I2(m_axi_wready), - .O(N2) - ); - LUT4 #( - .INIT ( 16'h02FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ) - ); - LUT4 #( - .INIT ( 16'h80FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid1 ( - .I0(m_axis_tready), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ) - ); - LUT3 #( - .INIT ( 8'hF8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ) - ); - LUT6 #( - .INIT ( 64'h0202000222222222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o1 ( - .I0(m_axi_rvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I4(m_axis_tready), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_214_o ) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_113_o ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2192 ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2191 ), - .I3(m_axi_arready), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2078 ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2077 ), - .I3(m_axi_awready), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ), - .I3(m_axi_wready), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ) - ); - LUT3 #( - .INIT ( 8'h54 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2078 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2077 ), - .I2(m_axi_awready), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - ); - LUT3 #( - .INIT ( 8'h54 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2192 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2191 ), - .I2(m_axi_arready), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - ); - LUT3 #( - .INIT ( 8'h54 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ), - .I2(m_axi_wready), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - ); - LUT4 #( - .INIT ( 16'h02FF )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2078 ), - .I1(m_axi_awready), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2077 ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2102 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h02FF )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2192 ), - .I1(m_axi_arready), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2191 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2216 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h02FF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ), - .I1(m_axi_wready), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2335 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I3(m_axi_bvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_865_o_add_0_OUT<1> ) - - ); - LUT5 #( - .INIT ( 32'hAAEAAA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_tstart_reg[0]_tstart_reg[0]_MUX_163_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_163_o ) - ); - LUT5 #( - .INIT ( 32'hEAAA2AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_tstart_reg[1]_tstart_reg[1]_MUX_162_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_162_o ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<2> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<3> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_27_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_27_o_add_0_OUT<1> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<2> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<3> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_36_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_36_o_add_0_OUT<1> ) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F200000002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/Mmux_S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_3739 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ) - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<4> ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<5> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<3> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<2> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<1> ) - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<4> ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<5> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<3> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<2> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_854_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_854_o_add_0_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<3> ) - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<4> ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<5> ) - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[5]_GND_7077_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<2> ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[5]_GND_7077_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_7077_o_add_0_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'hEA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_3147 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_6594 ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4688 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4689 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT112 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_4940 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_4941 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5208 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5209 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT112 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5457 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5458 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [2]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [1]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [14]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [13]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [12]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [11]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [10]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i18 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [0]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [9]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [8]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [7]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [6]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [5]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [4]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6284 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [3]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [2]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [1]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [14]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [13]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [12]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [11]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [10]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i18 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [0]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [9]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [8]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [7]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [6]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [5]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [4]) - ); - LUT6 #( - .INIT ( 64'h5151510000510000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6286 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/wr_data_i [3]) - ); - LUT5 #( - .INIT ( 32'hA280F7D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .I3(N28), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT5 #( - .INIT ( 32'hA280F7D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .I3(N30), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT4 #( - .INIT ( 16'hF0D0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_18_o1_6194 ) - - ); - LUT4 #( - .INIT ( 16'hAAAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6195 ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ) - ); - LUT4 #( - .INIT ( 16'h555D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h2B2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2548 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF7FFFFF7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_SW0 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I2(m_axis_tready), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .O(N16) - ); - LUT5 #( - .INIT ( 32'hAAAA222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6289 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6290 ) - ); - LUT5 #( - .INIT ( 32'hAAAA222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6291 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6292 ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [5]) - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [4]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF00080800 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_6212 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6211 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT5 #( - .INIT ( 32'h222F222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ) - ); - LUT4 #( - .INIT ( 16'h2B2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3478 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h02FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_3512 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT6 #( - .INIT ( 64'hFFFFA8FFFFFEA8AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ) - ); - LUT6 #( - .INIT ( 64'hAFACAAA8AAA8AAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h0880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp03 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_6201 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_6202 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAAAAAAAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_3512 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_6210 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_6209 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6208 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_6211 ) - - ); - LUT6 #( - .INIT ( 64'h0082820000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_6222 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_6223 ) - - ); - LUT6 #( - .INIT ( 64'h0082820000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6224 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6225 ) - ); - LUT6 #( - .INIT ( 64'h0082820000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_6227 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_6228 ) - ); - LUT5 #( - .INIT ( 32'h51500100 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_6608 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFEAA2EAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_3024 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_3752 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6279 ) - ); - LUT5 #( - .INIT ( 32'hFFFF0020 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6305 ) - ); - LUT6 #( - .INIT ( 64'h7B6A7B6A3322336A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I5(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6293 ) - ); - LUT5 #( - .INIT ( 32'h76765456 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6294 ) - ); - LUT4 #( - .INIT ( 16'h287D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]) - ); - LUT6 #( - .INIT ( 64'hA3ACACACACACAC5C )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[12] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_4375 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_4411 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_2518 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_3929 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6262 ) - ); - LUT5 #( - .INIT ( 32'hDDDD0D00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_4411 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_4375 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_3929 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_3936 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_2517 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6263 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5540 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5558 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_2520 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5274 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5292 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6264 ) - ); - LUT5 #( - .INIT ( 32'hDDDD0D00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5558 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5274 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5292 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_2519 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6265 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5023 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5041 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_2522 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_4754 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_4772 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6266 ) - ); - LUT5 #( - .INIT ( 32'hDDDD0D00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5041 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5023 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_4754 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_4772 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_2521 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6267 ) - ); - LUT6 #( - .INIT ( 64'hFFF0FFFF22202222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_4380 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_4377 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_3933 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6268 ) - ); - LUT6 #( - .INIT ( 64'hF0FFFFFF80888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_4377 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_4380 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_3933 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6269 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFA8A8AAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I4(m_axis_tready), - .I5(m_axi_rvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6275 ) - ); - LUT6 #( - .INIT ( 64'h0000000000000002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .O(N48) - ); - LUT6 #( - .INIT ( 64'h4444444444444044 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_184_o ) - ); - LUT5 #( - .INIT ( 32'h44444044 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - LUT5 #( - .INIT ( 32'hFFFFAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ) - ); - LUT4 #( - .INIT ( 16'h5515 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I3(m_axi_bvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA88888088 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_5618 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_2878 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hAAA2AAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n02981 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2924 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_5560 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ) - ); - LUT4 #( - .INIT ( 16'h5551 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ) - ); - LUT5 #( - .INIT ( 32'h28280A28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT5 #( - .INIT ( 32'h28280A28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT6 #( - .INIT ( 64'h6656565666665666 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT6 #( - .INIT ( 64'h6656565666665666 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT5 #( - .INIT ( 32'h444444F4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set ( - .I0(m_axis_tready), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_3625 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6276 ) - ); - LUT5 #( - .INIT ( 32'h69996669 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT5 #( - .INIT ( 32'h69996669 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT5 #( - .INIT ( 32'h69996669 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'h8288D7DDD7DD8288 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[8] ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [1]) - ); - LUT4 #( - .INIT ( 16'hFCA0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>1 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]) - ); - LUT5 #( - .INIT ( 32'hAAEAAA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2823 ), - .I1(m_axis_tready), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6605 ) - ); - LUT6 #( - .INIT ( 64'hAAAABBABAAAA88A8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2573 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_3520 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_6607 ) - ); - LUT4 #( - .INIT ( 16'h1110 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_3691 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(N50) - ); - LUT4 #( - .INIT ( 16'h1101 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_2211 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_3517 ) -, - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_3691 ), - .O(N52) - ); - LUT6 #( - .INIT ( 64'h2020202022202020 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2465 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2496 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2479 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2480 ), - .I5(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_5889 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF00080800 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6213 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5(N60), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF00080800 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_6217 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5(N62), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - ); - LUT4 #( - .INIT ( 16'h5551 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_3512 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h5444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_3148 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_111_o ) - ); - LUT6 #( - .INIT ( 64'h6656565666665666 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT6 #( - .INIT ( 64'h6656565666665666 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_cy [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/n0058 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/ram_init_done_i_4520 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT6 #( - .INIT ( 64'h2020202020222020 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_3029 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2536 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2563 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2587 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2547 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_5850 ) - - ); - LUT6 #( - .INIT ( 64'h2020202020222020 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_2004 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2428 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2335 ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2312 ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2311 ), - .I5(m_axi_wready), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_6168 ) - ); - LUT6 #( - .INIT ( 64'h8200008200000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o1_2446 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o3_6197 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_170_o4_6198 ) - - ); - LUT5 #( - .INIT ( 32'hFEFFA8AA )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2072 ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(N64) - ); - LUT5 #( - .INIT ( 32'h99696966 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I4(N64), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAA9FFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [3]) - ); - LUT5 #( - .INIT ( 32'hFEFFA8AA )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2186 ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(N66) - ); - LUT5 #( - .INIT ( 32'h99696966 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I4(N66), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFEF4F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_read_fifo1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .O(N6) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAAA8888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_5621 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6253 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ) - ); - LUT6 #( - .INIT ( 64'h8888882888888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_3693 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_3736 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [2]) - ); - LUT6 #( - .INIT ( 64'h002022A2AABABBFB )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT6 #( - .INIT ( 64'hAA6A6A6666565655 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_lut<3> ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - LUT5 #( - .INIT ( 32'hFFF8F8F8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_3166 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_3151 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_3148 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_5725 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_3152 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6271 ) - ); - LUT5 #( - .INIT ( 32'h66666966 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT5 #( - .INIT ( 32'h66666966 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2186 ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT5 #( - .INIT ( 32'h66666966 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6283 ), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2072 ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT6 #( - .INIT ( 64'h002022A2AABABBFB )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT6 #( - .INIT ( 64'h002022A2AABABBFB )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT6 #( - .INIT ( 64'h2020202020222020 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_2906 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_3473 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_3512 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_3519 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3479 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'hAAAA33CCA5A5CCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[9] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_3598 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>1 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2483 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_6625 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_6625 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2483 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_5754_o_add_14_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_5754_o_add_12_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_n0174_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_n0075_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_n0058_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_n0058_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/inverted_reset1_INV_0 ( - .I(aresetn), - .O(\U0/xst_axi_vfifo_ctrl/inverted_reset ) - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2070 ), - .O(m_axi_arvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2071 ), - .O(m_axi_awvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/w_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2300 ), - .O(m_axi_wvalid) - ); - INV - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0>_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_2516 ), - .O(m_axi_bready) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mcount_reset_addr_0_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_3376 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_3377 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mcount_reset_addr_0_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_3731 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_3730 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/rd_pntr_wr_inv_pad<9:1><0>1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/rd_pntr_wr_inv_pad<6:1><0>1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_7083_o_add_0_OUT_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1<0>_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/rd_pntr_wr_inv_pad<9:1><0>1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0> ) - - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_3753 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15 ( - .A0(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_6626 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_6626 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_6627 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2770 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_6628 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_6628 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_6629 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3 ( - .A0(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_6630 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_6630 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_6631 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_6632 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_6632 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_6633 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_6634 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_6634 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_6635 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_2665 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_6636 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_6636 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_6637 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_6638 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_6638 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_6639 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_6639 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_6640 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_6640 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_6641 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_6631 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_6640 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_6642 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_6642 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0_3046 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_6637 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_6641 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_6643 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_6643 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5540 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_6635 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_6641 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_6644 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_6644 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5274 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_6629 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_6641 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_6645 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_6645 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5023 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_6633 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_6641 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_6646 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_6646 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_4754 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_6647 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_6647 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_6648 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_6648 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_6649 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_6649 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_6650 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_6650 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_6651 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_6651 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_6652 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_6652 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_6653 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_6653 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_6654 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_6654 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_6655 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_6655 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_6656 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_6656 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_6657 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_6657 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_6658 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_6658 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_6659 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_6627 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_6659 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_6660 ) - ); - FDPE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_6660 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_894 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_893 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_888 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_887 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_897 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_896 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_891 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_890 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_10 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_882 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_881 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_9 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_876 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_875 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_10 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_885 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_884 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_870 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_869 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_873 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_872 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_9 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_879 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_878 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_864 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_863 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_867 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_866 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_857 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_860 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_855 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_854 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_831 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_830 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_832 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_852 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_851 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_834 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_833 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_835 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_10 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_9 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_835 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_832 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31_909 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31_909 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21_907 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21_907 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2735 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2736 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_13 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_13 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_13 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_897 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_896 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_894 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_893 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_891 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_890 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_888 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_887 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_885 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_884 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_882 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_881 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_879 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_878 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_876 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_875 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_873 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_872 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_870 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_869 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_867 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_866 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_864 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_863 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_861 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_860 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_858 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_857 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_855 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_854 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_852 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_851 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_834 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_833 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_831 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_830 ) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ), - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ), - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .INJECTDBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> }), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> }), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_10 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1532 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1531 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_9 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1526 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1525 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_10 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1535 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1534 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_9 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1529 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1528 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1520 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1519 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1514 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1513 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1523 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1522 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1508 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1507 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1511 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1510 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1517 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1516 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1502 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1501 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1505 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1504 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1496 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1495 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1499 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1498 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1490 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1489 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1475 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1476 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1493 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1492 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1478 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1477 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1479 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_10 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_9 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_7 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1479 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1476 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1547 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1547 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1545 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1545 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_2632 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_2633 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1535 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1534 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1532 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1531 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1529 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1528 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1526 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1525 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1523 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1522 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1520 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1519 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1517 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1516 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1514 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1513 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1511 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1510 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1508 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1507 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1505 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1504 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1502 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1501 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1499 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1498 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1496 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1495 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1493 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1492 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1490 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1489 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) - ); - MUXF8 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) - ); - MUXF7 \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1478 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1477 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1475 ) - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - ); - RAMB18E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 18'h00000 ), - .INIT_B ( 18'h00000 ), - .INIT_FILE ( "NONE" ), - .RAM_MODE ( "SDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 36 ), - .READ_WIDTH_B ( 0 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 18'h00000 ), - .SRVAL_B ( 18'h00000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 0 ), - .WRITE_WIDTH_B ( 36 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram ( - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .ENARDEN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .REGCEAREGCE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTRAMARSTRAM(NlwRenamedSig_OI_m_axi_aruser[0]), - .RSTRAMB(NlwRenamedSig_OI_m_axi_aruser[0]), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8] -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[10] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[9] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i[8] -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<0>_UNCONNECTED -}), - .WEA({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en }) - ); - GND - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "SDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 72 ), - .READ_WIDTH_B ( 0 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 0 ), - .WRITE_WIDTH_B ( 72 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en ), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEAREGCE -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTRAMARSTRAM(NlwRenamedSig_OI_m_axi_aruser[0]), - .RSTRAMB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .ADDRBWRADDR({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_865_o_add_0_OUT_cy<0>_inv , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [32], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [31], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [65]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [64], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [63], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [62], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [61], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [60], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [59], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [58], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [57], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [56], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [55], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [54], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [53], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [52], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [51], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [50], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [49], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [48], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [47], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [46], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [45], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [44], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [43], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [42], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [41], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [40], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [39], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [38], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [37], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [36], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [35], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [34], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [33]}), - .DIPADIP({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [8]}), - .DIPBDIP({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .DOADO({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [32] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [31] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [30] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [29] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [28] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [27] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [26] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [25] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [24] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [23] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [22] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [21] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [20] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [19] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [18] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [17] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [16] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [15] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [14] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [13] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [12] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [11] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [10] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [7] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [6] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [5] -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [4] -, 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-\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/ram_wr_en }) - ); - GND - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - - ); - VCC - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.veo b/fpga/usrp3/top/x300/coregen/axi_vfifo_64.veo deleted file mode 100644 index 0c0f2d52a..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.veo +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2012 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 * -* * -* The AXI Virtual FIFO Controller is a parameterizable number of multi * -* channel FIFO. * -*******************************************************************************/ - -// Interfaces: -// AXI4Stream_MASTER_M_AXIS -// AXI4Stream_SLAVE_S_AXIS -// AXI4_MASTER_M_AXI - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_vfifo_64 your_instance_name ( - .aclk(aclk), // input aclk - .aresetn(aresetn), // input aresetn - .m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid - .m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr - .m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen - .m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize - .m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst - .m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock - .m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache - .m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot - .m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos - .m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion - .m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser - .m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid - .m_axi_awready(m_axi_awready), // input m_axi_awready - .m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb - .m_axi_wlast(m_axi_wlast), // output m_axi_wlast - .m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser - .m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid - .m_axi_wready(m_axi_wready), // input m_axi_wready - .m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid - .m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp - .m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser - .m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid - .m_axi_bready(m_axi_bready), // output m_axi_bready - .m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid - .m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr - .m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen - .m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize - .m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst - .m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock - .m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache - .m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot - .m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos - .m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion - .m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser - .m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid - .m_axi_arready(m_axi_arready), // input m_axi_arready - .m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid - .m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp - .m_axi_rlast(m_axi_rlast), // input m_axi_rlast - .m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser - .m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid - .m_axi_rready(m_axi_rready), // output m_axi_rready - .s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid - .s_axis_tready(s_axis_tready), // output s_axis_tready - .s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata - .s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb - .s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep - .s_axis_tlast(s_axis_tlast), // input s_axis_tlast - .s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid - .s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest - .m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid - .m_axis_tready(m_axis_tready), // input m_axis_tready - .m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata - .m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb - .m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep - .m_axis_tlast(m_axis_tlast), // output m_axis_tlast - .m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid - .m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest - .vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full - .vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full - .vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty - .vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr - .vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr - .vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr - .vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_vfifo_64.v when simulating -// the core, axi_vfifo_64. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.xco b/fpga/usrp3/top/x300/coregen/axi_vfifo_64.xco deleted file mode 100644 index ce92275d7..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.xco +++ /dev/null @@ -1,75 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.3 -# Date: Thu Nov 22 06:37:07 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:axi_vfifo_ctrl:1.1 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT AXI_Virtual_FIFO_Controller xilinx.com:ip:axi_vfifo_ctrl:1.1 -# END Select -# BEGIN Parameters -CSET ar_weight_ch0=8 -CSET ar_weight_ch1=8 -CSET ar_weight_ch2=8 -CSET ar_weight_ch3=8 -CSET ar_weight_ch4=8 -CSET ar_weight_ch5=8 -CSET ar_weight_ch6=8 -CSET ar_weight_ch7=8 -CSET axi_burst_size=512 -CSET axis_tdata_width=64 -CSET axis_tuser_width=1 -CSET component_name=axi_vfifo_64 -CSET deassert_tready=false -CSET dram_base_addr=80000000 -CSET enable_axis_tid=true -CSET enable_axis_tuser=false -CSET enable_interrupt=true -CSET implementation_type=Burst_Mode -CSET number_of_channel=2 -CSET number_of_page_ch0=4096 -CSET number_of_page_ch1=4096 -CSET number_of_page_ch2=8 -CSET number_of_page_ch3=8 -CSET number_of_page_ch4=8 -CSET number_of_page_ch5=8 -CSET number_of_page_ch6=8 -CSET number_of_page_ch7=8 -CSET s2mm_txn_timeout_value=8 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-06-21T19:48:53Z -# END Extra information -GENERATE -# CRC: 70c312ac diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.xise b/fpga/usrp3/top/x300/coregen/axi_vfifo_64.xise deleted file mode 100644 index 04ce7d1ae..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64.xise +++ /dev/null @@ -1,368 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt deleted file mode 100644 index 2fbc94c40..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt +++ /dev/null @@ -1,189 +0,0 @@ -CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 - - Core name: Xilinx LogiCORE AXI Virtual FIFO Controller - Version: 1.1 - Release: ISE 14.2 / Vivado 2012.2 - Release Date: July 25, 2012 - --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURES HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm - -................................................................................ - - -2. DEVICE SUPPORT - - - 2.1 ISE - - The following device families are supported by the core for this release. - - - All 7 Series devices - Zynq-7000 devices - All Virtex-6 devices - All Spartan-6 devices - - - 2.2 Vivado - - All 7 Series devices - Zynq-7000 devices - -................................................................................ - - -3. NEW FEATURES HISTORY - - - 3.1 ISE - - - First release - - ISE 14.2 software support - - - 3.2 Vivado - - - First release - - 2012.2 software support - -................................................................................ - - -4. RESOLVED ISSUES - - - 4.1 ISE - - - N/A - - - 4.2 Vivado - - - N/A - - -................................................................................ - - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - N/A - - - 5.2 Vivado - - - N/A - - -The most recent information, including known issues, workarounds, and -resolutions for this version is provided in the IP Release Notes User Guide -located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -................................................................................ - - -6. TECHNICAL SUPPORT & FEEDBACK - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -................................................................................ - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support. -04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support. -================================================================================ - -................................................................................ - - -8. LEGAL DISCLAIMER - -(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html deleted file mode 100644 index 7ad3604b5..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html +++ /dev/null @@ -1,200 +0,0 @@ - - -axi_vfifo_ctrl_v1_1_vinfo - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf deleted file mode 100644 index 99f1cfca9..000000000 Binary files a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf and /dev/null differ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf deleted file mode 100755 index 4b89dc81c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf +++ /dev/null @@ -1,56 +0,0 @@ -################################################################################ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - - NET "ACLK" TNM_NET = "ACLK"; - TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ; - -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd deleted file mode 100755 index b74d4897e..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd +++ /dev/null @@ -1,370 +0,0 @@ --------------------------------------------------------------------------------- --- --- AXI Virtual FIFO Controller Core - core top file for implementation --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: axi_vfifo_64_exdes.vhd --- --- Description: --- This is the VFIFO core wrapper with BUFG instances for clock connections. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library unisim; -use unisim.vcomponents.all; - --------------------------------------------------------------------------------- --- Entity Declaration --------------------------------------------------------------------------------- -entity axi_vfifo_64_exdes is - PORT ( - - -- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC) - S_AXIS_TVALID : IN STD_LOGIC := '0'; - S_AXIS_TREADY : OUT STD_LOGIC := '0'; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TLAST : IN STD_LOGIC := '0'; - S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - - -- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch - M_AXIS_TVALID : OUT STD_LOGIC := '0'; - M_AXIS_TREADY : IN STD_LOGIC := '0'; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1'); - M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TLAST : OUT STD_LOGIC := '0'; - M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Write Address Channel Signals - M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWVALID : OUT STD_LOGIC := '0'; - M_AXI_AWREADY : IN STD_LOGIC := '0'; - - -- Write Data Channel Signals - M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WLAST : OUT STD_LOGIC := '0'; - M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WVALID : OUT STD_LOGIC := '0'; - M_AXI_WREADY : IN STD_LOGIC := '0'; - - -- Write Response Channel Signals - M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BVALID : IN STD_LOGIC := '0'; - M_AXI_BREADY : OUT STD_LOGIC := '1'; - - -- Read Address Channel Signals - M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARVALID : OUT STD_LOGIC := '0'; - M_AXI_ARREADY : IN STD_LOGIC := '0'; - - -- Read Data Channel Signals - M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RLAST : IN STD_LOGIC := '0'; - M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RVALID : IN STD_LOGIC := '0'; - M_AXI_RREADY : OUT STD_LOGIC := '0'; - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Status Signal - VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0'; - - -- Global Signals - ACLK : IN STD_LOGIC := '0'; - ARESETN : IN STD_LOGIC := '0' - ); - -end axi_vfifo_64_exdes; - - - -architecture xilinx of axi_vfifo_64_exdes is - - signal s_aclk_i : std_logic; - - component axi_vfifo_64 is - PORT ( - - -- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC) - S_AXIS_TVALID : IN STD_LOGIC := '0'; - S_AXIS_TREADY : OUT STD_LOGIC := '0'; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TLAST : IN STD_LOGIC := '0'; - S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - - -- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch - M_AXIS_TVALID : OUT STD_LOGIC := '0'; - M_AXIS_TREADY : IN STD_LOGIC := '0'; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1'); - M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TLAST : OUT STD_LOGIC := '0'; - M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Write Address Channel Signals - M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWVALID : OUT STD_LOGIC := '0'; - M_AXI_AWREADY : IN STD_LOGIC := '0'; - - -- Write Data Channel Signals - M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WLAST : OUT STD_LOGIC := '0'; - M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WVALID : OUT STD_LOGIC := '0'; - M_AXI_WREADY : IN STD_LOGIC := '0'; - - -- Write Response Channel Signals - M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BVALID : IN STD_LOGIC := '0'; - M_AXI_BREADY : OUT STD_LOGIC := '1'; - - -- Read Address Channel Signals - M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARVALID : OUT STD_LOGIC := '0'; - M_AXI_ARREADY : IN STD_LOGIC := '0'; - - -- Read Data Channel Signals - M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RLAST : IN STD_LOGIC := '0'; - M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RVALID : IN STD_LOGIC := '0'; - M_AXI_RREADY : OUT STD_LOGIC := '0'; - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Status Signal - VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0'; - - -- Global Signals - ACLK : IN STD_LOGIC := '0'; - ARESETN : IN STD_LOGIC := '0' - ); - - end component; - - -begin - - s_aclk_buf: bufg - PORT map( - i => ACLK, - o => s_aclk_i - ); - - exdes_inst : axi_vfifo_64 - PORT MAP ( - - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TREADY => S_AXIS_TREADY, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TSTRB => S_AXIS_TSTRB, - S_AXIS_TKEEP => S_AXIS_TKEEP, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TID => S_AXIS_TID, - S_AXIS_TDEST => S_AXIS_TDEST, - - M_AXIS_TVALID => M_AXIS_TVALID, - M_AXIS_TREADY => M_AXIS_TREADY, - M_AXIS_TDATA => M_AXIS_TDATA, - M_AXIS_TSTRB => M_AXIS_TSTRB, - M_AXIS_TKEEP => M_AXIS_TKEEP, - M_AXIS_TLAST => M_AXIS_TLAST, - M_AXIS_TID => M_AXIS_TID, - M_AXIS_TDEST => M_AXIS_TDEST, - - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => M_AXI_AWLOCK, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWUSER => M_AXI_AWUSER, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WUSER => M_AXI_WUSER, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BUSER => M_AXI_BUSER, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => M_AXI_ARLOCK, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARUSER => M_AXI_ARUSER, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RUSER => M_AXI_RUSER, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL, - VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY, - VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL, - - -- Status Signal - VFIFO_IDLE => VFIFO_IDLE, - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR, - VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR, - VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR, - - ACLK => s_aclk_i, - ARESETN => ARESETN - ); - -end xilinx; diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc deleted file mode 100755 index 94c78f7c9..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc +++ /dev/null @@ -1,55 +0,0 @@ -################################################################################ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - -create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ] - -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement.bat deleted file mode 100755 index a848a84f4..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement.bat +++ /dev/null @@ -1,88 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -copy axi_vfifo_64_exdes.ngc .\results\ - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\axi_vfifo_64.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\axi_vfifo_64_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes - -echo 'Running map' -map axi_vfifo_64_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement.sh deleted file mode 100755 index cf55fbb54..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -cp axi_vfifo_64_exdes.ngc ./results/ - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../axi_vfifo_64.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/axi_vfifo_64_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes - -echo 'Running map' -map axi_vfifo_64_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement_synplify.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement_synplify.bat deleted file mode 100755 index a88446b4c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement_synplify.bat +++ /dev/null @@ -1,87 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\axi_vfifo_64.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\axi_vfifo_64_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes - -echo 'Running map' -map axi_vfifo_64_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement_synplify.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement_synplify.sh deleted file mode 100755 index 42b3d31d1..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/implement_synplify.sh +++ /dev/null @@ -1,86 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../axi_vfifo_64.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/axi_vfifo_64_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes - -echo 'Running map' -map axi_vfifo_64_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.bat deleted file mode 100755 index 7d4334aad..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.bat +++ /dev/null @@ -1,54 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem ----------------------------------------------------------------------------- -rem Script to synthesize and implement the Coregen FIFO Generator -rem ----------------------------------------------------------------------------- -rmdir /S /Q results -mkdir results -cd results -copy ..\..\..\axi_vfifo_64.ngc . -planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.sh deleted file mode 100755 index 7682d53ba..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.sh +++ /dev/null @@ -1,55 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the Coregen FIFO Generator -#----------------------------------------------------------------------------- -rm -rf results -mkdir results -cd results -cp ../../../axi_vfifo_64.ngc . -planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.tcl b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.tcl deleted file mode 100755 index 0d9dc2fde..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.tcl +++ /dev/null @@ -1,67 +0,0 @@ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - - -set device xc7k410tffg900-2 -set projName axi_vfifo_64 -set design axi_vfifo_64 -set projDir [file dirname [info script]] -create_project $projName $projDir/results/$projName -part $device -force -set_property design_mode RTL [current_fileset -srcset] -set top_module axi_vfifo_64_exdes -add_files -norecurse {../../example_design/axi_vfifo_64_exdes.vhd} -add_files -norecurse {./axi_vfifo_64.ngc} -import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_exdes.xdc} -set_property top axi_vfifo_64_exdes [get_property srcset [current_run]] -synth_design -opt_design -place_design -route_design -write_sdf -rename_top_module axi_vfifo_64_exdes -file routed.sdf -write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_exdes routed.v -report_timing -nworst 30 -path_type full -file routed.twr -report_drc -file report.drc -write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/xst.prj b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/xst.prj deleted file mode 100755 index 37dc13c09..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/xst.prj +++ /dev/null @@ -1 +0,0 @@ -work ../example_design/axi_vfifo_64_exdes.vhd diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/xst.scr b/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/xst.scr deleted file mode 100755 index b589bbab9..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64/implement/xst.scr +++ /dev/null @@ -1,13 +0,0 @@ -run --ifmt VHDL --ent axi_vfifo_64_exdes --p xc7k410t-ffg900-2 --ifn xst.prj --write_timing_constraints No --iobuf YES --max_fanout 100 --ofn axi_vfifo_64_exdes --ofmt NGC --bus_delimiter () --hierarchy_separator / --case Maintain diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.gise b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.gise deleted file mode 100644 index a7fb8954d..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.ncf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.ngc b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.ngc deleted file mode 100644 index 7a9fe500c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$3fb4~753-Xnzd}foo8#5+421).97 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d152=<97co81;33?>o3=90;6)o82;656>hf?80:=65f45g94?"f?;0?:?5aa63957=o6=4+a6090345:9j01g=83.j;?4;639me27=9?10e9:6:18'e24=:058?l2303:1(l9=:541?kg093;376g;4683>!g0:3>=>6`n7082=>=n<=<1<7*n738727=ii>;1=l54i566>5<#i>818;<4n`52>4d<3`>??7>5$`51>1053gk<=7?l;:k707<72-k<>7:92:lb34<6l21b89?50;&b37<3>;1em:?51d98m127290/m:<54708jd1628l07d:o3;l0;6)o82;656>hf?809=65f42f94?"f?;0?:?5aa63967=:358?l21?3:1(l9=:541?kg0938376g;6783>!g0:3>=>6`n7081=>=n;1>l54i547>5<#i>818;<4n`52>7d<3`>>m7>5$`51>1053gk<=77:92:lb34<5l21b89:50;&b37<3>;1em:?52d98m15>290/m:<54708jd162;l07b:87;29 d152===7co81;28?l26:3:1(l9=:532?kg093:07d:>0;29 d152=;:7co81;38?l27n3:1(l9=:532?kg093807d:?e;29 d152=;:7co81;18?l27l3:1(l9=:532?kg093>07d:?c;29 d152=;:7co81;78?l27j3:1(l9=:532?kg093<07d:?a;29 d152=;:7co81;58?l26j3:1(l9=:532?kg093207d:>a;29 d152=;:7co81;;8?l2613:1(l9=:532?kg093k07d:>8;29 d152=;:7co81;`8?l26?3:1(l9=:532?kg093i07d:>6;29 d152=;:7co81;f8?l26=3:1(l9=:532?kg093o07d:>4;29 d152=;:7co81;d8?l26;3:1(l9=:532?kg093;;76g;0883>!g0:3>:=6`n70825>=n;ok1<7*n7380b<=ii>;1<65f3g:94?"f?;08j45aa6395>=n;o=1<7*n7380b<=ii>;1>65f3g794?"f?;08j45aa6397>=n;o>1<7*n7380b<=ii>;1865f3g194?"f?;08j45aa6391>=n;o;1<7*n7380b<=ii>;1:65f3g294?"f?;08j45aa6393>=n<991<7*n7380b<=ii>;1465f41094?"f?;08j45aa639=>=n<9;1<7*n7380b<=ii>;1m65f41294?"f?;08j45aa639f>=n;ol1<7*n7380b<=ii>;1o65f3gg94?"f?;08j45aa639`>=n;on1<7*n7380b<=ii>;1i65f3ga94?"f?;08j45aa639b>=n;oh1<7*n7380b<=ii>;1==54i2ge>5<#i>81?k74n`52>47<3f>997>5$`51>1433gk<=7>4;n617?6=,h=969<;;oc45?7<3f>9>7>5$`51>1433gk<=7<4;n615?6=,h=969<;;oc45?5<3f>9<7>5$`51>1433gk<=7:4;n62b?6=,h=969<;;oc45?3<3f>:i7>5$`51>1433gk<=784;n62`?6=,h=969<;;oc45?1<3f>9i7>5$`51>1433gk<=764;n61`?6=,h=969<;;oc45??<3f>9o7>5$`51>1433gk<=7o4;n61f?6=,h=969<;;oc45?d<3f>9m7>5$`51>1433gk<=7m4;n61=?6=,h=969<;;oc45?b<3f>947>5$`51>1433gk<=7k4;n613?6=,h=969<;;oc45?`<3f>9:7>5$`51>1433gk<=7??;:m75f<72-k<>7:=4:lb34<6921dm=:50;&b37i>ml0;6)o82;c37>hf?80:?65`9df94?"f?;0j<>5aa63951=<;oc45?7132e2il4?:%c46?g7;2dj;<4>7:9l=`?=83.j;?4n029me27=9110c4k7:18'e24=i990bl9>:0;8?j?b?3:1(l9=:`20?kg093;j76a6e783>!g0:3k;?6`n7082f>=h1l>1<7*n738b46=ii>;1=n54o8g0>5<#i>81m==4n`52>4b<3f3n>7>5$`51>d643gk<=7?j;:m:a4<72-k<>7o?3:lb34<6n21d5h>50;&b37i>lm0;6)o82;c37>hf?809?65`9ea94?"f?;0j<>5aa63961=<;oc45?4132ej<44?:%c46?g7;2dj;<4=7:9le5>=83.j;?4n029me27=:110cl>8:18'e24=i990bl9>:3;8?jg7>3:1(l9=:`20?kg0938j76an0483>!g0:3k;?6`n7081f>=h1oh1<7*n738b46=ii>;1>n54o8d3>5<#i>81m==4n`52>7b<3f3n97>5$`51>d643gk<=77o?3:lb34<5n21b=nj50;&b37<6kj1em:?50:9j5fd=83.j;?4>cb9me27=921b=no50;&b37<6kj1em:?52:9j5f?=83.j;?4>cb9me27=;21b=n650;&b37<6kj1em:?54:9j5f1=83.j;?4>cb9me27==21b=n850;&b37<6kj1em:?56:9j5f3=83.j;?4>cb9me27=?21b=n:50;&b37<6kj1em:?58:9j5f5=83.j;?4>cb9me27=121b=n?50;&b37<6kj1em:?5a:9j5f6=83.j;?4>cb9me27=j21b=oh50;&b37<6kj1em:?5c:9j5gc=83.j;?4>cb9me27=l21b=oj50;&b37<6kj1em:?5e:9j5gd=83.j;?4>cb9me27=n21b=oo50;&b37<6kj1em:?51198m4d>290/m:<51ba8jd1628;07d?m7;29 d1528ih7co81;31?>o6j?0;6)o82;3`g>hf?80:?65f1e794?"f?;0:on5aa63951=7:9j5a7=83.j;?4>cb9me27=9110e:0;8?l7dn3:1(l9=:0a`?kg093;j76g>cd83>!g0:3;ho6`n7082f>=n9j81<7*n7382gf=ii>;1=n54i0`6>5<#i>81=nm4n`52>4b<3fk=m7>5$`51>d0>3gk<=7>4;nc55$`51>d0>3gk<=7<4;nc52?6=,h=96l86;oc45?5<3fk=97>5$`51>d0>3gk<=7:4;nc50?6=,h=96l86;oc45?3<3fk=?7>5$`51>d0>3gk<=784;nc56?6=,h=96l86;oc45?1<3fk=<7>5$`51>d0>3gk<=764;nc6b?6=,h=96l86;oc45??<3fk>i7>5$`51>d0>3gk<=7o4;nc6`?6=,h=96l86;oc45?d<3fk>o7>5$`51>d0>3gk<=7m4;nc6f?6=,h=96l86;oc45?b<3fk>m7>5$`51>d0>3gk<=7k4;nc6=?6=,h=96l86;oc45?`<3fk>47>5$`51>d0>3gk<=7??;:mb12<72-k<>7o99:lb34<6921dm8;50;&b3701em:?51398kd33290/m:<5a7;8jd1628907bo:3;29 d152h<27co81;37?>if=;0;6)o82;c5=>hf?80:965`a4394?"f?;0j:45aa63953=9:9le1b=83.j;?4n689me27=9h10cl:l:18'e24=i?30bl9>:0`8?jg3i3:1(l9=:`4:?kg093;h76an4883>!g0:3k=56`n7082`>=hi=21<7*n738b2<=ii>;1=h54o`64>5<#i>81m;74n`52>4`<3fk?:7>5$`51>d0>3gk<=77o99:lb34<5921dm9:50;&b3701em:?52398kd24290/m:<5a7;8jd162;907bo;2;29 d152h<27co81;07?>if<80;6)o82;c5=>hf?809965`a6294?"f?;0j:45aa63963=:3`8?jg193:1(l9=:`4:?kg0938h76an5783>!g0:3k=56`n7081`>=hi=h1<7*n738b2<=ii>;1>h54o`63>5<#i>81m;74n`52>7`<3`8;?7>5$`51>7653gk<=7>4;h035?6=,h=96?>=;oc45?7<3`8;<7>5$`51>7653gk<=7<4;h3eb?6=,h=96?>=;oc45?5<3`;mi7>5$`51>7653gk<=7:4;h3e`?6=,h=96?>=;oc45?3<3`;mo7>5$`51>7653gk<=784;h3ef?6=,h=96?>=;oc45?1<3`;mm7>5$`51>7653gk<=764;h3e=?6=,h=96?>=;oc45??<3`;m;7>5$`51>7653gk<=7o4;h3e2?6=,h=96?>=;oc45?d<3`;m97>5$`51>7653gk<=7m4;h3e0?6=,h=96?>=;oc45?b<3`;m?7>5$`51>7653gk<=7k4;h3e6?6=,h=96?>=;oc45?`<3`;m=7>5$`51>7653gk<=7??;:k2b5<72-k<>7o58h0;6)o82;036>hf?80:965f21;94?"f?;09=;oc45?7?32c9<;4?:%c46?47:2dj;<4>9:9j653=83.j;?4=039me27=9h10e?>;:18'e24=:980bl9>:0`8?l7a03:1(l9=:321?kg093;h76g>ee83>!g0:38;>6`n7082`>=hi9n1<75fag294?=n<1:1<75f49094?=nio81<75f80f94?=n<1;1<75fag394?=nil21<75f49194?=h:>8i6=44o`2f>5<5<5<5<5<5<6=4+a6090205<#i>818:84n`52>7=54i552>5<#i>818:>4n`52>5=15d3ty:n:4?:3y]5g1<5;n2;7:vP>d59>6a?02=<37p}>d283>7}Y9m901?j67;653>{t9m81<70?:;5rs0f2>5<5sW;o=63=d85903352z\2`5=::m3<698;;|q2gc<72;qU=nh4=3f:3?22i2wx=nk50;0xZ4eb348o5:4;4g9~w4e52909wS?l2:?1`<1=<=>0q~?m5;296~X6j<16>i78:51:?xu4n:0;6?uQ3g1897b>?39m?6s|3g394?4|V:l:70;5l0=1?k>4}r637?6=:rT?<>522e;4>1643ty?>;<0g=2<3881v9>?:181[278279h4954128yv5an3:1>vP6a?02:lm7p}7}Y;oo01?j67;1ea>{t;on1<708ji5rs2d`>5<5sW9mo63=d8597ce52z\0bg=::m3<6>hm;|q0ac<72;qU?hh4=3f:3?5bn2wx85m50;0xZ1>d348o5:4;8b9~wg7?2909wSl>8:?1`<1=io90q~l?7;296~Xe8>16>i78:8fg?xue8<0;6?uQb17897b>?33oo6s|b1694?4|Vk:?70;5l0=1m=o4}r`27?6=:rTi=>522e;4>d6>3tyi=?4?:3y]f44<5;n2;7o?8:pf47=838pRo?>;<0g=21vo??:181[d68279h495a148yvd7n3:1>vPm0g9>6a?02h:>7p}m0d83>7}Yj9o01?j67;;ef>{tj9n1<702j=5rsc2`>5<5sWh;o63=d859=`352z\a46=::m3<64jn;|q1`<0=832p1?98f;;g<>;5l0=18594=3f:3??c:279h4959e3897b>?33hi63=d859=fb<5;n2;7=n6:8n;_6bg>;5l0=18;k4=3f:3?21k279h49547c897b>?33o863=d859=a6<5;n2;77lf:?1`<1=i:301?j67;c03>;5l0=1m>84=3f:3?g4=279h495a26897b>?3k8?63=d859e64<5;n2;7o<1:?1`<1=i;l01?j67;c1a>;5l0=1m?j4=3f:3?g5k279h495a3`897b>?3k9m63=d859e7?<5;n2;7o=8:?1`<1=i;=01?j67;c12>;5l0=1m?:4=3f:3?g5;279h495a30897b>?3k9=63=d859e76<5;n2;7o>f:?1`<1=i8o01?j67;c2`>;5l0=1m?3k:463=d859e41<5;n2;7o>6:?1`<1=i8?01?j67;c20>;5l0=1m<=4=3f:3?g6:279h495a03897b>?3k:<63=d859e6`<5;n2;7o;5l0=1m>l4=3f:3?g4i279h495a22897b>?3k9963=d859e4g<5;n2;7o?f:?1`<1=:m901?j67;0g5>;5l0=18;=4=3f:3?219279h495472897b>?3>>j63=d85900c<5;n2;7::d:?1`<1=<;5l0=18874=3f:3?220279h495445897b>?3>>:63=d859003<5;n2;7::4:?1`<1=<<901?j67;666>;5l0=188?4=3f:3?228279h49545g897b>?3>?h63=d85901e<5;n2;7:;b:?1`<1=<=k01?j67;67=>;5l0=18964=3f:3?23?279h495454897b>?3>?963=d859015<5;n2;7:;2:?1`<1=<=;01?j67;674>;5l0=18>h4=3f:3?24m279h49542f897b>?3>:>63=d859046<5;n2;7:?f:?1`<1=<9o01?j67;63`>;5l0=18=m4=3f:3?27j279h49541c897b>?3>:n63=d85904g<5;n2;7:>9:?1`<1=<8201?j67;623>;5l0=18<84=3f:3?26=279h495406897b>?3>:?63=d85905?<5;n2;7=ia:?1`<1=;o201?j67;1e3>;5l0=1?k;4=3f:3?5a<279h4951bf897b>?3;hn63=d8595fg<5;n2;7?l9:?1`<1=9j201?j67;3`3>;5l0=1=n84=3f:3?7d=279h4951b6897b>?3;h?63=d8595f7<5;n2;7?l0:?1`<1=9kl01?j67;3aa>;5l0=1=oj4=3f:3?7ej279h4951cc897b>?3;i563=d8595g1<5;n2;7?m6:?1`<1=9m?01?j67;3g0>;5l0=1=i=4=3f:3?7c:279h4951e3897b>?3;o<63=d8595f`<5;n2;7?le:?1`<1=9j801?j67;3a1>;5l0=1>==4=3f:3?479279h495212897b>?3;mj63=d8595cc<5;n2;7?id:?1`<1=9oi01?j67;3ef>;5l0=1=ko4=3f:3?7a1279h4951g5897b>?3;m:63=d8595c3<5;n2;7?i4:?1`<1=9o901?j67;3e6>;5l0=1=k?4=3f:3?7a8279h4951dd897b>?3;ni63=d85965d<5;n2;7;5l0=1>=94=3f:3?47>279h495217897b>?38;863=d8595c><5;n2;7?jd:?1`<1=io:01?j67;6;4>;5l0=185<4=3f:3?ga:279h49580f897b>?3>3=63=d859ec7<5;n2;7oj8:?1`<1=<1901?j67;cfg>;5l0=1mhl4=3f:3?20n279h49546g897b>?3>01?j67;6;1>;5l0=18:?4=3f:3?21n2wvn<9=c;2975<42;hpD?9=d:&`ga<50jl0V9=>:2y72?202<:1q)b99me27=821b=o950;&b37<6j11em:?51:9j5g0=83.j;?4>b99me27=:21b=i;50;&b37<6j11em:?53:9j5a2=83.j;?4>b99me27=<21b=i=50;&b37<6j11em:?55:9j5a4=83.j;?4>b99me27=>21b=i?50;&b37<6j11em:?57:9j5a6=83.j;?4>b99me27=021b=nh50;&b37<6j11em:?59:9j5fc=83.j;?4>b99me27=i21b=n<50;&b37<6j11em:?5b:9j5g3=83.j;?4>b99me27=k21b?k=50;&b37<4n;1em:?50:9j7c7=83.j;?450;&b37<4n;1em:?52:9j055=83.j;?450;&b37<4n;1em:?56:9j7c`=83.j;?4?l50;9j0dd=831b8:m50;9j064=831bn<650;9jf7g=831bn?<50;9lf51=83.j;?4m079me27=821dn=;50;&b3721dn<>50;&b37:9m;I046a=h1m21<75rb354a?6=93:1=i7E<82e9l33g=831vn?j67;2952`=83:pD?9=d:&`ga<08l1Q8>?5ezf6>4762o:1=865c`84=?ca2ln1;54l9;g`>21=ml0h47s+9e496gd73g;no7>4n3f7>5=i:m?1<6*=d6847==#:m214<74$2gg>0ba3g>;47>4n513>5=#<:919ih4n54g>5=i<>81<6`;a`83?!>603o;7c6>a;28j=7d291e5i;50:&b4f=7?3-h:n7o?c:&a5f7:80:lb34<532e3=h4?::k7<2<722e?:o4?::k74?::m167<72-k<>7<=1:lb34<732e9>=4?:%c46?4592dj;<4>;:m15c<72-k<>7<=1:lb34<532e9=h4?:%c46?4592dj;<4<;:m15a<72-k<>7<=1:lb34<332e9=n4?:%c46?4592dj;<4:;:m15g<72-k<>7<=1:lb34<132e9=l4?:%c46?4592dj;<48;:m15<<72-k<>7<=1:lb347<=1:lb347<=1:lb344?:%c46?4592dj;<4k;:m157<72-k<>7<=1:lb347<=1:lb34<6821d>=h50;&b37<5:81em:?51098k76b290/m:<52338jd1628807bi5:h0;6)o82;015>hf?80:865`23;94?"f?;09><5aa63950=;oc45?7032e9>;4?:%c46?4592dj;<4>8:9l673=83.j;?4=209me27=9010c?<;:18'e24=:;;0bl9>:0c8?j45;3:1(l9=:302?kg093;i76a=1683>!g0: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d152h937co81;3b?>of9k0;6)o82;c0<>hf?80:n65fa0;94?"f?;0j?55aa6395f=f:9je43=83.j;?4n399me27=:910el?;:18'e24=i:20bl9>:338?lg6;3:1(l9=:`1;?kg0938976gn1383>!g0:3k846`n70817>=ni8;1<7*n738b7==ii>;1>954i`33>5<#i>81m>64n`52>73<3`k8j7>5$`51>d5?3gk<=7<9;:kb7`<72-k<>7o<8:lb34<5?21bm>j50;&b37of;h0;6)o82;c0<>hf?809n65fa2294?"f?;0j?55aa6396f=6=4+a609e6>i?50;&b37<5l;1em:?51:9j6a6=83.j;?4=d39me27=:21b>nh50;&b37<5l;1em:?53:9j035=83.j;?4;639me27=821b8;?50;&b37<3>;1em:?51:9j036=83.j;?4;639me27=:21b88h50;&b37<3>;1em:?53:9j00c=83.j;?4;639me27=<21b88j50;&b37<3>;1em:?55:9j00e=83.j;?4;639me27=>21b88l50;&b37<3>;1em:?57:9j00?=83.j;?4;639me27=021b88650;&b37<3>;1em:?59:9j001=83.j;?4;639me27=i21b88850;&b37<3>;1em:?5b:9j003=83.j;?4;639me27=k21b88:50;&b37<3>;1em:?5d:9j005=83.j;?4;639me27=m21b88<50;&b37<3>;1em:?5f:9j007=83.j;?4;639me27=9910e9;?:18'e24=:038?l23m3:1(l9=:541?kg093;976g;4e83>!g0:3>=>6`n70827>=n<=i1<7*n738727=ii>;1=954i56a>5<#i>818;<4n`52>43<3`>?m7>5$`51>1053gk<=7?9;:k70<<72-k<>7:92:lb34<6?21b89650;&b37<3>;1em:?51998m120290/m:<54708jd1628307d:;6;29 d152=<97co81;3b?>o3<<0;6)o82;656>hf?80:n65f45194?"f?;0?:?5aa6395f=96=4+a609034f:9j06`=83.j;?4;639me27=:910e9=j:18'e24=:338?l24l3:1(l9=:541?kg0938976g;3b83>!g0:3>=>6`n70817>=n<:h1<7*n738727=ii>;1>954i51b>5<#i>818;<4n`52>73<3`>=57>5$`51>1053gk<=7<9;:k72=<72-k<>7:92:lb34<5?21b8;950;&b37<3>;1em:?52998m101290/m:<54708jd162;307d:95;29 d152=<97co81;0b?>o3>=0;6)o82;656>hf?809n65f44c94?"f?;0?:?5aa6396f=m6=4+a609034=83.j;?4;109me27=j21b8<950;&b37<3981em:?5c:9j040=83.j;?4;109me27=l21b8<;50;&b37<3981em:?5e:9j042=83.j;?4;109me27=n21b8<=50;&b37<3981em:?51198m16>290/m:<54038jd1628;07d=ia;29 d152:l27co81;28?l5a03:1(l9=:2d:?kg093;07d=i7;29 d152:l27co81;08?l5a=3:1(l9=:2d:?kg093907d=i4;29 d152:l27co81;68?l5a;3:1(l9=:2d:?kg093?07d=i1;29 d152:l27co81;48?l5a83:1(l9=:2d:?kg093=07d:?3;29 d152:l27co81;:8?l27:3:1(l9=:2d:?kg093307d:?1;29 d152:l27co81;c8?l2783:1(l9=:2d:?kg093h07d=if;29 d152:l27co81;a8?l5am3:1(l9=:2d:?kg093n07d=id;29 d152:l27co81;g8?l5ak3:1(l9=:2d:?kg093l07d=ib;29 d152:l27co81;33?>o4mo0;6)o82;1e=>hf?80:=65`43794?"f?;0?>95aa6394>=h<;91<7*n738761=ii>;1=65`43094?"f?;0?>95aa6396>=h<;;1<7*n738761=ii>;1?65`43294?"f?;0?>95aa6390>=h<8l1<7*n738761=ii>;1965`40g94?"f?;0?>95aa6392>=h<8n1<7*n738761=ii>;1;65`43g94?"f?;0?>95aa639<>=h<;n1<7*n738761=ii>;1565`43a94?"f?;0?>95aa639e>=h<;h1<7*n738761=ii>;1n65`43c94?"f?;0?>95aa639g>=h<;31<7*n738761=ii>;1h65`43:94?"f?;0?>95aa639a>=h<;=1<7*n738761=ii>;1j65`43494?"f?;0?>95aa63955=<;oc45?6<3fk;>7>5$`51>d643gk<=7?4;nc35?6=,h=96l><;oc45?4<3fk;<7>5$`51>d643gk<=7=4;n;eb?6=,h=96l><;oc45?2<3f3mi7>5$`51>d643gk<=7;4;n;e`?6=,h=96l><;oc45?0<3f3mo7>5$`51>d643gk<=794;n;ee?6=,h=96l><;oc45?><3f3m57>5$`51>d643gk<=774;n;e<;oc45?g<3f3m;7>5$`51>d643gk<=7l4;n;e2?6=,h=96l><;oc45?e<3f3m97>5$`51>d643gk<=7j4;n;e0?6=,h=96l><;oc45?c<3f3m?7>5$`51>d643gk<=7h4;n;e6?6=,h=96l><;oc45?7732e2j<4?:%c46?g7;2dj;<4>1:9l=``=83.j;?4n029me27=9;10c4kj:18'e24=i990bl9>:018?j?bl3:1(l9=:`20?kg093;?76a6eb83>!g0:3k;?6`n70821>=h1lh1<7*n738b46=ii>;1=;54o8gb>5<#i>81m==4n`52>41<3f3n57>5$`51>d643gk<=7?7;:m:a=<72-k<>7o?3:lb34<6121d5h950;&b37i>m:0;6)o82;c37>hf?80:h65`9d094?"f?;0j<>5aa6395`=<;oc45?4732e2hk4?:%c46?g7;2dj;<4=1:9l=ac=83.j;?4n029me27=:;10c4jk:18'e24=i990bl9>:318?j?ck3:1(l9=:`20?kg0938?76a6dc83>!g0:3k;?6`n70811>=hi9k1<7*n738b46=ii>;1>;54o`2:>5<#i>81m==4n`52>71<3fk;47>5$`51>d643gk<=7<7;:mb42<72-k<>7o?3:lb34<5121dm=850;&b37i>n90;6)o82;c37>hf?809h65`9d794?"f?;0j<>5aa6396`=5$`51>4ed3gk<=7?4;h3`e?6=,h=965$`51>4ed3gk<=7=4;h3`5$`51>4ed3gk<=7;4;h3`2?6=,h=965$`51>4ed3gk<=794;h3`0?6=,h=96<3`;h?7>5$`51>4ed3gk<=774;h3`5?6=,h=965$`51>4ed3gk<=7l4;h3ab?6=,h=965$`51>4ed3gk<=7j4;h3a`?6=,h=965$`51>4ed3gk<=7h4;h3ae?6=,h=961:9j5g1=83.j;?4>cb9me27=9;10e:018?l7c=3:1(l9=:0a`?kg093;?76g>d583>!g0:3;ho6`n70821>=n9m91<7*n7382gf=ii>;1=;54i0f1>5<#i>81=nm4n`52>41<3`;o=7>5$`51>4ed3gk<=7?7;:k2`5<72-k<>7?lc:lb34<6121b=nh50;&b37<6kj1em:?51`98m4eb290/m:<51ba8jd1628h07d?l2;29 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d152:l27co81;;8?l2793:1(l9=:2d:?kg093k07d:?0;29 d152:l27co81;`8?l5an3:1(l9=:2d:?kg093i07d=ie;29 d152:l27co81;f8?l5al3:1(l9=:2d:?kg093o07d=ic;29 d152:l27co81;d8?l5aj3:1(l9=:2d:?kg093;;76g!g0:39m56`n70825>=h<;?1<7*n738761=ii>;1<65`43194?"f?;0?>95aa6395>=h<;81<7*n738761=ii>;1>65`43394?"f?;0?>95aa6397>=h<;:1<7*n738761=ii>;1865`40d94?"f?;0?>95aa6391>=h<8o1<7*n738761=ii>;1:65`40f94?"f?;0?>95aa6393>=h<;o1<7*n738761=ii>;1465`43f94?"f?;0?>95aa639=>=h<;i1<7*n738761=ii>;1m65`43`94?"f?;0?>95aa639f>=h<;k1<7*n738761=ii>;1o65`43;94?"f?;0?>95aa639`>=h<;21<7*n738761=ii>;1i65`43594?"f?;0?>95aa639b>=h<;<1<7*n738761=ii>;1==54o53`>5<#i>818?:4n`52>47<3fk;87>5$`51>d643gk<=7>4;nc36?6=,h=96l><;oc45?7<3fk;=7>5$`51>d643gk<=7<4;nc34?6=,h=96l><;oc45?5<3f3mj7>5$`51>d643gk<=7:4;n;ea?6=,h=96l><;oc45?3<3f3mh7>5$`51>d643gk<=784;n;eg?6=,h=96l><;oc45?1<3f3mm7>5$`51>d643gk<=764;n;e=?6=,h=96l><;oc45??<3f3m47>5$`51>d643gk<=7o4;n;e3?6=,h=96l><;oc45?d<3f3m:7>5$`51>d643gk<=7m4;n;e1?6=,h=96l><;oc45?b<3f3m87>5$`51>d643gk<=7k4;n;e7?6=,h=96l><;oc45?`<3f3m>7>5$`51>d643gk<=7??;:m:b4<72-k<>7o?3:lb34<6921d5hh50;&b37i>mj0;6)o82;c37>hf?80:965`9d`94?"f?;0j<>5aa63953=<;oc45?7?32e2i54?:%c46?g7;2dj;<4>9:9l=`1=83.j;?4n029me27=9h10c4k9:18'e24=i990bl9>:0`8?j?b<3:1(l9=:`20?kg093;h76a6e283>!g0:3k;?6`n7082`>=h1l81<7*n738b46=ii>;1=h54o8g2>5<#i>81m==4n`52>4`<3f3n<7>5$`51>d643gk<=77o?3:lb34<5921d5ik50;&b37i>lk0;6)o82;c37>hf?809965`a1c94?"f?;0j<>5aa63963=<;oc45?4?32ej<:4?:%c46?g7;2dj;<4=9:9le50=83.j;?4n029me27=:h10cl>::18'e24=i990bl9>:3`8?j?aj3:1(l9=:`20?kg0938h76a6f183>!g0:3k;?6`n7081`>=h1l?1<7*n738b46=ii>;1>h54o8fb>5<#i>81m==4n`52>7`<3`;hh7>5$`51>4ed3gk<=7>4;h3`f?6=,h=965$`51>4ed3gk<=7<4;h3`=?6=,h=965$`51>4ed3gk<=7:4;h3`3?6=,h=965$`51>4ed3gk<=784;h3`1?6=,h=965$`51>4ed3gk<=764;h3`7?6=,h=965$`51>4ed3gk<=7o4;h3`4?6=,h=965$`51>4ed3gk<=7m4;h3aa?6=,h=965$`51>4ed3gk<=7k4;h3af?6=,h=965$`51>4ed3gk<=7??;:k2f<<72-k<>7?lc:lb34<6921b=o950;&b37<6kj1em:?51398m4d1290/m:<51ba8jd1628907d?k5;29 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d152;:97co81;30?>o58k0;6)o82;036>hf?80:865f21c94?"f?;09=;oc45?7032c9<:4?:%c46?47:2dj;<4>8:9j650=83.j;?4=039me27=9010e?>::18'e24=:980bl9>:0c8?l47<3:1(l9=:321?kg093;i76g>f983>!g0:38;>6`n7082g>=n9ln1<7*n738147=ii>;1=i54o`2g>5<5<5<5<5<5;hcfg?6=3`knn7>5;h64b?6=3`>5;h64`?6=3`knh7>5;h6;2?6=3f3o;7>5;h6;0?6=3`>397>5;n641?6=,h=96999;oc45?7<3f><87>5$`51>1113gk<=7<4;n647?6=,h=96999;oc45?5<3`><=7>5$`51>1173gk<=7>4;h65b?6=,h=9699?;oc45?7<3ty:n44?:3y]5g?<5;n2;7:279h49542c8yv7c=3:1>vP>d49>6a?02=<27p}>d583>7}Y9m>01?j67;65<>{t9m91<70?::5rs0f1>5<5sW;o>63=d85903052z\2`4=::m3<698:;|q2`5<72;qU=i>4=3f:3?21<2wx=nh50;0xZ4ea348o5:4;5`9~w4eb2909wS?le:?1`<1=<=l0q~?l2;296~X6k;16>i78:567?xu6j<0;6?uQ1c7897b>?3>856s|3g194?4|V:l870;5l0=1?k?4}r1e4?6=:rT8j=522e;4>6`73ty?<>4?:3y]055<5;n2;7:?3:p054=838pR9>=;<0g=2<38;1v9>>:181[279279h4954138yv2783:1>vP;019>6a?02=:;7p}7}Y;ol01?j67;1eb>{t;oo1<708jh5rs2dg>5<5sW9mh63=d8597cb52z\0bf=::m3<6>hl;|q0bg<72;qU?kl4=3f:3?5aj2wx?hh50;0xZ6ca348o5:4d2909wS:7c:?1`<1=<1i0q~l>8;296~Xe9116>i78:`d0?xue8>0;6?uQb15897b>?33oh6s|b1794?4|Vk:>70;5l0=15il4}r`20?6=:rTi=9522e;4>d6f3tyi=>4?:3y]f45<5;n2;7o?9:pf44=838pRo?=;<0g=2:181[d69279h495a158yvd683:1>vPm119>6a?02h:=7p}m0g83>7}Yj9l01?j67;c31>{tj9o1<702jo5rsc2g>5<5sWh;h63=d859=c652z\a4f=::m3<64k:;|qa46<72;qUn==4=3f:3??ci2wx>i79:18;840?o02h5522e;4>1>0348o5:46d39>6a?020n:70i78:3ae?xu3ij0;6n:t=354a?11i2T?mn522e;4>10b348o5:4;6b9>6a?02=ko16>i78:`1:?84c1>0j?:522e;4>d51348o5:4n349>6a?02h9?70i78:`0e?84c1>0j>h522e;4>d4c348o5:4n2b9>6a?02h8i70i78:`04?84c1>0j>;522e;4>d43348o5:4n229>6a?02h8970i78:`3f?84c1>0j=i522e;4>d7d348o5:4n1c9>6a?02h;270i78:`36?84c1>0j=9522e;4>d74348o5:4n139>6a?02h;:70i78:`1g?84c1>0j?n522e;4>d5e348o5:4n3`9>6a?02h9;70i78:3f0?84c1>09h<522e;4>104348o5:4;609>6a?02=<;70i78:57`?84c1>0?9o522e;4>13>348o5:4;599>6a?02=?<70i78:570?84c1>0?9?522e;4>136348o5:4;519>6a?02=>n70i78:56b?84c1>0?84522e;4>12?348o5:4;469>6a?02=>=70i78:562?84c1>0?8=522e;4>15a348o5:4;3d9>6a?02=9o70i78:52f?84c1>0?16d348o5:4;0c9>6a?02=:j70i78:53;?84c1>0?=:522e;4>171348o5:4;149>6a?02=;?706;<0g=2<4nh16>i78:2d;?84c1>08j:522e;4>6`2348o5:46a?028io70i78:0a;?84c1>0:o:522e;4>4e1348o5:4>c49>6a?028i?70;<0g=2<6k916>i78:0`e?84c1>0:nh522e;4>4dc348o5:4>bc9>6a?028hj70i78:0f6?84c1>0:h9522e;4>4b4348o5:4>d39>6a?028n:70i78:0a1?84c1>0:n8522e;4>764348o5:4=009>6a?02;:;70i78:0d`?84c1>0:jo522e;4>4`f348o5:4>f89>6a?028l<70i78:0d0?84c1>0:j?522e;4>4`6348o5:4>f19>6a?028om70m;<0g=2<58h16>i78:32:?84c1>09<5522e;4>760348o5:4=079>6a?02;:>70i78:`d3?84c1>0?4=522e;4>1>5348o5:4nf39>6a?021;o70;<0g=2i78:5:0?84c1>0jin522e;4>dce348o5:4;7g9>6a?02==n70i78:5:7?84c1>0?48522e;4>116348o5:4;6g9~yg728l0;6>>53;0aM40:m1/onj529ae?_24939p8;4;7;73>x"5l0o1>i7k;%0g=c<5l0i0e:198m4d0290/m:<51c:8jd162810e:398m4b2290/m:<51c:8jd162:10e:598m4b4290/m:<51c:8jd162<10e:798m4b6290/m:<51c:8jd162>10e:998m4ea290/m:<51c:8jd162010e:`98m4e5290/m:<51c:8jd162k10e:b98m6`4290/m:<53g08jd162910e>h>:18'e24=;o80bl9>:098m6`7290/m:<53g08jd162;10e9><:18'e24=;o80bl9>:298m165290/m:<53g08jd162=10e9>>:18'e24=;o80bl9>:498m167290/m:<53g08jd162?10e>hi:18'e24=;o80bl9>:698m6`b290/m:<53g08jd162110e>hk:18'e24=;o80bl9>:898m6`d290/m:<53g08jd162h10e>hm:18'e24=;o80bl9>:c98m6ca290/m:<53g08jd162j10e96l:188m74e2900e9om:188m11d2900e9==:188mg7?2900eo8:18'e24=j9<0bl9>:198kg62290/m:<5b148jd162810co>;:18'e24=j9<0bl9>:398kg73290/m:<5b148jd162:10co?<:18'e24=j9<0bl9>:598kg75290/m:<5b148jd162<10co?>:18'e24=j9<0bl9>:798kg77290/m:<5b148jd162>10co>i:18'e24=j9<0bl9>:998kg6b290/m:<5b148jd162010co>k:18'e24=j9<0bl9>:`98kg6d290/m:<5b148jd162k10co><:18'e24=j9<0bl9>:b98k1gd2900n?98f;295?6=8r.hoi4=7208L710j2B9;?j4o8f;>5<5}#kjn1;;l4H354f>N5?;n0c:8n:188yg4c1>0;6<9i:183M40:m1/onj571g8^1562lqo97?>1;d3>43?2jk1;44jf;gg>2>=k00no798:dg9g=4n3f6>5=#:m=1;>64$3f;>=7>3-9nh7;kf:l74=<73g>8<7>4$510>0ba3g>=h7>4n551>5=ih?9h0;7c6>c;28j8:&a5g7)<82d8:g<=#:>8m64mn;%0475<>kj1b8;k50;&b37<3?91em:?52:9l<4c=831b85950;9l03d=831b85m50;9j03e=831b8;o50;9jec5=831d>?<50;&b37<5:81em:?50:9l676=83.j;?4=209me27=921d><750;&b37<5:81em:?58:9l64>=83.j;?4=209me27=121d><850;&b37<5:81em:?5a:9l643=83.j;?4=209me27=j21d><:50;&b37<5:81em:?5c:9l645=83.j;?4=209me27=l21d><<50;&b37<5:81em:?5e:9l647=83.j;?4=209me27=n21d><>50;&b37<5:81em:?51198k76a290/m:<52338jd1628;07bi58m0;6)o82;015>hf?80:?65`23c94?"f?;09><5aa63951=;oc45?7132e9>:4?:%c46?4592dj;<4>7:9l670=83.j;?4=209me27=9110c?<::18'e24=:;;0bl9>:0;8?j45<3:1(l9=:302?kg093;j76a=2283>!g0:389=6`n7082f>=h:8=1<7*n738164=ii>;1=n54o32`>5<#i>81>??4n`52>4b<3`3o87>5$`51>4;h;g6?6=,h=964j<;oc45?7<3`3o=7>5$`51>5$`51>5$`51>5$`51>d5?3gk<=7?4;hc02?6=,h=96l=7;oc45?4<3`k897>5$`51>d5?3gk<=7=4;hc00?6=,h=96l=7;oc45?2<3`k8?7>5$`51>d5?3gk<=7;4;hc06?6=,h=96l=7;oc45?0<3`k8=7>5$`51>d5?3gk<=794;hc1b?6=,h=96l=7;oc45?><3`k9i7>5$`51>d5?3gk<=774;hc1`?6=,h=96l=7;oc45?g<3`k9o7>5$`51>d5?3gk<=7l4;hc1f?6=,h=96l=7;oc45?e<3`k9m7>5$`51>d5?3gk<=7j4;hc1=?6=,h=96l=7;oc45?c<3`k947>5$`51>d5?3gk<=7h4;hc13?6=,h=96l=7;oc45?7732cj>;4?:%c46?g402dj;<4>1:9je72=83.j;?4n399me27=9;10el<<:18'e24=i:20bl9>:018?lg5:3:1(l9=:`1;?kg093;?76gn2083>!g0:3k846`n70821>=ni;:1<7*n738b7==ii>;1=;54i`3e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d152h937co81;3`?>of910;6)o82;c0<>hf?80:h65fa0594?"f?;0j?55aa6395`=:318?lg693:1(l9=:`1;?kg0938?76gn1183>!g0:3k846`n70811>=ni:l1<7*n738b7==ii>;1>;54i`1f>5<#i>81m>64n`52>71<3`k8h7>5$`51>d5?3gk<=7<7;:kb7f<72-k<>7o<8:lb34<5121bm>l50;&b37of:<0;6)o82;c0<>hf?809h65fa0c94?"f?;0j?55aa6396`=5$`51>7b53gk<=7?4;h0g4?6=,h=96?j=;oc45?4<3`8hj7>5$`51>7b53gk<=7=4;h657?6=,h=9698=;oc45?6<3`>==7>5$`51>1053gk<=7?4;h654?6=,h=9698=;oc45?4<3`>>j7>5$`51>1053gk<=7=4;h66a?6=,h=9698=;oc45?2<3`>>h7>5$`51>1053gk<=7;4;h66g?6=,h=9698=;oc45?0<3`>>n7>5$`51>1053gk<=794;h66=?6=,h=9698=;oc45?><3`>>47>5$`51>1053gk<=774;h663?6=,h=9698=;oc45?g<3`>>:7>5$`51>1053gk<=7l4;h661?6=,h=9698=;oc45?e<3`>>87>5$`51>1053gk<=7j4;h667?6=,h=9698=;oc45?c<3`>>>7>5$`51>1053gk<=7h4;h665?6=,h=9698=;oc45?7732c?9=4?:%c46?21:2dj;<4>1:9j01c=83.j;?4;639me27=9;10e9:k:18'e24=:018?l23k3:1(l9=:541?kg093;?76g;4c83>!g0:3>=>6`n70821>=n<=k1<7*n738727=ii>;1=;54i56:>5<#i>818;<4n`52>41<3`>?47>5$`51>1053gk<=7?7;:k702<72-k<>7:92:lb34<6121b89850;&b37<3>;1em:?51`98m122290/m:<54708jd1628h07d:;3;29 d152=<97co81;3`?>o3<;0;6)o82;656>hf?80:h65f45394?"f?;0?:?5aa6395`=;6=4+a609034:318?l24j3:1(l9=:541?kg0938?76g;3`83>!g0:3>=>6`n70811>=n;1>;54i54;>5<#i>818;<4n`52>71<3`>=;7>5$`51>1053gk<=7<7;:k723<72-k<>7:92:lb34<5121b8;;50;&b37<3>;1em:?52`98m103290/m:<54708jd162;h07d::a;29 d152=<97co81;0`?>o3hf?809h65f45694?"f?;0?:?5aa6396`=:>7>5$`51>1763gk<=7>4;h624?6=,h=969?>;oc45?7<3`>;j7>5$`51>1763gk<=7<4;h63a?6=,h=969?>;oc45?5<3`>;h7>5$`51>1763gk<=7:4;h63g?6=,h=969?>;oc45?3<3`>;n7>5$`51>1763gk<=784;h63e?6=,h=969?>;oc45?1<3`>:n7>5$`51>1763gk<=764;h62e?6=,h=969?>;oc45??<3`>:57>5$`51>1763gk<=7o4;h62;oc45?d<3`>:;7>5$`51>1763gk<=7m4;h622?6=,h=969?>;oc45?b<3`>:97>5$`51>1763gk<=7k4;h620?6=,h=969?>;oc45?`<3`>:?7>5$`51>1763gk<=7??;:k74<<72-k<>7:>1:lb34<6921b?ko50;&b37<4n01em:?50:9j7c>=83.j;?4e;29 d152=8?7co81;48?j26l3:1(l9=:507?kg093=07b:=e;29 d152=8?7co81;:8?j25l3:1(l9=:507?kg093307b:=c;29 d152=8?7co81;c8?j25j3:1(l9=:507?kg093h07b:=a;29 d152=8?7co81;a8?j2513:1(l9=:507?kg093n07b:=8;29 d152=8?7co81;g8?j25?3:1(l9=:507?kg093l07b:=6;29 d152=8?7co81;33?>i39j0;6)o82;610>hf?80:=65`a1694?"f?;0j<>5aa6394>=hi981<7*n738b46=ii>;1=65`a1394?"f?;0j<>5aa6396>=hi9:1<7*n738b46=ii>;1?65`9gd94?"f?;0j<>5aa6390>=h1oo1<7*n738b46=ii>;1965`9gf94?"f?;0j<>5aa6392>=h1oi1<7*n738b46=ii>;1;65`9gc94?"f?;0j<>5aa639<>=h1o31<7*n738b46=ii>;1565`9g:94?"f?;0j<>5aa639e>=h1o=1<7*n738b46=ii>;1n65`9g494?"f?;0j<>5aa639g>=h1o?1<7*n738b46=ii>;1h65`9g694?"f?;0j<>5aa639a>=h1o91<7*n738b46=ii>;1j65`9g094?"f?;0j<>5aa63955=<;oc45?7532e2ih4?:%c46?g7;2dj;<4>3:9l=`b=83.j;?4n029me27=9=10c4kl:18'e24=i990bl9>:078?j?bj3:1(l9=:`20?kg093;=76a6e`83>!g0:3k;?6`n70823>=h1l31<7*n738b46=ii>;1=554o8g;>5<#i>81m==4n`52>4?<3f3n;7>5$`51>d643gk<=7?n;:m:a3<72-k<>7o?3:lb34<6j21d5h:50;&b37i>m80;6)o82;c37>hf?80:j65`9d294?"f?;0j<>5aa63965=<;oc45?4532e2hi4?:%c46?g7;2dj;<4=3:9l=ae=83.j;?4n029me27=:=10c4jm:18'e24=i990bl9>:378?jg7i3:1(l9=:`20?kg0938=76an0883>!g0:3k;?6`n70813>=hi921<7*n738b46=ii>;1>554o`24>5<#i>81m==4n`52>7?<3fk;:7>5$`51>d643gk<=77o?3:lb34<5j21d5kl50;&b37i>lh0;6)o82;c37>hf?809j65f1bf94?"f?;0:on5aa6394>=n9jh1<7*n7382gf=ii>;1=65f1bc94?"f?;0:on5aa6396>=n9j31<7*n7382gf=ii>;1?65f1b:94?"f?;0:on5aa6390>=n9j=1<7*n7382gf=ii>;1965f1b494?"f?;0:on5aa6392>=n9j?1<7*n7382gf=ii>;1;65f1b694?"f?;0:on5aa639<>=n9j91<7*n7382gf=ii>;1565f1b394?"f?;0:on5aa639e>=n9j:1<7*n7382gf=ii>;1n65f1cd94?"f?;0:on5aa639g>=n9ko1<7*n7382gf=ii>;1h65f1cf94?"f?;0:on5aa639a>=n9kh1<7*n7382gf=ii>;1j65f1cc94?"f?;0:on5aa63955=3:9j5a3=83.j;?4>cb9me27=9=10e:078?l7c;3:1(l9=:0a`?kg093;=76g>d383>!g0:3;ho6`n70823>=n9m;1<7*n7382gf=ii>;1=554i0f3>5<#i>81=nm4n`52>4?<3`;hj7>5$`51>4ed3gk<=7?n;:k2g`<72-k<>7?lc:lb34<6j21b=n<50;&b37<6kj1em:?51b98m4d2290/m:<51ba8jd1628n07bo9a;29 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d152=<97co81;58?l2213:1(l9=:541?kg093207d::8;29 d152=<97co81;;8?l22?3:1(l9=:541?kg093k07d::6;29 d152=<97co81;`8?l22=3:1(l9=:541?kg093i07d::4;29 d152=<97co81;f8?l22;3:1(l9=:541?kg093o07d::2;29 d152=<97co81;d8?l2293:1(l9=:541?kg093;;76g;5183>!g0:3>=>6`n70825>=n<=o1<7*n738727=ii>;1=?54i56g>5<#i>818;<4n`52>45<3`>?o7>5$`51>1053gk<=7?;;:k70g<72-k<>7:92:lb34<6=21b89o50;&b37<3>;1em:?51798m12>290/m:<54708jd1628=07d:;8;29 d152=<97co81;3;?>o3<>0;6)o82;656>hf?80:565f45494?"f?;0?:?5aa6395d=>6=4+a609034d:9j017=83.j;?4;639me27=9l10e9:?:18'e24=:0d8?l24n3:1(l9=:541?kg0938;76g;3d83>!g0:3>=>6`n70815>=n<:n1<7*n738727=ii>;1>?54i51`>5<#i>818;<4n`52>75<3`>8n7>5$`51>1053gk<=7<;;:k77d<72-k<>7:92:lb34<5=21b8;750;&b37<3>;1em:?52798m10?290/m:<54708jd162;=07d:97;29 d152=<97co81;0;?>o3>?0;6)o82;656>hf?809565f47794?"f?;0?:?5aa6396d=:3d8?j20?3:1(l9=:555?kg093:07d:>2;29 d152=;:7co81;28?l2683:1(l9=:532?kg093;07d:?f;29 d152=;:7co81;08?l27m3:1(l9=:532?kg093907d:?d;29 d152=;:7co81;68?l27k3:1(l9=:532?kg093?07d:?b;29 d152=;:7co81;48?l27i3:1(l9=:532?kg093=07d:>b;29 d152=;:7co81;:8?l26i3:1(l9=:532?kg093307d:>9;29 d152=;:7co81;c8?l2603:1(l9=:532?kg093h07d:>7;29 d152=;:7co81;a8?l26>3:1(l9=:532?kg093n07d:>5;29 d152=;:7co81;g8?l26<3:1(l9=:532?kg093l07d:>3;29 d152=;:7co81;33?>o3800;6)o82;625>hf?80:=65f3gc94?"f?;08j45aa6394>=n;o21<7*n7380b<=ii>;1=65f3g594?"f?;08j45aa6396>=n;o?1<7*n7380b<=ii>;1?65f3g694?"f?;08j45aa6390>=n;o91<7*n7380b<=ii>;1965f3g394?"f?;08j45aa6392>=n;o:1<7*n7380b<=ii>;1;65f41194?"f?;08j45aa639<>=n<981<7*n7380b<=ii>;1565f41394?"f?;08j45aa639e>=n<9:1<7*n7380b<=ii>;1n65f3gd94?"f?;08j45aa639g>=n;oo1<7*n7380b<=ii>;1h65f3gf94?"f?;08j45aa639a>=n;oi1<7*n7380b<=ii>;1j65f3g`94?"f?;08j45aa63955=9?7>5$`51>1433gk<=7?4;n616?6=,h=969<;;oc45?4<3f>9=7>5$`51>1433gk<=7=4;n614?6=,h=969<;;oc45?2<3f>:j7>5$`51>1433gk<=7;4;n62a?6=,h=969<;;oc45?0<3f>:h7>5$`51>1433gk<=794;n61a?6=,h=969<;;oc45?><3f>9h7>5$`51>1433gk<=774;n61g?6=,h=969<;;oc45?g<3f>9n7>5$`51>1433gk<=7l4;n61e?6=,h=969<;;oc45?e<3f>957>5$`51>1433gk<=7j4;n619;7>5$`51>1433gk<=7h4;n612?6=,h=969<;;oc45?7732e?=n4?:%c46?25<2dj;<4>1:9le52=83.j;?4n029me27=821dm=<50;&b3750;&b3721d5km50;&b37=83.j;?4n029me27=i21d5k950;&b37:18'e24=i990bl9>:038?j?bn3:1(l9=:`20?kg093;976a6ed83>!g0:3k;?6`n70827>=h1ln1<7*n738b46=ii>;1=954o8g`>5<#i>81m==4n`52>43<3f3nn7>5$`51>d643gk<=7?9;:m:ad<72-k<>7o?3:lb34<6?21d5h750;&b37i>m?0;6)o82;c37>hf?80:n65`9d694?"f?;0j<>5aa6395f=<;oc45?7b32e2i<4?:%c46?g7;2dj;<4>f:9l=`6=83.j;?4n029me27=:910c4ji:18'e24=i990bl9>:338?j?cm3:1(l9=:`20?kg0938976a6de83>!g0:3k;?6`n70817>=h1mi1<7*n738b46=ii>;1>954o8fa>5<#i>81m==4n`52>73<3fk;m7>5$`51>d643gk<=7<9;:mb4<<72-k<>7o?3:lb34<5?21dm=650;&b37if8<0;6)o82;c37>hf?809n65`9g`94?"f?;0j<>5aa6396f=<;oc45?4b32e2hl4?:%c46?g7;2dj;<4=f:9j5fb=83.j;?4>cb9me27=821b=nl50;&b37<6kj1em:?51:9j5fg=83.j;?4>cb9me27=:21b=n750;&b37<6kj1em:?53:9j5f>=83.j;?4>cb9me27=<21b=n950;&b37<6kj1em:?55:9j5f0=83.j;?4>cb9me27=>21b=n;50;&b37<6kj1em:?57:9j5f2=83.j;?4>cb9me27=021b=n=50;&b37<6kj1em:?59:9j5f7=83.j;?4>cb9me27=i21b=n>50;&b37<6kj1em:?5b:9j5g`=83.j;?4>cb9me27=k21b=ok50;&b37<6kj1em:?5d:9j5gb=83.j;?4>cb9me27=m21b=ol50;&b37<6kj1em:?5f:9j5gg=83.j;?4>cb9me27=9910e:038?l7e?3:1(l9=:0a`?kg093;976g>b783>!g0:3;ho6`n70827>=n9m?1<7*n7382gf=ii>;1=954i0f7>5<#i>81=nm4n`52>43<3`;o?7>5$`51>4ed3gk<=7?9;:k2`7<72-k<>7?lc:lb34<6?21b=i?50;&b37<6kj1em:?51998m4b7290/m:<51ba8jd1628307d?lf;29 d1528ih7co81;3b?>o6kl0;6)o82;3`g>hf?80:n65f1b094?"f?;0:on5aa6395f=6=4+a6095fe5$`51>d0>3gk<=7?4;nc53?6=,h=96l86;oc45?4<3fk=:7>5$`51>d0>3gk<=7=4;nc51?6=,h=96l86;oc45?2<3fk=87>5$`51>d0>3gk<=7;4;nc57?6=,h=96l86;oc45?0<3fk=>7>5$`51>d0>3gk<=794;nc54?6=,h=96l86;oc45?><3fk>j7>5$`51>d0>3gk<=774;nc6a?6=,h=96l86;oc45?g<3fk>h7>5$`51>d0>3gk<=7l4;nc6g?6=,h=96l86;oc45?e<3fk>n7>5$`51>d0>3gk<=7j4;nc6e?6=,h=96l86;oc45?c<3fk>57>5$`51>d0>3gk<=7h4;nc61:9le03=83.j;?4n689me27=9;10cl;;:18'e24=i?30bl9>:018?jg2;3:1(l9=:`4:?kg093;?76an5383>!g0:3k=56`n70821>=hi<;1<7*n738b2<=ii>;1=;54o`73>5<#i>81m;74n`52>41<3fk?j7>5$`51>d0>3gk<=7?7;:mb0`<72-k<>7o99:lb34<6121dm9j50;&b3701em:?51`98kd2d290/m:<5a7;8jd1628h07bo;a;29 d152h<27co81;3`?>if<00;6)o82;c5=>hf?80:h65`a5:94?"f?;0j:45aa6395`=<6=4+a609e3?:318?jg3:3:1(l9=:`4:?kg0938?76an4083>!g0:3k=56`n70811>=hi>:1<7*n738b2<=ii>;1>;54o`4e>5<#i>81m;74n`52>71<3fk=i7>5$`51>d0>3gk<=7<7;:mb2a<72-k<>7o99:lb34<5121dm;m50;&b3701em:?52`98kd0e290/m:<5a7;8jd162;h07bo91;29 d152h<27co81;0`?>if=?0;6)o82;c5=>hf?809h65`a5`94?"f?;0j:45aa6396`=;6=4+a609e3?=;oc45?6<3`8;=7>5$`51>7653gk<=7?4;h034?6=,h=96?>=;oc45?4<3`;mj7>5$`51>7653gk<=7=4;h3ea?6=,h=96?>=;oc45?2<3`;mh7>5$`51>7653gk<=7;4;h3eg?6=,h=96?>=;oc45?0<3`;mn7>5$`51>7653gk<=794;h3ee?6=,h=96?>=;oc45?><3`;m57>5$`51>7653gk<=774;h3e3?6=,h=96?>=;oc45?g<3`;m:7>5$`51>7653gk<=7l4;h3e1?6=,h=96?>=;oc45?e<3`;m87>5$`51>7653gk<=7j4;h3e7?6=,h=96?>=;oc45?c<3`;m>7>5$`51>7653gk<=7h4;h3e5?6=,h=96?>=;oc45?7732c:j=4?:%c46?47:2dj;<4>1:9j5``=83.j;?4=039me27=9;10e:018?l47j3:1(l9=:321?kg093;?76g=0`83>!g0:38;>6`n70821>=n:931<7*n738147=ii>;1=;54i32;>5<#i>81>=<4n`52>41<3`8;;7>5$`51>7653gk<=7?7;:k143<72-k<>7=;50;&b37<58;1em:?51`98m763290/m:<52108jd1628h07d?i8;29 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d152;8:7co81;35?>i5:>0;6)o82;015>hf?80:;65`23494?"f?;09><5aa6395==6=4+a609677;oc45?7f32e9>>4?:%c46?4592dj;<4>b:9l641=83.j;?4=209me27=9j10c?>l:18'e24=:;;0bl9>:0f8?l?c<3:1(l9=:8f0?kg093:07d7k2;29 d1520n87co81;38?l?c93:1(l9=:8f0?kg093807d7k0;29 d1520n87co81;18?l?dn3:1(l9=:8f0?kg093>07d7le;29 d1520n87co81;78?l?dl3:1(l9=:8f0?kg093<07do<9;29 d152h937co81;28?lg4?3:1(l9=:`1;?kg093;07do<6;29 d152h937co81;08?lg4=3:1(l9=:`1;?kg093907do<4;29 d152h937co81;68?lg4;3:1(l9=:`1;?kg093?07do<2;29 d152h937co81;48?lg493:1(l9=:`1;?kg093=07do=f;29 d152h937co81;:8?lg5m3:1(l9=:`1;?kg093307do=d;29 d152h937co81;c8?lg5k3:1(l9=:`1;?kg093h07do=b;29 d152h937co81;a8?lg5i3:1(l9=:`1;?kg093n07do=9;29 d152h937co81;g8?lg503:1(l9=:`1;?kg093l07do=7;29 d152h937co81;33?>of:?0;6)o82;c0<>hf?80:=65fa3694?"f?;0j?55aa63957=<4?:%c46?g402dj;<4>5:9je76=83.j;?4n399me27=9?10el?i:18'e24=i:20bl9>:058?lg6m3:1(l9=:`1;?kg093;376gn1e83>!g0:3k846`n7082=>=ni8i1<7*n738b7==ii>;1=l54i`3a>5<#i>81m>64n`52>4d<3`k:57>5$`51>d5?3gk<=7?l;:kb5=<72-k<>7o<8:lb34<6l21bm<950;&b375;29 d152h937co81;03?>of9=0;6)o82;c0<>hf?809=65fa0194?"f?;0j?55aa63967=:358?lg4l3:1(l9=:`1;?kg0938376gn3b83>!g0:3k846`n7081=>=ni:h1<7*n738b7==ii>;1>l54i`1b>5<#i>81m>64n`52>7d<3`k8<7>5$`51>d5?3gk<=77o<8:lb34<5l21bm3:1(l9=:541?kg093h07d::5;29 d152=<97co81;a8?l22<3:1(l9=:541?kg093n07d::3;29 d152=<97co81;g8?l22:3:1(l9=:541?kg093l07d::1;29 d152=<97co81;33?>o3=90;6)o82;656>hf?80:=65f45g94?"f?;0?:?5aa63957=o6=4+a6090345:9j01g=83.j;?4;639me27=9?10e9:6:18'e24=:058?l2303:1(l9=:541?kg093;376g;4683>!g0:3>=>6`n7082=>=n<=<1<7*n738727=ii>;1=l54i566>5<#i>818;<4n`52>4d<3`>??7>5$`51>1053gk<=7?l;:k707<72-k<>7:92:lb34<6l21b89?50;&b37<3>;1em:?51d98m127290/m:<54708jd1628l07d:o3;l0;6)o82;656>hf?809=65f42f94?"f?;0?:?5aa63967=:358?l21?3:1(l9=:541?kg0938376g;6783>!g0:3>=>6`n7081=>=n;1>l54i547>5<#i>818;<4n`52>7d<3`>>m7>5$`51>1053gk<=77:92:lb34<5l21b89:50;&b37<3>;1em:?52d98m15>290/m:<54708jd162;l07b:87;29 d152===7co81;28?l26:3:1(l9=:532?kg093:07d:>0;29 d152=;:7co81;38?l27n3:1(l9=:532?kg093807d:?e;29 d152=;:7co81;18?l27l3:1(l9=:532?kg093>07d:?c;29 d152=;:7co81;78?l27j3:1(l9=:532?kg093<07d:?a;29 d152=;:7co81;58?l26j3:1(l9=:532?kg093207d:>a;29 d152=;:7co81;;8?l2613:1(l9=:532?kg093k07d:>8;29 d152=;:7co81;`8?l26?3:1(l9=:532?kg093i07d:>6;29 d152=;:7co81;f8?l26=3:1(l9=:532?kg093o07d:>4;29 d152=;:7co81;d8?l26;3:1(l9=:532?kg093;;76g;0883>!g0:3>:=6`n70825>=n;ok1<7*n7380b<=ii>;1<65f3g:94?"f?;08j45aa6395>=n;o=1<7*n7380b<=ii>;1>65f3g794?"f?;08j45aa6397>=n;o>1<7*n7380b<=ii>;1865f3g194?"f?;08j45aa6391>=n;o;1<7*n7380b<=ii>;1:65f3g294?"f?;08j45aa6393>=n<991<7*n7380b<=ii>;1465f41094?"f?;08j45aa639=>=n<9;1<7*n7380b<=ii>;1m65f41294?"f?;08j45aa639f>=n;ol1<7*n7380b<=ii>;1o65f3gg94?"f?;08j45aa639`>=n;on1<7*n7380b<=ii>;1i65f3ga94?"f?;08j45aa639b>=n;oh1<7*n7380b<=ii>;1==54i2ge>5<#i>81?k74n`52>47<3f>997>5$`51>1433gk<=7>4;n617?6=,h=969<;;oc45?7<3f>9>7>5$`51>1433gk<=7<4;n615?6=,h=969<;;oc45?5<3f>9<7>5$`51>1433gk<=7:4;n62b?6=,h=969<;;oc45?3<3f>:i7>5$`51>1433gk<=784;n62`?6=,h=969<;;oc45?1<3f>9i7>5$`51>1433gk<=764;n61`?6=,h=969<;;oc45??<3f>9o7>5$`51>1433gk<=7o4;n61f?6=,h=969<;;oc45?d<3f>9m7>5$`51>1433gk<=7m4;n61=?6=,h=969<;;oc45?b<3f>947>5$`51>1433gk<=7k4;n613?6=,h=969<;;oc45?`<3f>9:7>5$`51>1433gk<=7??;:m75f<72-k<>7:=4:lb34<6921dm=:50;&b37i>ml0;6)o82;c37>hf?80:?65`9df94?"f?;0j<>5aa63951=<;oc45?7132e2il4?:%c46?g7;2dj;<4>7:9l=`?=83.j;?4n029me27=9110c4k7:18'e24=i990bl9>:0;8?j?b?3:1(l9=:`20?kg093;j76a6e783>!g0:3k;?6`n7082f>=h1l>1<7*n738b46=ii>;1=n54o8g0>5<#i>81m==4n`52>4b<3f3n>7>5$`51>d643gk<=7?j;:m:a4<72-k<>7o?3:lb34<6n21d5h>50;&b37i>lm0;6)o82;c37>hf?809?65`9ea94?"f?;0j<>5aa63961=<;oc45?4132ej<44?:%c46?g7;2dj;<4=7:9le5>=83.j;?4n029me27=:110cl>8:18'e24=i990bl9>:3;8?jg7>3:1(l9=:`20?kg0938j76an0483>!g0:3k;?6`n7081f>=h1oh1<7*n738b46=ii>;1>n54o8d3>5<#i>81m==4n`52>7b<3f3n97>5$`51>d643gk<=77o?3:lb34<5n21b=nj50;&b37<6kj1em:?50:9j5fd=83.j;?4>cb9me27=921b=no50;&b37<6kj1em:?52:9j5f?=83.j;?4>cb9me27=;21b=n650;&b37<6kj1em:?54:9j5f1=83.j;?4>cb9me27==21b=n850;&b37<6kj1em:?56:9j5f3=83.j;?4>cb9me27=?21b=n:50;&b37<6kj1em:?58:9j5f5=83.j;?4>cb9me27=121b=n?50;&b37<6kj1em:?5a:9j5f6=83.j;?4>cb9me27=j21b=oh50;&b37<6kj1em:?5c:9j5gc=83.j;?4>cb9me27=l21b=oj50;&b37<6kj1em:?5e:9j5gd=83.j;?4>cb9me27=n21b=oo50;&b37<6kj1em:?51198m4d>290/m:<51ba8jd1628;07d?m7;29 d1528ih7co81;31?>o6j?0;6)o82;3`g>hf?80:?65f1e794?"f?;0:on5aa63951=7:9j5a7=83.j;?4>cb9me27=9110e:0;8?l7dn3:1(l9=:0a`?kg093;j76g>cd83>!g0:3;ho6`n7082f>=n9j81<7*n7382gf=ii>;1=n54i0`6>5<#i>81=nm4n`52>4b<3fk=m7>5$`51>d0>3gk<=7>4;nc55$`51>d0>3gk<=7<4;nc52?6=,h=96l86;oc45?5<3fk=97>5$`51>d0>3gk<=7:4;nc50?6=,h=96l86;oc45?3<3fk=?7>5$`51>d0>3gk<=784;nc56?6=,h=96l86;oc45?1<3fk=<7>5$`51>d0>3gk<=764;nc6b?6=,h=96l86;oc45??<3fk>i7>5$`51>d0>3gk<=7o4;nc6`?6=,h=96l86;oc45?d<3fk>o7>5$`51>d0>3gk<=7m4;nc6f?6=,h=96l86;oc45?b<3fk>m7>5$`51>d0>3gk<=7k4;nc6=?6=,h=96l86;oc45?`<3fk>47>5$`51>d0>3gk<=7??;:mb12<72-k<>7o99:lb34<6921dm8;50;&b3701em:?51398kd33290/m:<5a7;8jd1628907bo:3;29 d152h<27co81;37?>if=;0;6)o82;c5=>hf?80:965`a4394?"f?;0j:45aa63953=9:9le1b=83.j;?4n689me27=9h10cl:l:18'e24=i?30bl9>:0`8?jg3i3:1(l9=:`4:?kg093;h76an4883>!g0:3k=56`n7082`>=hi=21<7*n738b2<=ii>;1=h54o`64>5<#i>81m;74n`52>4`<3fk?:7>5$`51>d0>3gk<=77o99:lb34<5921dm9:50;&b3701em:?52398kd24290/m:<5a7;8jd162;907bo;2;29 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7b?21;27)=jd;7gb>h3810;7c:<0;28 15426=5+a1a9<>hf?<0:7)l>a;:2<>"e9k0jk01/>:=h08o1<75f49594?=h<5aa6394>=h:;:1<7*n738164=ii>;1=65`20d94?"f?;09><5aa6396>=h:8o1<7*n738164=ii>;1?65`20f94?"f?;09><5aa6390>=h:8i1<7*n738164=ii>;1965`20`94?"f?;09><5aa6392>=h:8k1<7*n738164=ii>;1;65`20;94?"f?;09><5aa639<>=h:821<7*n738164=ii>;1565`20494?"f?;09><5aa639e>=h:8?1<7*n738164=ii>;1n65`20694?"f?;09><5aa639g>=h:891<7*n738164=ii>;1h65`20094?"f?;09><5aa639a>=h:8;1<7*n738164=ii>;1j65`20294?"f?;09><5aa63955=;oc45?7532e93:9l67g=83.j;?4=209me27=9=10c?<6:18'e24=:;;0bl9>:078?j4503:1(l9=:302?kg093;=76a=2683>!g0:389=6`n70823>=h:;<1<7*n738164=ii>;1=554o306>5<#i>81>??4n`52>4?<3f8987>5$`51>7463gk<=7?n;:m166<72-k<>7<=1:lb34<6j21d><950;&b37<5:81em:?51b98k76d290/m:<52338jd1628n07d7k4;29 d1520n87co81;28?l?c:3:1(l9=:8f0?kg093;07d7k1;29 d1520n87co81;08?l?c83:1(l9=:8f0?kg093907d7lf;29 d1520n87co81;68?l?dm3:1(l9=:8f0?kg093?07d7ld;29 d1520n87co81;48?lg413:1(l9=:`1;?kg093:07do<7;29 d152h937co81;38?lg4>3:1(l9=:`1;?kg093807do<5;29 d152h937co81;18?lg4<3:1(l9=:`1;?kg093>07do<3;29 d152h937co81;78?lg4:3:1(l9=:`1;?kg093<07do<1;29 d152h937co81;58?lg5n3:1(l9=:`1;?kg093207do=e;29 d152h937co81;;8?lg5l3:1(l9=:`1;?kg093k07do=c;29 d152h937co81;`8?lg5j3:1(l9=:`1;?kg093i07do=a;29 d152h937co81;f8?lg513:1(l9=:`1;?kg093o07do=8;29 d152h937co81;d8?lg5?3:1(l9=:`1;?kg093;;76gn2783>!g0:3k846`n70825>=ni;>1<7*n738b7==ii>;1=?54i`00>5<#i>81m>64n`52>45<3`k9>7>5$`51>d5?3gk<=7?;;:kb64<72-k<>7o<8:lb34<6=21bm?>50;&b37e;29 d152h937co81;3;?>of9m0;6)o82;c0<>hf?80:565fa0a94?"f?;0j?55aa6395d=d:9je41=83.j;?4n399me27=9l10el?9:18'e24=i:20bl9>:0d8?lg6=3:1(l9=:`1;?kg0938;76gn1583>!g0:3k846`n70815>=ni891<7*n738b7==ii>;1>?54i`31>5<#i>81m>64n`52>75<3`k:=7>5$`51>d5?3gk<=7<;;:kb55<72-k<>7o<8:lb34<5=21bm>h50;&b37of;j0;6)o82;c0<>hf?809565fa2`94?"f?;0j?55aa6396d=84?:%c46?g402dj;<4=d:9je4g=83.j;?4n399me27=:l10el>i:18'e24=i:20bl9>:3d8?l4c;3:1(l9=:3f1?kg093:07d07d::d;29 d152=<97co81;78?l22k3:1(l9=:541?kg093<07d::b;29 d152=<97co81;58?l2213:1(l9=:541?kg093207d::8;29 d152=<97co81;;8?l22?3:1(l9=:541?kg093k07d::6;29 d152=<97co81;`8?l22=3:1(l9=:541?kg093i07d::4;29 d152=<97co81;f8?l22;3:1(l9=:541?kg093o07d::2;29 d152=<97co81;d8?l2293:1(l9=:541?kg093;;76g;5183>!g0:3>=>6`n70825>=n<=o1<7*n738727=ii>;1=?54i56g>5<#i>818;<4n`52>45<3`>?o7>5$`51>1053gk<=7?;;:k70g<72-k<>7:92:lb34<6=21b89o50;&b37<3>;1em:?51798m12>290/m:<54708jd1628=07d:;8;29 d152=<97co81;3;?>o3<>0;6)o82;656>hf?80:565f45494?"f?;0?:?5aa6395d=>6=4+a609034d:9j017=83.j;?4;639me27=9l10e9:?:18'e24=:0d8?l24n3:1(l9=:541?kg0938;76g;3d83>!g0:3>=>6`n70815>=n<:n1<7*n738727=ii>;1>?54i51`>5<#i>818;<4n`52>75<3`>8n7>5$`51>1053gk<=7<;;:k77d<72-k<>7:92:lb34<5=21b8;750;&b37<3>;1em:?52798m10?290/m:<54708jd162;=07d:97;29 d152=<97co81;0;?>o3>?0;6)o82;656>hf?809565f47794?"f?;0?:?5aa6396d=:3d8?j20?3:1(l9=:555?kg093:07d:>2;29 d152=;:7co81;28?l2683:1(l9=:532?kg093;07d:?f;29 d152=;:7co81;08?l27m3:1(l9=:532?kg093907d:?d;29 d152=;:7co81;68?l27k3:1(l9=:532?kg093?07d:?b;29 d152=;:7co81;48?l27i3:1(l9=:532?kg093=07d:>b;29 d152=;:7co81;:8?l26i3:1(l9=:532?kg093307d:>9;29 d152=;:7co81;c8?l2603:1(l9=:532?kg093h07d:>7;29 d152=;:7co81;a8?l26>3:1(l9=:532?kg093n07d:>5;29 d152=;:7co81;g8?l26<3:1(l9=:532?kg093l07d:>3;29 d152=;:7co81;33?>o3800;6)o82;625>hf?80:=65f3gc94?"f?;08j45aa6394>=n;o21<7*n7380b<=ii>;1=65f3g594?"f?;08j45aa6396>=n;o?1<7*n7380b<=ii>;1?65f3g694?"f?;08j45aa6390>=n;o91<7*n7380b<=ii>;1965f3g394?"f?;08j45aa6392>=n;o:1<7*n7380b<=ii>;1;65f41194?"f?;08j45aa639<>=n<981<7*n7380b<=ii>;1565f41394?"f?;08j45aa639e>=n<9:1<7*n7380b<=ii>;1n65f3gd94?"f?;08j45aa639g>=n;oo1<7*n7380b<=ii>;1h65f3gf94?"f?;08j45aa639a>=n;oi1<7*n7380b<=ii>;1j65f3g`94?"f?;08j45aa63955=9?7>5$`51>1433gk<=7?4;n616?6=,h=969<;;oc45?4<3f>9=7>5$`51>1433gk<=7=4;n614?6=,h=969<;;oc45?2<3f>:j7>5$`51>1433gk<=7;4;n62a?6=,h=969<;;oc45?0<3f>:h7>5$`51>1433gk<=794;n61a?6=,h=969<;;oc45?><3f>9h7>5$`51>1433gk<=774;n61g?6=,h=969<;;oc45?g<3f>9n7>5$`51>1433gk<=7l4;n61e?6=,h=969<;;oc45?e<3f>957>5$`51>1433gk<=7j4;n619;7>5$`51>1433gk<=7h4;n612?6=,h=969<;;oc45?7732e?=n4?:%c46?25<2dj;<4>1:9le52=83.j;?4n029me27=821dm=<50;&b3750;&b3721d5km50;&b37=83.j;?4n029me27=i21d5k950;&b37:18'e24=i990bl9>:038?j?bn3:1(l9=:`20?kg093;976a6ed83>!g0:3k;?6`n70827>=h1ln1<7*n738b46=ii>;1=954o8g`>5<#i>81m==4n`52>43<3f3nn7>5$`51>d643gk<=7?9;:m:ad<72-k<>7o?3:lb34<6?21d5h750;&b37i>m?0;6)o82;c37>hf?80:n65`9d694?"f?;0j<>5aa6395f=<;oc45?7b32e2i<4?:%c46?g7;2dj;<4>f:9l=`6=83.j;?4n029me27=:910c4ji:18'e24=i990bl9>:338?j?cm3:1(l9=:`20?kg0938976a6de83>!g0:3k;?6`n70817>=h1mi1<7*n738b46=ii>;1>954o8fa>5<#i>81m==4n`52>73<3fk;m7>5$`51>d643gk<=7<9;:mb4<<72-k<>7o?3:lb34<5?21dm=650;&b37if8<0;6)o82;c37>hf?809n65`9g`94?"f?;0j<>5aa6396f=<;oc45?4b32e2hl4?:%c46?g7;2dj;<4=f:9j5fb=83.j;?4>cb9me27=821b=nl50;&b37<6kj1em:?51:9j5fg=83.j;?4>cb9me27=:21b=n750;&b37<6kj1em:?53:9j5f>=83.j;?4>cb9me27=<21b=n950;&b37<6kj1em:?55:9j5f0=83.j;?4>cb9me27=>21b=n;50;&b37<6kj1em:?57:9j5f2=83.j;?4>cb9me27=021b=n=50;&b37<6kj1em:?59:9j5f7=83.j;?4>cb9me27=i21b=n>50;&b37<6kj1em:?5b:9j5g`=83.j;?4>cb9me27=k21b=ok50;&b37<6kj1em:?5d:9j5gb=83.j;?4>cb9me27=m21b=ol50;&b37<6kj1em:?5f:9j5gg=83.j;?4>cb9me27=9910e:038?l7e?3:1(l9=:0a`?kg093;976g>b783>!g0:3;ho6`n70827>=n9m?1<7*n7382gf=ii>;1=954i0f7>5<#i>81=nm4n`52>43<3`;o?7>5$`51>4ed3gk<=7?9;:k2`7<72-k<>7?lc:lb34<6?21b=i?50;&b37<6kj1em:?51998m4b7290/m:<51ba8jd1628307d?lf;29 d1528ih7co81;3b?>o6kl0;6)o82;3`g>hf?80:n65f1b094?"f?;0:on5aa6395f=6=4+a6095fe5$`51>d0>3gk<=7?4;nc53?6=,h=96l86;oc45?4<3fk=:7>5$`51>d0>3gk<=7=4;nc51?6=,h=96l86;oc45?2<3fk=87>5$`51>d0>3gk<=7;4;nc57?6=,h=96l86;oc45?0<3fk=>7>5$`51>d0>3gk<=794;nc54?6=,h=96l86;oc45?><3fk>j7>5$`51>d0>3gk<=774;nc6a?6=,h=96l86;oc45?g<3fk>h7>5$`51>d0>3gk<=7l4;nc6g?6=,h=96l86;oc45?e<3fk>n7>5$`51>d0>3gk<=7j4;nc6e?6=,h=96l86;oc45?c<3fk>57>5$`51>d0>3gk<=7h4;nc61:9le03=83.j;?4n689me27=9;10cl;;:18'e24=i?30bl9>:018?jg2;3:1(l9=:`4:?kg093;?76an5383>!g0:3k=56`n70821>=hi<;1<7*n738b2<=ii>;1=;54o`73>5<#i>81m;74n`52>41<3fk?j7>5$`51>d0>3gk<=7?7;:mb0`<72-k<>7o99:lb34<6121dm9j50;&b3701em:?51`98kd2d290/m:<5a7;8jd1628h07bo;a;29 d152h<27co81;3`?>if<00;6)o82;c5=>hf?80:h65`a5:94?"f?;0j:45aa6395`=<6=4+a609e3?:318?jg3:3:1(l9=:`4:?kg0938?76an4083>!g0:3k=56`n70811>=hi>:1<7*n738b2<=ii>;1>;54o`4e>5<#i>81m;74n`52>71<3fk=i7>5$`51>d0>3gk<=7<7;:mb2a<72-k<>7o99:lb34<5121dm;m50;&b3701em:?52`98kd0e290/m:<5a7;8jd162;h07bo91;29 d152h<27co81;0`?>if=?0;6)o82;c5=>hf?809h65`a5`94?"f?;0j:45aa6396`=;6=4+a609e3?=;oc45?6<3`8;=7>5$`51>7653gk<=7?4;h034?6=,h=96?>=;oc45?4<3`;mj7>5$`51>7653gk<=7=4;h3ea?6=,h=96?>=;oc45?2<3`;mh7>5$`51>7653gk<=7;4;h3eg?6=,h=96?>=;oc45?0<3`;mn7>5$`51>7653gk<=794;h3ee?6=,h=96?>=;oc45?><3`;m57>5$`51>7653gk<=774;h3e3?6=,h=96?>=;oc45?g<3`;m:7>5$`51>7653gk<=7l4;h3e1?6=,h=96?>=;oc45?e<3`;m87>5$`51>7653gk<=7j4;h3e7?6=,h=96?>=;oc45?c<3`;m>7>5$`51>7653gk<=7h4;h3e5?6=,h=96?>=;oc45?7732c:j=4?:%c46?47:2dj;<4>1:9j5``=83.j;?4=039me27=9;10e:018?l47j3:1(l9=:321?kg093;?76g=0`83>!g0:38;>6`n70821>=n:931<7*n738147=ii>;1=;54i32;>5<#i>81>=<4n`52>41<3`8;;7>5$`51>7653gk<=7?7;:k143<72-k<>7=;50;&b37<58;1em:?51`98m763290/m:<52108jd1628h07d?i8;29 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d152=<97co81;58?l2213:1(l9=:541?kg093207d::8;29 d152=<97co81;;8?l22?3:1(l9=:541?kg093k07d::6;29 d152=<97co81;`8?l22=3:1(l9=:541?kg093i07d::4;29 d152=<97co81;f8?l22;3:1(l9=:541?kg093o07d::2;29 d152=<97co81;d8?l2293:1(l9=:541?kg093;;76g;5183>!g0:3>=>6`n70825>=n<=o1<7*n738727=ii>;1=?54i56g>5<#i>818;<4n`52>45<3`>?o7>5$`51>1053gk<=7?;;:k70g<72-k<>7:92:lb34<6=21b89o50;&b37<3>;1em:?51798m12>290/m:<54708jd1628=07d:;8;29 d152=<97co81;3;?>o3<>0;6)o82;656>hf?80:565f45494?"f?;0?:?5aa6395d=>6=4+a609034d:9j017=83.j;?4;639me27=9l10e9:?:18'e24=:0d8?l24n3:1(l9=:541?kg0938;76g;3d83>!g0:3>=>6`n70815>=n<:n1<7*n738727=ii>;1>?54i51`>5<#i>818;<4n`52>75<3`>8n7>5$`51>1053gk<=7<;;:k77d<72-k<>7:92:lb34<5=21b8;750;&b37<3>;1em:?52798m10?290/m:<54708jd162;=07d:97;29 d152=<97co81;0;?>o3>?0;6)o82;656>hf?809565f47794?"f?;0?:?5aa6396d=:3d8?j20?3:1(l9=:555?kg093:07d:>2;29 d152=;:7co81;28?l2683:1(l9=:532?kg093;07d:?f;29 d152=;:7co81;08?l27m3:1(l9=:532?kg093907d:?d;29 d152=;:7co81;68?l27k3:1(l9=:532?kg093?07d:?b;29 d152=;:7co81;48?l27i3:1(l9=:532?kg093=07d:>b;29 d152=;:7co81;:8?l26i3:1(l9=:532?kg093307d:>9;29 d152=;:7co81;c8?l2603:1(l9=:532?kg093h07d:>7;29 d152=;:7co81;a8?l26>3:1(l9=:532?kg093n07d:>5;29 d152=;:7co81;g8?l26<3:1(l9=:532?kg093l07d:>3;29 d152=;:7co81;33?>o3800;6)o82;625>hf?80:=65f3gc94?"f?;08j45aa6394>=n;o21<7*n7380b<=ii>;1=65f3g594?"f?;08j45aa6396>=n;o?1<7*n7380b<=ii>;1?65f3g694?"f?;08j45aa6390>=n;o91<7*n7380b<=ii>;1965f3g394?"f?;08j45aa6392>=n;o:1<7*n7380b<=ii>;1;65f41194?"f?;08j45aa639<>=n<981<7*n7380b<=ii>;1565f41394?"f?;08j45aa639e>=n<9:1<7*n7380b<=ii>;1n65f3gd94?"f?;08j45aa639g>=n;oo1<7*n7380b<=ii>;1h65f3gf94?"f?;08j45aa639a>=n;oi1<7*n7380b<=ii>;1j65f3g`94?"f?;08j45aa63955=9?7>5$`51>1433gk<=7?4;n616?6=,h=969<;;oc45?4<3f>9=7>5$`51>1433gk<=7=4;n614?6=,h=969<;;oc45?2<3f>:j7>5$`51>1433gk<=7;4;n62a?6=,h=969<;;oc45?0<3f>:h7>5$`51>1433gk<=794;n61a?6=,h=969<;;oc45?><3f>9h7>5$`51>1433gk<=774;n61g?6=,h=969<;;oc45?g<3f>9n7>5$`51>1433gk<=7l4;n61e?6=,h=969<;;oc45?e<3f>957>5$`51>1433gk<=7j4;n619;7>5$`51>1433gk<=7h4;n612?6=,h=969<;;oc45?7732e?=n4?:%c46?25<2dj;<4>1:9le52=83.j;?4n029me27=821dm=<50;&b3750;&b3721d5km50;&b37=83.j;?4n029me27=i21d5k950;&b37:18'e24=i990bl9>:038?j?bn3:1(l9=:`20?kg093;976a6ed83>!g0:3k;?6`n70827>=h1ln1<7*n738b46=ii>;1=954o8g`>5<#i>81m==4n`52>43<3f3nn7>5$`51>d643gk<=7?9;:m:ad<72-k<>7o?3:lb34<6?21d5h750;&b37i>m?0;6)o82;c37>hf?80:n65`9d694?"f?;0j<>5aa6395f=<;oc45?7b32e2i<4?:%c46?g7;2dj;<4>f:9l=`6=83.j;?4n029me27=:910c4ji:18'e24=i990bl9>:338?j?cm3:1(l9=:`20?kg0938976a6de83>!g0:3k;?6`n70817>=h1mi1<7*n738b46=ii>;1>954o8fa>5<#i>81m==4n`52>73<3fk;m7>5$`51>d643gk<=7<9;:mb4<<72-k<>7o?3:lb34<5?21dm=650;&b37if8<0;6)o82;c37>hf?809n65`9g`94?"f?;0j<>5aa6396f=<;oc45?4b32e2hl4?:%c46?g7;2dj;<4=f:9j5fb=83.j;?4>cb9me27=821b=nl50;&b37<6kj1em:?51:9j5fg=83.j;?4>cb9me27=:21b=n750;&b37<6kj1em:?53:9j5f>=83.j;?4>cb9me27=<21b=n950;&b37<6kj1em:?55:9j5f0=83.j;?4>cb9me27=>21b=n;50;&b37<6kj1em:?57:9j5f2=83.j;?4>cb9me27=021b=n=50;&b37<6kj1em:?59:9j5f7=83.j;?4>cb9me27=i21b=n>50;&b37<6kj1em:?5b:9j5g`=83.j;?4>cb9me27=k21b=ok50;&b37<6kj1em:?5d:9j5gb=83.j;?4>cb9me27=m21b=ol50;&b37<6kj1em:?5f:9j5gg=83.j;?4>cb9me27=9910e:038?l7e?3:1(l9=:0a`?kg093;976g>b783>!g0:3;ho6`n70827>=n9m?1<7*n7382gf=ii>;1=954i0f7>5<#i>81=nm4n`52>43<3`;o?7>5$`51>4ed3gk<=7?9;:k2`7<72-k<>7?lc:lb34<6?21b=i?50;&b37<6kj1em:?51998m4b7290/m:<51ba8jd1628307d?lf;29 d1528ih7co81;3b?>o6kl0;6)o82;3`g>hf?80:n65f1b094?"f?;0:on5aa6395f=6=4+a6095fe5$`51>d0>3gk<=7?4;nc53?6=,h=96l86;oc45?4<3fk=:7>5$`51>d0>3gk<=7=4;nc51?6=,h=96l86;oc45?2<3fk=87>5$`51>d0>3gk<=7;4;nc57?6=,h=96l86;oc45?0<3fk=>7>5$`51>d0>3gk<=794;nc54?6=,h=96l86;oc45?><3fk>j7>5$`51>d0>3gk<=774;nc6a?6=,h=96l86;oc45?g<3fk>h7>5$`51>d0>3gk<=7l4;nc6g?6=,h=96l86;oc45?e<3fk>n7>5$`51>d0>3gk<=7j4;nc6e?6=,h=96l86;oc45?c<3fk>57>5$`51>d0>3gk<=7h4;nc61:9le03=83.j;?4n689me27=9;10cl;;:18'e24=i?30bl9>:018?jg2;3:1(l9=:`4:?kg093;?76an5383>!g0:3k=56`n70821>=hi<;1<7*n738b2<=ii>;1=;54o`73>5<#i>81m;74n`52>41<3fk?j7>5$`51>d0>3gk<=7?7;:mb0`<72-k<>7o99:lb34<6121dm9j50;&b3701em:?51`98kd2d290/m:<5a7;8jd1628h07bo;a;29 d152h<27co81;3`?>if<00;6)o82;c5=>hf?80:h65`a5:94?"f?;0j:45aa6395`=<6=4+a609e3?:318?jg3:3:1(l9=:`4:?kg0938?76an4083>!g0:3k=56`n70811>=hi>:1<7*n738b2<=ii>;1>;54o`4e>5<#i>81m;74n`52>71<3fk=i7>5$`51>d0>3gk<=7<7;:mb2a<72-k<>7o99:lb34<5121dm;m50;&b3701em:?52`98kd0e290/m:<5a7;8jd162;h07bo91;29 d152h<27co81;0`?>if=?0;6)o82;c5=>hf?809h65`a5`94?"f?;0j:45aa6396`=;6=4+a609e3?=;oc45?6<3`8;=7>5$`51>7653gk<=7?4;h034?6=,h=96?>=;oc45?4<3`;mj7>5$`51>7653gk<=7=4;h3ea?6=,h=96?>=;oc45?2<3`;mh7>5$`51>7653gk<=7;4;h3eg?6=,h=96?>=;oc45?0<3`;mn7>5$`51>7653gk<=794;h3ee?6=,h=96?>=;oc45?><3`;m57>5$`51>7653gk<=774;h3e3?6=,h=96?>=;oc45?g<3`;m:7>5$`51>7653gk<=7l4;h3e1?6=,h=96?>=;oc45?e<3`;m87>5$`51>7653gk<=7j4;h3e7?6=,h=96?>=;oc45?c<3`;m>7>5$`51>7653gk<=7h4;h3e5?6=,h=96?>=;oc45?7732c:j=4?:%c46?47:2dj;<4>1:9j5``=83.j;?4=039me27=9;10e:018?l47j3:1(l9=:321?kg093;?76g=0`83>!g0:38;>6`n70821>=n:931<7*n738147=ii>;1=;54i32;>5<#i>81>=<4n`52>41<3`8;;7>5$`51>7653gk<=7?7;:k143<72-k<>7=;50;&b37<58;1em:?51`98m763290/m:<52108jd1628h07d?i8;29 d152;:97co81;3`?>o6mm0;6)o82;036>hf?80:h65`a1f94?=nio:1<75f49294?=n<181<75fag094?=n08n1<75f49394?=nio;1<75fad:94?=n<191<75`260a>5<5<5<5<5<5<6=44o556>5<#i>818:84n`52>4=5<#i>818:84n`52>6=5<#i>818:>4n`52>4=52z\2fa=::m3<69=i;|q2fg<72;qU=ol4=3f:3?24m2wx=oo50;0xZ4df348o5:4;3e9~w4d>2909wS?m9:?1`<1=<:i0q~?m7;296~X6j>16>i78:51a?xu6j?0;6?uQ1c4897b>?3>8m6s|1e794?4|V8n>70;5l0=18;64}r3g7?6=:rT:h>522e;4>1003ty:h?4?:3y]5a4<5;n2;7:96:p5a7=838pR;<0g=2<3><1vvP>cg9>6a?02=?j7p}>cd83>7}Y9jo01?j67;67b>{t9j81<70?895rs0`6>5<5sW;i963=d85906?52z\0b2=::m3<6>h8;|q0b0<72;qU?k;4=3f:3?5a=2wx?k:50;0xZ6`3348o5:4i78:2d2?xu4n90;6?uQ3g2897b>?39m<6s|41194?4|V=:870;5l0=18=<4}r635?6=:rT?<<522e;4>1663ty?<=4?:3y]056<5;n2;7:?0:p7c`=838pR>hi;<0g=2<4no1v>hj:181[5am279h4953gg8yv5al3:1>vP6a?02:lo7p}7}Y;oi01?j67;1eg>{t;oh1<708jo5rs2ge>5<5sW9nj63=d8597``3o7>52z\72909wSl?9:?1`<1=1ml0q~l?8;296~Xe8116>i78:8ff?xue8>0;6?uQb15897b>?33oh6s|b1794?4|Vk:>70;5l0=15il4}r`20?6=:rTi=9522e;4>d6f3tyi=>4?:3y]f45<5;n2;7o?9:pf44=838pRo?=;<0g=2:181[d69279h495a158yvd683:1>vPm119>6a?02h:=7p}m0g83>7}Yj9l01?j67;c31>{tj9o1<702jo5rsc2g>5<5sWh;h63=d859=c652z\a4f=::m3<64k:;|qa46<72;qUn==4=3f:3??ci2wx>i79:18;840?o02h5522e;4>1>0348o5:46d39>6a?020n:70i78:3ae?xu3ij0;6okt=354a?11i2T?mn522e;4>10b348o5:4;6b9>6a?02=ko16>i78:`1:?84c1>0j?:522e;4>d51348o5:4n349>6a?02h9?70i78:`0e?84c1>0j>h522e;4>d4c348o5:4n2b9>6a?02h8i70i78:`04?84c1>0j>;522e;4>d43348o5:4n229>6a?02h8970i78:`3f?84c1>0j=i522e;4>d7d348o5:4n1c9>6a?02h;270i78:`36?84c1>0j=9522e;4>d74348o5:4n139>6a?02h;:70i78:`1g?84c1>0j?n522e;4>d5e348o5:4n3`9>6a?02h9;70i78:3f0?84c1>09h<522e;4>104348o5:4;609>6a?02=<;70i78:57`?84c1>0?9o522e;4>13>348o5:4;599>6a?02=?<70i78:570?84c1>0?9?522e;4>136348o5:4;519>6a?02=>n70i78:56b?84c1>0?84522e;4>12?348o5:4;469>6a?02=>=70i78:562?84c1>0?8=522e;4>175348o5:4;119>6a?02=:m70k;<0g=2<38j16>i78:52a?84c1>0?17e348o5:4;1`9>6a?02=;270i78:536?84c1>0?=9522e;4>174348o5:4;089>6a?02:lj70i78:0ab?84c1>0:o4522e;4>4e?348o5:4>c69>6a?028i=70i78:0a2?84c1>0:o=522e;4>4da348o5:4>bd9>6a?028ho70i78:0`4?84c1>0:n;522e;4>4b2348o5:4>d59>6a?028n870;<0g=2<6l916>i78:0ae?84c1>0:oh522e;4>4e5348o5:4>b49>6a?02;:870?;<0g=2<6no16>i78:0df?84c1>0:ji522e;4>4`d348o5:4>fc9>6a?028lj70i78:0d6?84c1>0:j9522e;4>4`4348o5:4>f39>6a?028l:70i78:32a?84c1>0976>348o5:4=099>6a?02;:<70:;<0g=2<58=16>i78:0d;?84c1>0:ii522e;4>d`7348o5:4;819>6a?02=2970i78:`d2?84c1>0ji5522e;4>1>4348o5:4neb9>6a?02hoi70i78:`gg?84c1>0?4;522e;4>1>3348o5:4;849>6a?02==:70i5+cbf96=b73S>8=7=t6485g?132t.9h4k52e;g?!4c1o09h4m4i0`g>5<#i>81=om4n`52>5=5<#i>81=om4n`52>7=54i0`4>5<#i>81=om4n`52>1=5<#i>81=om4n`52>3=5<#i>81=om4n`52>==5<#i>81=om4n`52>d=5<#i>81=om4n`52>f=5<#i>81=om4n`52>`=6=4+a6095ge5<#i>81?k84n`52>5=6=4+a6097c05<#i>81?k84n`52>7=54i2d2>5<#i>81?k84n`52>1=5<#i>81?k84n`52>3=5<#i>81?k84n`52>==5<#i>81?k84n`52>d=5<#i>81?k84n`52>f=5<#i>81?k84n`52>`=5<5<5<5<5<#i>81n=o4n`52>5=5<#i>81n=o4n`52>7=54oc26>5<#i>81n=o4n`52>1=5<#i>81n=o4n`52>3=5<#i>81n=o4n`52>==5<#i>81n=o4n`52>d=5<#i>81n=o4n`52>f=5<#i>81n=o4n`52>`=5<51;294~"dkm09;><4H354f>N5?;n0c4j7:188yg40?l0;6<4?:1y'gfb=??h0D?98b:J137b`}c=3;:=7h?:07;>fg=?00nj7kk:6:9g<eb83?k4c<3:0b?j::19'6a1=?:20(?j7:93:?!5bl3?oj6`;0983?k2483:0(9=<:4fe?k21l3:0b99=:19m0dg=82.3=54j0:l;5d<73g2:o7>4n8f6>5=#i9i146`n7482?!d6i32:46*m1c8b4f=#j8i1ng723-8<>h46c89'624a20ij7)<8318:gf=n;1>65`80g94?=n<1=1<75`47`94?=n<1i1<75f47a94?=n;1<65`23294?"f?;09><5aa6395>=h:8l1<7*n738164=ii>;1>65`20g94?"f?;09><5aa6397>=h:8n1<7*n738164=ii>;1865`20a94?"f?;09><5aa6391>=h:8h1<7*n738164=ii>;1:65`20c94?"f?;09><5aa6393>=h:831<7*n738164=ii>;1465`20:94?"f?;09><5aa639=>=h:8<1<7*n738164=ii>;1m65`20794?"f?;09><5aa639f>=h:8>1<7*n738164=ii>;1o65`20194?"f?;09><5aa639`>=h:881<7*n738164=ii>;1i65`20394?"f?;09><5aa639b>=h:8:1<7*n738164=ii>;1==54o32e>5<#i>81>??4n`52>47<3f8;i7>5$`51>7463gk<=7?=;:m14a<72-k<>7<=1:lb34<6;21d>?o50;&b37<5:81em:?51598k74>290/m:<52338jd1628?07b<=8;29 d152;8:7co81;35?>i5:>0;6)o82;015>hf?80:;65`23494?"f?;09><5aa6395==6=4+a609677;oc45?7f32e9>>4?:%c46?4592dj;<4>b:9l641=83.j;?4=209me27=9j10c?>l:18'e24=:;;0bl9>:0f8?l?c<3:1(l9=:8f0?kg093:07d7k2;29 d1520n87co81;38?l?c93:1(l9=:8f0?kg093807d7k0;29 d1520n87co81;18?l?dn3:1(l9=:8f0?kg093>07d7le;29 d1520n87co81;78?l?dl3:1(l9=:8f0?kg093<07do<9;29 d152h937co81;28?lg4?3:1(l9=:`1;?kg093;07do<6;29 d152h937co81;08?lg4=3:1(l9=:`1;?kg093907do<4;29 d152h937co81;68?lg4;3:1(l9=:`1;?kg093?07do<2;29 d152h937co81;48?lg493:1(l9=:`1;?kg093=07do=f;29 d152h937co81;:8?lg5m3:1(l9=:`1;?kg093307do=d;29 d152h937co81;c8?lg5k3:1(l9=:`1;?kg093h07do=b;29 d152h937co81;a8?lg5i3:1(l9=:`1;?kg093n07do=9;29 d152h937co81;g8?lg503:1(l9=:`1;?kg093l07do=7;29 d152h937co81;33?>of:?0;6)o82;c0<>hf?80:=65fa3694?"f?;0j?55aa63957=<4?:%c46?g402dj;<4>5:9je76=83.j;?4n399me27=9?10el?i:18'e24=i:20bl9>:058?lg6m3:1(l9=:`1;?kg093;376gn1e83>!g0:3k846`n7082=>=ni8i1<7*n738b7==ii>;1=l54i`3a>5<#i>81m>64n`52>4d<3`k:57>5$`51>d5?3gk<=7?l;:kb5=<72-k<>7o<8:lb34<6l21bm<950;&b375;29 d152h937co81;03?>of9=0;6)o82;c0<>hf?809=65fa0194?"f?;0j?55aa63967=:358?lg4l3:1(l9=:`1;?kg0938376gn3b83>!g0:3k846`n7081=>=ni:h1<7*n738b7==ii>;1>l54i`1b>5<#i>81m>64n`52>7d<3`k8<7>5$`51>d5?3gk<=77o<8:lb34<5l21bm3:1(l9=:541?kg093h07d::5;29 d152=<97co81;a8?l22<3:1(l9=:541?kg093n07d::3;29 d152=<97co81;g8?l22:3:1(l9=:541?kg093l07d::1;29 d152=<97co81;33?>o3=90;6)o82;656>hf?80:=65f45g94?"f?;0?:?5aa63957=o6=4+a6090345:9j01g=83.j;?4;639me27=9?10e9:6:18'e24=:058?l2303:1(l9=:541?kg093;376g;4683>!g0:3>=>6`n7082=>=n<=<1<7*n738727=ii>;1=l54i566>5<#i>818;<4n`52>4d<3`>??7>5$`51>1053gk<=7?l;:k707<72-k<>7:92:lb34<6l21b89?50;&b37<3>;1em:?51d98m127290/m:<54708jd1628l07d:o3;l0;6)o82;656>hf?809=65f42f94?"f?;0?:?5aa63967=:358?l21?3:1(l9=:541?kg0938376g;6783>!g0:3>=>6`n7081=>=n;1>l54i547>5<#i>818;<4n`52>7d<3`>>m7>5$`51>1053gk<=77:92:lb34<5l21b89:50;&b37<3>;1em:?52d98m15>290/m:<54708jd162;l07b:87;29 d152===7co81;28?l26:3:1(l9=:532?kg093:07d:>0;29 d152=;:7co81;38?l27n3:1(l9=:532?kg093807d:?e;29 d152=;:7co81;18?l27l3:1(l9=:532?kg093>07d:?c;29 d152=;:7co81;78?l27j3:1(l9=:532?kg093<07d:?a;29 d152=;:7co81;58?l26j3:1(l9=:532?kg093207d:>a;29 d152=;:7co81;;8?l2613:1(l9=:532?kg093k07d:>8;29 d152=;:7co81;`8?l26?3:1(l9=:532?kg093i07d:>6;29 d152=;:7co81;f8?l26=3:1(l9=:532?kg093o07d:>4;29 d152=;:7co81;d8?l26;3:1(l9=:532?kg093;;76g;0883>!g0:3>:=6`n70825>=n;ok1<7*n7380b<=ii>;1<65f3g:94?"f?;08j45aa6395>=n;o=1<7*n7380b<=ii>;1>65f3g794?"f?;08j45aa6397>=n;o>1<7*n7380b<=ii>;1865f3g194?"f?;08j45aa6391>=n;o;1<7*n7380b<=ii>;1:65f3g294?"f?;08j45aa6393>=n<991<7*n7380b<=ii>;1465f41094?"f?;08j45aa639=>=n<9;1<7*n7380b<=ii>;1m65f41294?"f?;08j45aa639f>=n;ol1<7*n7380b<=ii>;1o65f3gg94?"f?;08j45aa639`>=n;on1<7*n7380b<=ii>;1i65f3ga94?"f?;08j45aa639b>=n;oh1<7*n7380b<=ii>;1==54i2ge>5<#i>81?k74n`52>47<3f>997>5$`51>1433gk<=7>4;n617?6=,h=969<;;oc45?7<3f>9>7>5$`51>1433gk<=7<4;n615?6=,h=969<;;oc45?5<3f>9<7>5$`51>1433gk<=7:4;n62b?6=,h=969<;;oc45?3<3f>:i7>5$`51>1433gk<=784;n62`?6=,h=969<;;oc45?1<3f>9i7>5$`51>1433gk<=764;n61`?6=,h=969<;;oc45??<3f>9o7>5$`51>1433gk<=7o4;n61f?6=,h=969<;;oc45?d<3f>9m7>5$`51>1433gk<=7m4;n61=?6=,h=969<;;oc45?b<3f>947>5$`51>1433gk<=7k4;n613?6=,h=969<;;oc45?`<3f>9:7>5$`51>1433gk<=7??;:m75f<72-k<>7:=4:lb34<6921dm=:50;&b37i>ml0;6)o82;c37>hf?80:?65`9df94?"f?;0j<>5aa63951=<;oc45?7132e2il4?:%c46?g7;2dj;<4>7:9l=`?=83.j;?4n029me27=9110c4k7:18'e24=i990bl9>:0;8?j?b?3:1(l9=:`20?kg093;j76a6e783>!g0:3k;?6`n7082f>=h1l>1<7*n738b46=ii>;1=n54o8g0>5<#i>81m==4n`52>4b<3f3n>7>5$`51>d643gk<=7?j;:m:a4<72-k<>7o?3:lb34<6n21d5h>50;&b37i>lm0;6)o82;c37>hf?809?65`9ea94?"f?;0j<>5aa63961=<;oc45?4132ej<44?:%c46?g7;2dj;<4=7:9le5>=83.j;?4n029me27=:110cl>8:18'e24=i990bl9>:3;8?jg7>3:1(l9=:`20?kg0938j76an0483>!g0:3k;?6`n7081f>=h1oh1<7*n738b46=ii>;1>n54o8d3>5<#i>81m==4n`52>7b<3f3n97>5$`51>d643gk<=77o?3:lb34<5n21b=nj50;&b37<6kj1em:?50:9j5fd=83.j;?4>cb9me27=921b=no50;&b37<6kj1em:?52:9j5f?=83.j;?4>cb9me27=;21b=n650;&b37<6kj1em:?54:9j5f1=83.j;?4>cb9me27==21b=n850;&b37<6kj1em:?56:9j5f3=83.j;?4>cb9me27=?21b=n:50;&b37<6kj1em:?58:9j5f5=83.j;?4>cb9me27=121b=n?50;&b37<6kj1em:?5a:9j5f6=83.j;?4>cb9me27=j21b=oh50;&b37<6kj1em:?5c:9j5gc=83.j;?4>cb9me27=l21b=oj50;&b37<6kj1em:?5e:9j5gd=83.j;?4>cb9me27=n21b=oo50;&b37<6kj1em:?51198m4d>290/m:<51ba8jd1628;07d?m7;29 d1528ih7co81;31?>o6j?0;6)o82;3`g>hf?80:?65f1e794?"f?;0:on5aa63951=7:9j5a7=83.j;?4>cb9me27=9110e:0;8?l7dn3:1(l9=:0a`?kg093;j76g>cd83>!g0:3;ho6`n7082f>=n9j81<7*n7382gf=ii>;1=n54i0`6>5<#i>81=nm4n`52>4b<3fk=m7>5$`51>d0>3gk<=7>4;nc55$`51>d0>3gk<=7<4;nc52?6=,h=96l86;oc45?5<3fk=97>5$`51>d0>3gk<=7:4;nc50?6=,h=96l86;oc45?3<3fk=?7>5$`51>d0>3gk<=784;nc56?6=,h=96l86;oc45?1<3fk=<7>5$`51>d0>3gk<=764;nc6b?6=,h=96l86;oc45??<3fk>i7>5$`51>d0>3gk<=7o4;nc6`?6=,h=96l86;oc45?d<3fk>o7>5$`51>d0>3gk<=7m4;nc6f?6=,h=96l86;oc45?b<3fk>m7>5$`51>d0>3gk<=7k4;nc6=?6=,h=96l86;oc45?`<3fk>47>5$`51>d0>3gk<=7??;:mb12<72-k<>7o99:lb34<6921dm8;50;&b3701em:?51398kd33290/m:<5a7;8jd1628907bo:3;29 d152h<27co81;37?>if=;0;6)o82;c5=>hf?80:965`a4394?"f?;0j:45aa63953=9:9le1b=83.j;?4n689me27=9h10cl:l:18'e24=i?30bl9>:0`8?jg3i3:1(l9=:`4:?kg093;h76an4883>!g0:3k=56`n7082`>=hi=21<7*n738b2<=ii>;1=h54o`64>5<#i>81m;74n`52>4`<3fk?:7>5$`51>d0>3gk<=77o99:lb34<5921dm9:50;&b3701em:?52398kd24290/m:<5a7;8jd162;907bo;2;29 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7b?21;27)=jd;7gb>h3810;7c:<0;28 15426=5+a1a9<>hf?<0:7)l>a;:2<>"e9k0jk01/>:=h08o1<75f49594?=h<5aa6394>=h:;:1<7*n738164=ii>;1=65`20d94?"f?;09><5aa6396>=h:8o1<7*n738164=ii>;1?65`20f94?"f?;09><5aa6390>=h:8i1<7*n738164=ii>;1965`20`94?"f?;09><5aa6392>=h:8k1<7*n738164=ii>;1;65`20;94?"f?;09><5aa639<>=h:821<7*n738164=ii>;1565`20494?"f?;09><5aa639e>=h:8?1<7*n738164=ii>;1n65`20694?"f?;09><5aa639g>=h:891<7*n738164=ii>;1h65`20094?"f?;09><5aa639a>=h:8;1<7*n738164=ii>;1j65`20294?"f?;09><5aa63955=;oc45?7532e93:9l67g=83.j;?4=209me27=9=10c?<6:18'e24=:;;0bl9>:078?j4503:1(l9=:302?kg093;=76a=2683>!g0:389=6`n70823>=h:;<1<7*n738164=ii>;1=554o306>5<#i>81>??4n`52>4?<3f8987>5$`51>7463gk<=7?n;:m166<72-k<>7<=1:lb34<6j21d><950;&b37<5:81em:?51b98k76d290/m:<52338jd1628n07d7k4;29 d1520n87co81;28?l?c:3:1(l9=:8f0?kg093;07d7k1;29 d1520n87co81;08?l?c83:1(l9=:8f0?kg093907d7lf;29 d1520n87co81;68?l?dm3:1(l9=:8f0?kg093?07d7ld;29 d1520n87co81;48?lg413:1(l9=:`1;?kg093:07do<7;29 d152h937co81;38?lg4>3:1(l9=:`1;?kg093807do<5;29 d152h937co81;18?lg4<3:1(l9=:`1;?kg093>07do<3;29 d152h937co81;78?lg4:3:1(l9=:`1;?kg093<07do<1;29 d152h937co81;58?lg5n3:1(l9=:`1;?kg093207do=e;29 d152h937co81;;8?lg5l3:1(l9=:`1;?kg093k07do=c;29 d152h937co81;`8?lg5j3:1(l9=:`1;?kg093i07do=a;29 d152h937co81;f8?lg513:1(l9=:`1;?kg093o07do=8;29 d152h937co81;d8?lg5?3:1(l9=:`1;?kg093;;76gn2783>!g0:3k846`n70825>=ni;>1<7*n738b7==ii>;1=?54i`00>5<#i>81m>64n`52>45<3`k9>7>5$`51>d5?3gk<=7?;;:kb64<72-k<>7o<8:lb34<6=21bm?>50;&b37e;29 d152h937co81;3;?>of9m0;6)o82;c0<>hf?80:565fa0a94?"f?;0j?55aa6395d=d:9je41=83.j;?4n399me27=9l10el?9:18'e24=i:20bl9>:0d8?lg6=3:1(l9=:`1;?kg0938;76gn1583>!g0:3k846`n70815>=ni891<7*n738b7==ii>;1>?54i`31>5<#i>81m>64n`52>75<3`k:=7>5$`51>d5?3gk<=7<;;:kb55<72-k<>7o<8:lb34<5=21bm>h50;&b37of;j0;6)o82;c0<>hf?809565fa2`94?"f?;0j?55aa6396d=84?:%c46?g402dj;<4=d:9je4g=83.j;?4n399me27=:l10el>i:18'e24=i:20bl9>:3d8?l4c;3:1(l9=:3f1?kg093:07d07d::d;29 d152=<97co81;78?l22k3:1(l9=:541?kg093<07d::b;29 d152=<97co81;58?l2213:1(l9=:541?kg093207d::8;29 d152=<97co81;;8?l22?3:1(l9=:541?kg093k07d::6;29 d152=<97co81;`8?l22=3:1(l9=:541?kg093i07d::4;29 d152=<97co81;f8?l22;3:1(l9=:541?kg093o07d::2;29 d152=<97co81;d8?l2293:1(l9=:541?kg093;;76g;5183>!g0:3>=>6`n70825>=n<=o1<7*n738727=ii>;1=?54i56g>5<#i>818;<4n`52>45<3`>?o7>5$`51>1053gk<=7?;;:k70g<72-k<>7:92:lb34<6=21b89o50;&b37<3>;1em:?51798m12>290/m:<54708jd1628=07d:;8;29 d152=<97co81;3;?>o3<>0;6)o82;656>hf?80:565f45494?"f?;0?:?5aa6395d=>6=4+a609034d:9j017=83.j;?4;639me27=9l10e9:?:18'e24=:0d8?l24n3:1(l9=:541?kg0938;76g;3d83>!g0:3>=>6`n70815>=n<:n1<7*n738727=ii>;1>?54i51`>5<#i>818;<4n`52>75<3`>8n7>5$`51>1053gk<=7<;;:k77d<72-k<>7:92:lb34<5=21b8;750;&b37<3>;1em:?52798m10?290/m:<54708jd162;=07d:97;29 d152=<97co81;0;?>o3>?0;6)o82;656>hf?809565f47794?"f?;0?:?5aa6396d=:3d8?j20?3:1(l9=:555?kg093:07d:>2;29 d152=;:7co81;28?l2683:1(l9=:532?kg093;07d:?f;29 d152=;:7co81;08?l27m3:1(l9=:532?kg093907d:?d;29 d152=;:7co81;68?l27k3:1(l9=:532?kg093?07d:?b;29 d152=;:7co81;48?l27i3:1(l9=:532?kg093=07d:>b;29 d152=;:7co81;:8?l26i3:1(l9=:532?kg093307d:>9;29 d152=;:7co81;c8?l2603:1(l9=:532?kg093h07d:>7;29 d152=;:7co81;a8?l26>3:1(l9=:532?kg093n07d:>5;29 d152=;:7co81;g8?l26<3:1(l9=:532?kg093l07d:>3;29 d152=;:7co81;33?>o3800;6)o82;625>hf?80:=65f3gc94?"f?;08j45aa6394>=n;o21<7*n7380b<=ii>;1=65f3g594?"f?;08j45aa6396>=n;o?1<7*n7380b<=ii>;1?65f3g694?"f?;08j45aa6390>=n;o91<7*n7380b<=ii>;1965f3g394?"f?;08j45aa6392>=n;o:1<7*n7380b<=ii>;1;65f41194?"f?;08j45aa639<>=n<981<7*n7380b<=ii>;1565f41394?"f?;08j45aa639e>=n<9:1<7*n7380b<=ii>;1n65f3gd94?"f?;08j45aa639g>=n;oo1<7*n7380b<=ii>;1h65f3gf94?"f?;08j45aa639a>=n;oi1<7*n7380b<=ii>;1j65f3g`94?"f?;08j45aa63955=9?7>5$`51>1433gk<=7?4;n616?6=,h=969<;;oc45?4<3f>9=7>5$`51>1433gk<=7=4;n614?6=,h=969<;;oc45?2<3f>:j7>5$`51>1433gk<=7;4;n62a?6=,h=969<;;oc45?0<3f>:h7>5$`51>1433gk<=794;n61a?6=,h=969<;;oc45?><3f>9h7>5$`51>1433gk<=774;n61g?6=,h=969<;;oc45?g<3f>9n7>5$`51>1433gk<=7l4;n61e?6=,h=969<;;oc45?e<3f>957>5$`51>1433gk<=7j4;n619;7>5$`51>1433gk<=7h4;n612?6=,h=969<;;oc45?7732e?=n4?:%c46?25<2dj;<4>1:9le52=83.j;?4n029me27=821dm=<50;&b3750;&b3721d5km50;&b37=83.j;?4n029me27=i21d5k950;&b37:18'e24=i990bl9>:038?j?bn3:1(l9=:`20?kg093;976a6ed83>!g0:3k;?6`n70827>=h1ln1<7*n738b46=ii>;1=954o8g`>5<#i>81m==4n`52>43<3f3nn7>5$`51>d643gk<=7?9;:m:ad<72-k<>7o?3:lb34<6?21d5h750;&b37i>m?0;6)o82;c37>hf?80:n65`9d694?"f?;0j<>5aa6395f=<;oc45?7b32e2i<4?:%c46?g7;2dj;<4>f:9l=`6=83.j;?4n029me27=:910c4ji:18'e24=i990bl9>:338?j?cm3:1(l9=:`20?kg0938976a6de83>!g0:3k;?6`n70817>=h1mi1<7*n738b46=ii>;1>954o8fa>5<#i>81m==4n`52>73<3fk;m7>5$`51>d643gk<=7<9;:mb4<<72-k<>7o?3:lb34<5?21dm=650;&b37if8<0;6)o82;c37>hf?809n65`9g`94?"f?;0j<>5aa6396f=<;oc45?4b32e2hl4?:%c46?g7;2dj;<4=f:9j5fb=83.j;?4>cb9me27=821b=nl50;&b37<6kj1em:?51:9j5fg=83.j;?4>cb9me27=:21b=n750;&b37<6kj1em:?53:9j5f>=83.j;?4>cb9me27=<21b=n950;&b37<6kj1em:?55:9j5f0=83.j;?4>cb9me27=>21b=n;50;&b37<6kj1em:?57:9j5f2=83.j;?4>cb9me27=021b=n=50;&b37<6kj1em:?59:9j5f7=83.j;?4>cb9me27=i21b=n>50;&b37<6kj1em:?5b:9j5g`=83.j;?4>cb9me27=k21b=ok50;&b37<6kj1em:?5d:9j5gb=83.j;?4>cb9me27=m21b=ol50;&b37<6kj1em:?5f:9j5gg=83.j;?4>cb9me27=9910e:038?l7e?3:1(l9=:0a`?kg093;976g>b783>!g0:3;ho6`n70827>=n9m?1<7*n7382gf=ii>;1=954i0f7>5<#i>81=nm4n`52>43<3`;o?7>5$`51>4ed3gk<=7?9;:k2`7<72-k<>7?lc:lb34<6?21b=i?50;&b37<6kj1em:?51998m4b7290/m:<51ba8jd1628307d?lf;29 d1528ih7co81;3b?>o6kl0;6)o82;3`g>hf?80:n65f1b094?"f?;0:on5aa6395f=6=4+a6095fe5$`51>d0>3gk<=7?4;nc53?6=,h=96l86;oc45?4<3fk=:7>5$`51>d0>3gk<=7=4;nc51?6=,h=96l86;oc45?2<3fk=87>5$`51>d0>3gk<=7;4;nc57?6=,h=96l86;oc45?0<3fk=>7>5$`51>d0>3gk<=794;nc54?6=,h=96l86;oc45?><3fk>j7>5$`51>d0>3gk<=774;nc6a?6=,h=96l86;oc45?g<3fk>h7>5$`51>d0>3gk<=7l4;nc6g?6=,h=96l86;oc45?e<3fk>n7>5$`51>d0>3gk<=7j4;nc6e?6=,h=96l86;oc45?c<3fk>57>5$`51>d0>3gk<=7h4;nc61:9le03=83.j;?4n689me27=9;10cl;;:18'e24=i?30bl9>:018?jg2;3:1(l9=:`4:?kg093;?76an5383>!g0:3k=56`n70821>=hi<;1<7*n738b2<=ii>;1=;54o`73>5<#i>81m;74n`52>41<3fk?j7>5$`51>d0>3gk<=7?7;:mb0`<72-k<>7o99:lb34<6121dm9j50;&b3701em:?51`98kd2d290/m:<5a7;8jd1628h07bo;a;29 d152h<27co81;3`?>if<00;6)o82;c5=>hf?80:h65`a5:94?"f?;0j:45aa6395`=<6=4+a609e3?:318?jg3:3:1(l9=:`4:?kg0938?76an4083>!g0:3k=56`n70811>=hi>:1<7*n738b2<=ii>;1>;54o`4e>5<#i>81m;74n`52>71<3fk=i7>5$`51>d0>3gk<=7<7;:mb2a<72-k<>7o99:lb34<5121dm;m50;&b3701em:?52`98kd0e290/m:<5a7;8jd162;h07bo91;29 d152h<27co81;0`?>if=?0;6)o82;c5=>hf?809h65`a5`94?"f?;0j:45aa6396`=;6=4+a609e3?=;oc45?6<3`8;=7>5$`51>7653gk<=7?4;h034?6=,h=96?>=;oc45?4<3`;mj7>5$`51>7653gk<=7=4;h3ea?6=,h=96?>=;oc45?2<3`;mh7>5$`51>7653gk<=7;4;h3eg?6=,h=96?>=;oc45?0<3`;mn7>5$`51>7653gk<=794;h3ee?6=,h=96?>=;oc45?><3`;m57>5$`51>7653gk<=774;h3e3?6=,h=96?>=;oc45?g<3`;m:7>5$`51>7653gk<=7l4;h3e1?6=,h=96?>=;oc45?e<3`;m87>5$`51>7653gk<=7j4;h3e7?6=,h=96?>=;oc45?c<3`;m>7>5$`51>7653gk<=7h4;h3e5?6=,h=96?>=;oc45?7732c:j=4?:%c46?47:2dj;<4>1:9j5``=83.j;?4=039me27=9;10e:018?l47j3:1(l9=:321?kg093;?76g=0`83>!g0:38;>6`n70821>=n:931<7*n738147=ii>;1=;54i32;>5<#i>81>=<4n`52>41<3`8;;7>5$`51>7653gk<=7?7;:k143<72-k<>7=;50;&b37<58;1em:?51`98m763290/m:<52108jd1628h07d?i8;29 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d152=li7co81;3`?>o3n00;6)o82;6ef>hf?80:h65f4dg94?"f?;0?jo5aa6395`=5$`51>0b03gk<=7?4;h7g1?6=,h=968j8;oc45?4<3`?o?7>5$`51>0b03gk<=7=4;h7ga?6=,h=968jk;oc45?6<3`?oo7>5$`51>0bc3gk<=7?4;h7gf?6=,h=968jk;oc45?4<3`?o57>5$`51>0bc3gk<=7=4;n7e`?6=,h=968hl;oc45?6<3f?mn7>5$`51>0`d3gk<=7?4;n7e=?6=,h=968hl;oc45?4<3f?m47>5$`51>0`d3gk<=7=4;n7e3?6=,h=968hl;oc45?2<3f?m:7>5$`51>0`d3gk<=7;4;n7e1?6=,h=968hl;oc45?0<3f?m87>5$`51>0`d3gk<=794;n7e7?6=,h=968hl;oc45?><3f?m>7>5$`51>0`d3gk<=774;n7e5?6=,h=968hl;oc45?g<3f?m<7>5$`51>0`d3gk<=7l4;n7fa?6=,h=968hl;oc45?e<3f?nh7>5$`51>0`d3gk<=7j4;n7fg?6=,h=968hl;oc45?c<3f?nn7>5$`51>0`d3gk<=7h4;n7fe?6=,h=968hl;oc45?7732e>i54?:%c46?3ak2dj;<4>1:9l1`1=83.j;?4:fb9me27=9;10c8k9:18'e24==oi0bl9>:018?j3b=3:1(l9=:4d`?kg093;?76a:e583>!g0:3?mo6`n70821>=h>9>1<7*n7386bf=ii>;1=;54o720>5<#i>819km4n`52>41<3f<;>7>5$`51>0`d3gk<=7?7;:m544<72-k<>7;ic:lb34<6121d:=>50;&b37<2nj1em:?51`98k0`a290/m:<55ga8jd1628h07b;ie;29 d152i2nh0;6)o82;7eg>hf?80:h65`5dd94?"f?;0>jn5aa6395`=5$`51>3453gk<=7?4;n42b?6=,h=96;<=;oc45?4<3f<:i7>5$`51>3453gk<=7=4;n42`?6=,h=96;<=;oc45?2<3f<:o7>5$`51>3453gk<=7;4;n42f?6=,h=96;<=;oc45?0<3f<:m7>5$`51>3453gk<=794;n42=?6=,h=96;<=;oc45?><3f<:47>5$`51>3453gk<=774;n423?6=,h=96;<=;oc45?g<3f<::7>5$`51>3453gk<=7l4;n420?6=,h=96;<=;oc45?e<3f<:?7>5$`51>3453gk<=7j4;n426?6=,h=96;<=;oc45?c<3f<:=7>5$`51>3453gk<=7h4;n424?6=,h=96;<=;oc45?7732e=1:9l25b=83.j;?49239me27=9;10c;>l:18'e24=>;80bl9>:018?j07j3:1(l9=:701?kg093;?76a90`83>!g0:3<9>6`n70821>=h>;k1<7*n738567=ii>;1=;54o70:>5<#i>81:?<4n`52>41<3f<947>5$`51>3453gk<=7?7;:m562<72-k<>78=2:lb34<6121d:?850;&b37<1:;1em:?51`98k342290/m:<56308jd1628h07b8=4;29 d152?897co81;3`?>i1:90;6)o82;416>hf?80:h65`60794?"f?;0=>?5aa6395`=5$`51>3513gk<=7?4;n400?6=,h=96;=9;oc45?4<3f<8>7>5$`51>3513gk<=7=4;n40`?6=,h=96;=l;oc45?6<3f<8n7>5$`51>35d3gk<=7?4;n40e?6=,h=96;=l;oc45?4<3f<847>5$`51>35d3gk<=7=4;n52`?6=,h=96:?l;oc45?6<3f=:n7>5$`51>27d3gk<=7?4;n52e?6=,h=96:?l;oc45?4<3f=:57>5$`51>27d3gk<=7=4;n525$`51>27d3gk<=7;4;n522?6=,h=96:?l;oc45?0<3f=:97>5$`51>27d3gk<=794;ncaa?6=,h=96llk;oc45?6<@k8876anbb83>!g0:3kih6`n7082?Md5;21dmol50;&b375Gb318?jgdj3:1(l9=:``g?kg093>07bol9;29 d152hho7co81;78?jgd03:1(l9=:``g?kg093<07bol7;29 d152hho7co81;58?jgd>3:1(l9=:``g?kg093207bol5;29 d152hho7co81;;8?jgd<3:1(l9=:``g?kg093k07bol3;29 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d152=n=7co81;33?>o3k;0;6)o82;6g2>hf?80:=65f4b394?"f?;0?h;5aa63957=2dj;<4>5:9j0ac=83.j;?4;d79me27=9?10e9jk:18'e24=:058?l2ck3:1(l9=:5f5?kg093;376g;dc83>!g0:3>o:6`n7082=>=n;1=l54i5f:>5<#i>818i84n`52>4d<3`>o47>5$`51>1b13gk<=7?l;:k7`1<72-k<>7:k6:lb34<6l21b8n750;&b37<3l?1em:?51d98m1dc290/m:<54e48jd1628l07d:ic;29 d152=li7co81;28?l2ai3:1(l9=:5da?kg093;07d:i8;29 d152=li7co81;08?l2a?3:1(l9=:5da?kg093907d:i6;29 d152=li7co81;68?l2a=3:1(l9=:5da?kg093?07d:i4;29 d152=li7co81;48?l2a;3:1(l9=:5da?kg093=07d:i2;29 d152=li7co81;:8?l2a93:1(l9=:5da?kg093307d:i0;29 d152=li7co81;c8?l2bn3:1(l9=:5da?kg093h07d:jd;29 d152=li7co81;a8?l2bk3:1(l9=:5da?kg093n07d:jb;29 d152=li7co81;g8?l2bi3:1(l9=:5da?kg093l07d:j9;29 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d152=n=7co81;37?>o3jl0;6)o82;6g2>hf?80:965f4eg94?"f?;0?h;5aa63953=2dj;<4>9:9j0ag=83.j;?4;d79me27=9h10e9j6:18'e24=:0`8?l2c03:1(l9=:5f5?kg093;h76g;d583>!g0:3>o:6`n7082`>=n;1=h54i5`g>5<#i>818i84n`52>4`<3`>mo7>5$`51>1`e3gk<=7>4;h6ee?6=,h=969hm;oc45?7<3`>m47>5$`51>1`e3gk<=7<4;h6e3?6=,h=969hm;oc45?5<3`>m:7>5$`51>1`e3gk<=7:4;h6e1?6=,h=969hm;oc45?3<3`>m87>5$`51>1`e3gk<=784;h6e7?6=,h=969hm;oc45?1<3`>m>7>5$`51>1`e3gk<=764;h6e5?6=,h=969hm;oc45??<3`>m<7>5$`51>1`e3gk<=7o4;h6fb?6=,h=969hm;oc45?d<3`>nh7>5$`51>1`e3gk<=7m4;h6fg?6=,h=969hm;oc45?b<3`>nn7>5$`51>1`e3gk<=7k4;h6fe?6=,h=969hm;oc45?`<3`>n57>5$`51>1`e3gk<=7??;:k7a2<72-k<>7:ib:lb34<6921b8h850;&b37<3nk1em:?51398m1c2290/m:<54g`8jd1628907d:j4;29 d152=li7co81;37?>o3m:0;6)o82;6ef>hf?80:965f51194?"f?;0?jo5aa63953=<=4?:%c46?2aj2dj;<4>9:9j0c`=83.j;?4;fc9me27=9h10e9hj:18'e24=:0`8?l2al3:1(l9=:5da?kg093;h76g;f883>!g0:3>mn6`n7082`>=n;1=h54i5g1>5<#i>818kl4n`52>4`<3`?o47>5$`51>0b03gk<=7>4;h7g2?6=,h=968j8;oc45?7<3`?o97>5$`51>0b03gk<=7<4;h7g7?6=,h=968j8;oc45?5<3`?oi7>5$`51>0bc3gk<=7>4;h7gg?6=,h=968jk;oc45?7<3`?on7>5$`51>0bc3gk<=7<4;h7g=?6=,h=968jk;oc45?5<3f?mh7>5$`51>0`d3gk<=7>4;n7ef?6=,h=968hl;oc45?7<3f?m57>5$`51>0`d3gk<=7<4;n7e5$`51>0`d3gk<=7:4;n7e2?6=,h=968hl;oc45?3<3f?m97>5$`51>0`d3gk<=784;n7e0?6=,h=968hl;oc45?1<3f?m?7>5$`51>0`d3gk<=764;n7e6?6=,h=968hl;oc45??<3f?m=7>5$`51>0`d3gk<=7o4;n7e4?6=,h=968hl;oc45?d<3f?ni7>5$`51>0`d3gk<=7m4;n7f`?6=,h=968hl;oc45?b<3f?no7>5$`51>0`d3gk<=7k4;n7ff?6=,h=968hl;oc45?`<3f?nm7>5$`51>0`d3gk<=7??;:m6a=<72-k<>7;ic:lb34<6921d9h950;&b37<2nj1em:?51398k0c1290/m:<55ga8jd1628907b;j5;29 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; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3849 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_4067 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4196 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0_4210 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_4214 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_40_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_39_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_4380 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_4396 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_4612 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_4616 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_4620 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_4624 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_4628 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4_4812 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3_4815 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2_4818 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1_4821 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi_4824 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_4825 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<23> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<24> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<25> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<26> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<27> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<28> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5023 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_5026 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5027 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_5028 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_5029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5030 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5134 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5135 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5144 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5145 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5146 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4_5219 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3_5222 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2_5225 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1_5228 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi_5231 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_5232 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5233 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5234 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5235 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5236 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5237 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5238 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5239 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5240 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5241 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5242 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5243 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5244 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5245 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5247 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5248 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5249 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5250 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5251 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5252 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5253 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5254 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5255 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5256 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5257 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5258 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5259 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<25> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<26> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<27> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<28> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5446 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_5447 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5448 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_5449 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_5450 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5451 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5475 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5547 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5548 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5557 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5558 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5561 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5562 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5726 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5727 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5728 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5729 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5819 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5837 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5975 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5976 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5977 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5978 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6086 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6104 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6242 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6243 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6244 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6245 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6335 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6353 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6488 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6489 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6490 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6491 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6599 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6617 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_6647 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6678 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6679 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_6788 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6789 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6790 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ; - wire N2; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6794 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6796 ; - wire N4; - wire N6; - wire N10; - wire N12; - wire N14; - wire N20; - wire N22; - wire N24; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6806 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6808 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6809 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6811 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6812 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6813 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6814 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6816 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6818 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6820 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6821 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6823 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6824 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6825 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6826 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6828 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ; - wire N26; - wire N28; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6834 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6835 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6836 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6837 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6838 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6839 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6840 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6841 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6842 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6843 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6844 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6845 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6846 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6848 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6849 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6852 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6853 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6854 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6862 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6863 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6864 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6865 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6866 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6867 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6868 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6869 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6870 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6871 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6872 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6873 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6874 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6875 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6876 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6877 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6878 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6879 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6880 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6881 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6882 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6883 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6884 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6885 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6886 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6887 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6889 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6890 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6891 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6892 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6893 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6894 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6895 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6896 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6897 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6898 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6899 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6900 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6901 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6902 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6903 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6904 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6905 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6906 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6907 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6908 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6909 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6910 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6911 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6912 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6913 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6914 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6915 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6916 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6917 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6918 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6919 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6920 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6921 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6922 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6923 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6924 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6925 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6926 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6927 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6928 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6929 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6930 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6931 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6932 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6933 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6934 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6935 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6936 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6937 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6938 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6939 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6940 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6941 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6942 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6943 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6944 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6945 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6946 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6947 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6948 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6949 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6950 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6951 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6952 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6953 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6954 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6955 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6956 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6957 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6958 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6959 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6960 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6961 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6962 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6963 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6964 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6965 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6966 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6967 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6968 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6969 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6970 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6971 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6972 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6973 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6974 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6975 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6976 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6977 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6978 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6979 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6980 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6981 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6982 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6983 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6984 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6985 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6986 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6987 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6988 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6989 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6990 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6991 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6992 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6993 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6994 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6995 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6996 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6997 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_6998 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_6999 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7000 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7001 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7002 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7003 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7004 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7005 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7006 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7007 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7008 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7009 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7011 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7012 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7013 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7014 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7015 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7016 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7017 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7018 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7019 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7020 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7021 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7022 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7023 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7024 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7025 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7026 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7027 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7028 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7030 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7031 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7032 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7033 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7034 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7035 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7036 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7037 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7038 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7039 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7040 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7042 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7043 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7044 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7045 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7046 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7047 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7048 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7049 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7050 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7051 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7052 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7053 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7054 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7055 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7056 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7057 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7058 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7059 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7060 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7061 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7062 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7063 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7064 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7065 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7066 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7067 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7068 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7069 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7070 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7071 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7072 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7073 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7074 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7075 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7076 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7077 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7078 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7079 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7080 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7081 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7082 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7083 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7084 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7085 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7086 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7087 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7089 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7090 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7091 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7092 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7093 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7094 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7095 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7096 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7097 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7098 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7099 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7100 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7101 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7102 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7103 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt_7104 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7105 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt_7106 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7107 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7108 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7109 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7110 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7111 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_7112 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_7113 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_7114 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_7115 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7116 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7117 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_7119 ; - wire N31; - wire N33; - wire N34; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_7123 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_7125 ; - wire N38; - wire N40; - wire N42; - wire N44; - wire N46; - wire N48; - wire N50; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7133 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7134 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7135 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7137 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7138 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_7139 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_7140 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7141 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7142 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_7143 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_7144 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7145 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7146 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7148 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7149 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7150 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_7151 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_7152 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7153 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7154 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_7155 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7156 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7157 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7158 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7159 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_7160 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_7161 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_7162 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_7163 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_7164 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_7165 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_7166 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_7167 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_7168 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_7169 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_7170 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_7171 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_7172 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_7173 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_989 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_988 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_987 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_986 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_985 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_984 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_982 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_972 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_971 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_960 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_915 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_914 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_912 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_904 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_900 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1320 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1317 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_1279 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_1274 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_1268 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_1263 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_1257 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_1252 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_1246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_1241 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1235 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1230 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1224 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1219 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1213 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1208 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1202 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1197 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1191 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1186 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1180 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1175 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1169 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1164 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1158 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1153 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1142 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1136 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1131 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1125 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1120 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1114 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1109 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1087 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1082 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1077 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1075 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1070 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1718 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1715 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1677 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1672 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1666 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1661 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1655 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1650 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1644 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1639 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1633 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1628 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1622 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1617 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1611 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1606 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1600 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1595 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1589 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1584 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1578 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1573 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1567 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1562 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1556 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1551 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1545 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1540 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1534 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1529 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1523 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1518 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1512 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1507 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1492 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1491 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1486 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1481 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1479 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2066 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N01 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2052 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2051 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_2007 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_2006 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2005 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_1902 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1901 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1899 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_1892 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_1881 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_2181 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_2179 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2178 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2177 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2176 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2174 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_2173 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_2172 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_2170 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_2169 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2161 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2160 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2153 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_2131 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_2130 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2129 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2107 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2106 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2104 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2097 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2073 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N3 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N2 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2427 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2426 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2425 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2424 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2423 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2421 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2420 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2396 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2283 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2282 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2280 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2272 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2268 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N3 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N2 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2677 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2676 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2675 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2674 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2673 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2671 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2670 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2646 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2533 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2532 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2530 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2522 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2518 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_3207 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N01 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3193 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3192 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_3182 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_3148 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_3147 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3146 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2993 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2992 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2990 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2983 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2972 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire [72 : 72] \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 ; - wire [0 : 0] \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL ; - wire [0 : 0] NlwRenamedSig_OI_m_axis_tstrb; - wire [65 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i ; - wire [44 : 13] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i ; - wire [28 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [16 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [16 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i ; - wire [6 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload ; - wire [8 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly ; - wire [98 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg ; - wire [27 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload ; - wire [2 : 2] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr ; - wire [7 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i ; - wire [2 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg ; - wire [63 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [97 : 97] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i ; - wire [24 : 15] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly ; - wire [9 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [27 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [24 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly ; - wire [0 : 0] NlwRenamedSig_OI_m_axi_aruser; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [12 : 10] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r ; - wire [64 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [9 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [5 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [5 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [9 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - assign - m_axi_awsize[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awsize[1] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awsize[0] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awburst[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awburst[0] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awlock[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awuser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_wstrb[7] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[6] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[5] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[4] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[3] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[2] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wuser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arsize[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arsize[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arsize[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arburst[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arburst[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arlock[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_aruser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axis_tdata[63] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] , - m_axis_tdata[62] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] , - m_axis_tdata[61] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] , - m_axis_tdata[60] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] , - m_axis_tdata[59] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] , - m_axis_tdata[58] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] , - m_axis_tdata[57] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] , - m_axis_tdata[56] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] , - m_axis_tdata[55] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] , - m_axis_tdata[54] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] , - m_axis_tdata[53] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] , - m_axis_tdata[52] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] , - m_axis_tdata[51] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] , - m_axis_tdata[50] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] , - m_axis_tdata[49] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] , - m_axis_tdata[48] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] , - m_axis_tdata[47] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] , - m_axis_tdata[46] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] , - m_axis_tdata[45] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] , - m_axis_tdata[44] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] , - m_axis_tdata[43] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] , - m_axis_tdata[42] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] , - m_axis_tdata[41] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] , - m_axis_tdata[40] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] , - m_axis_tdata[39] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] , - m_axis_tdata[38] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] , - m_axis_tdata[37] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] , - m_axis_tdata[36] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] , - m_axis_tdata[35] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] , - m_axis_tdata[34] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] , - m_axis_tdata[33] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] , - m_axis_tdata[32] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] , - m_axis_tdata[31] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] , - m_axis_tdata[30] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] , - m_axis_tdata[29] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] , - m_axis_tdata[28] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] , - m_axis_tdata[27] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] , - m_axis_tdata[26] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] , - m_axis_tdata[25] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] , - m_axis_tdata[24] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] , - m_axis_tdata[23] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] , - m_axis_tdata[22] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] , - m_axis_tdata[21] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] , - m_axis_tdata[20] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] , - m_axis_tdata[19] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] , - m_axis_tdata[18] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] , - m_axis_tdata[17] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] , - m_axis_tdata[16] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] , - m_axis_tdata[15] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] , - m_axis_tdata[14] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] , - m_axis_tdata[13] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] , - m_axis_tdata[12] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] , - m_axis_tdata[11] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] , - m_axis_tdata[10] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] , - m_axis_tdata[9] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] , - m_axis_tdata[8] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] , - m_axis_tdata[7] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] , - m_axis_tdata[6] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] , - m_axis_tdata[5] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] , - m_axis_tdata[4] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] , - m_axis_tdata[3] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] , - m_axis_tdata[2] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] , - m_axis_tdata[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] , - m_axis_tdata[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] , - m_axis_tstrb[7] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[6] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[5] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[4] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[3] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[2] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tkeep[7] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] , - m_axis_tkeep[6] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] , - m_axis_tkeep[5] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] , - m_axis_tkeep[4] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] , - m_axis_tkeep[3] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] , - m_axis_tkeep[2] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] , - m_axis_tkeep[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] , - m_axis_tkeep[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] , - m_axis_tid[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] , - m_axis_tdest[0] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72], - vfifo_s2mm_channel_full[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [1], - vfifo_s2mm_channel_full[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [0], - vfifo_mm2s_channel_empty[1] = -\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q , - vfifo_mm2s_channel_empty[0] = -\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q , - vfifo_idle[1] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q , - vfifo_idle[0] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q , - m_axi_rready = NlwRenamedSig_OI_m_axi_rready, - m_axis_tvalid = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i , - m_axis_tlast = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] , - vfifo_mm2s_rresp_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR , - vfifo_s2mm_bresp_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR , - vfifo_s2mm_overrun_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ; - VCC XST_VCC ( - .P(NlwRenamedSig_OI_m_axis_tstrb[0]) - ); - GND XST_GND ( - .G(NlwRenamedSig_OI_m_axi_aruser[0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3848 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4196 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3848 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3849 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3849 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3850 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3850 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3851 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3851 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_39_o ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_40_o ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ) - ); - FD #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tid[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_73 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tlast), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdest[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6882 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6882 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6883 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6883 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6884 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6884 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6885 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6885 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6886 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6886 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6887 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6887 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6888 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6888 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6889 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6889 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6890 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6890 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6891 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6891 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6892 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6892 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6893 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6893 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6894 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6894 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6895 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6895 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6896 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6896 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6897 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6897 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6898 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6898 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6899 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6899 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6900 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6900 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6901 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6901 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_4380 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6902 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6902 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_4380 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6903 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6903 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6904 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6904 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6905 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6905 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6906 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6906 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6907 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6907 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6908 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6908 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6909 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6909 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6910 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6910 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6911 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6911 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6912 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6912 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6913 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6913 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6914 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6914 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6915 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6915 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_4396 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<15> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6916 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6916 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_4396 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6917 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6917 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6918 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6918 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6919 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6919 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6920 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6920 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6921 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6921 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6922 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6922 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6923 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6923 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6925 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6925 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6926 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6926 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6927 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6927 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6928 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6928 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6929 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6929 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [12]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [1], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_4612 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_4616 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_4620 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_4624 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_4628 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_76 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[0] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_66 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<3> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [1]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [3]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [1]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [0]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]) - ); - FDSE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]) - ); - FDRE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg_1 ( - .C(aclk), - .D(vfifo_mm2s_channel_full[1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg_0 ( - .C(aclk), - .D(vfifo_mm2s_channel_full[0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [0]) - ); - FD #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[8].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[9].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[10].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[11].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[12].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[13].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[14].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]) - ); - LUT5 #( - .INIT ( 32'h00000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4_4812 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [4]) - ); - LUT5 #( - .INIT ( 32'h10000010 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [4]) - ); - LUT5 #( - .INIT ( 32'h00101011 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4_4812 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3_4815 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [3]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [3]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3_4815 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2_4818 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [2]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [2]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2_4818 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1_4821 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [1]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [1]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1_4821 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi_4824 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [0]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [0]) - ); - LUT4 #( - .INIT ( 16'h7FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi_4824 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_4825 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt_7104 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<28> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6930 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<27> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6930 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_4825 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6931 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<26> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6931 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6932 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<25> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6932 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6933 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<24> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6933 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6934 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<23> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6934 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6935 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6935 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6938 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6938 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6939 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6939 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6940 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6940 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6941 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6941 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6942 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6942 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6943 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6943 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6944 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6944 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6945 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6945 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6946 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6946 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6947 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6947 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6948 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6948 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6949 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6949 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6950 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6950 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6951 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6951 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6952 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6952 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6953 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6953 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6954 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6954 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6955 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6955 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6956 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6956 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7105 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [31]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6957 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [30]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6957 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6958 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [29]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6958 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6959 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6959 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6960 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6960 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6961 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6961 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6962 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6962 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6963 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6963 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6964 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6964 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6965 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6965 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6966 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6966 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6967 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6967 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6968 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6968 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6969 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6969 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6970 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6970 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6971 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6971 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6972 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6972 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6973 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6973 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6974 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6974 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6975 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6975 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6976 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6976 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6977 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6977 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6978 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6978 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6979 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6979 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6980 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6980 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6981 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6981 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6982 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6982 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6983 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6983 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6984 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6984 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6985 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6985 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6986 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6986 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_5029 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5023 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_5028 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_5029 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5027 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_5028 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_5026 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5027 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_5026 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5030 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5145 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5135 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5144 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5134 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5147 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5145 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5146 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5144 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5146 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5147 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_98 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [98]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_97 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i [97]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [97]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_96 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [96]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_95 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [95]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_94 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [94]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_93 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [93]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_92 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [92]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_91 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [91]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_90 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [90]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_89 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [89]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_88 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [88]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_87 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [87]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_86 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [86]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_85 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [85]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_84 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [84]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_83 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [83]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_82 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [82]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_81 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [81]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_80 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [80]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_79 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [79]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_78 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [78]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_77 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [77]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_76 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [76]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [75]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [74]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_73 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [73]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [72]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [71]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [70]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [69]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [68]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [67]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_66 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [66]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [65]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[8].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[9].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[10].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[11].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[12].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[13].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[14].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [15]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms_O_UNCONNECTED ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [4]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [3]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [2]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [1]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [2]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [1]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [0]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]) - ); - LUT5 #( - .INIT ( 32'h00000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4_5219 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [4]) - ); - LUT5 #( - .INIT ( 32'h10000010 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [4]) - ); - LUT5 #( - .INIT ( 32'h00101011 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4_5219 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3_5222 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [3]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [3]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3_5222 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2_5225 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [2]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [2]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2_5225 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1_5228 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [1]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [1]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1_5228 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi_5231 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [0]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [0]) - ); - LUT4 #( - .INIT ( 16'h7FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi_5231 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_5232 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt_7106 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<28> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5233 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6987 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<27> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5233 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6987 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_5232 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5234 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6988 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<26> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5234 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6988 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5233 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5235 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6989 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<25> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5235 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6989 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5234 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5236 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6990 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5236 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6990 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5235 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5237 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6991 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5237 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6991 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5236 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5238 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6992 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5238 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6992 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5237 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5239 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6993 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5239 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6993 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5238 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5240 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6994 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5240 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6994 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5239 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5241 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6995 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5241 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6995 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5240 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5242 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6996 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5242 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6996 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5241 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5243 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6997 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5243 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6997 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5242 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5244 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_6998 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5244 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_6998 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5243 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5245 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_6999 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5245 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_6999 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5244 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5246 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7000 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5246 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7000 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5245 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5247 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7001 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5247 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7001 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5246 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5248 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7002 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5248 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7002 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5247 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5249 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7003 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5249 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7003 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5248 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5250 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7004 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5250 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7004 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5249 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5251 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7005 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5251 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7005 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5250 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5252 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7006 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5252 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7006 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5251 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5253 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7007 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5253 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7007 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5252 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5254 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7008 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5254 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7008 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5253 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5255 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7009 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5255 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7009 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5254 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5256 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7010 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5256 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7010 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5255 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5257 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7011 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5257 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7011 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5256 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5258 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7012 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5258 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7012 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5257 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5259 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7013 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5259 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7013 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5258 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5259 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7107 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [31]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7014 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [30]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7014 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7015 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [29]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7015 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7016 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7016 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7017 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7017 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7018 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7018 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7019 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7019 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7020 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7020 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7021 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7021 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7022 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7022 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7023 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7023 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7024 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7024 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7025 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7025 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7026 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7026 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7027 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7027 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7028 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7028 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7029 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7029 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7030 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7030 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7031 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7031 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7032 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7032 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7033 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7033 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7034 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7034 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7035 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7035 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7036 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7036 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7037 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7037 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7038 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7038 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7039 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7039 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7040 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7040 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7041 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7041 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7043 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7043 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [29], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [13], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [7], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [9], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [11], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [1], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [3], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [5], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5451 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_5450 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5446 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_5449 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_5450 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5448 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_5449 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_5447 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5448 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_5447 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_24 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_23 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_22 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_21 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_20 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_19 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_18 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_17 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_16 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_31 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [31]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_30 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [30]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_29 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [29]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_28 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [28]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_27 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_26 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_25 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_24 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_23 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_22 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_21 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_20 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_19 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_18 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_17 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_16 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5475 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5558 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5548 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5557 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5547 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5562 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5558 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5561 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5557 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5561 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5562 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7044 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7044 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7108 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7045 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7045 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7046 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7046 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7047 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7047 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7048 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7048 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7049 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7049 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7050 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7050 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7051 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7051 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7052 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7052 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7053 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7053 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7054 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7054 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7055 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7055 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7056 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7056 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7057 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7057 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7058 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7058 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7137 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7134 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5726 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5727 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5727 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5729 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5726 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5728 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5729 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5728 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5837 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_4067 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7059 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7059 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7109 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7060 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7060 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7061 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7061 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7062 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7062 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7063 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7063 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7064 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7064 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7065 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7065 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7066 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7066 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7067 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7067 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7068 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7068 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7069 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7069 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7070 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7070 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7071 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7071 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7072 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7072 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7073 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7073 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7135 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5975 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5976 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5976 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5978 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5975 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5977 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5978 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5977 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6104 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7074 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7074 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7110 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7075 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7075 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7076 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7076 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7077 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7077 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7078 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7078 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7079 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7079 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7080 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7080 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7081 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7081 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7082 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7082 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7083 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7083 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7084 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7084 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7085 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7085 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7086 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7086 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7087 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7087 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7138 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7133 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6242 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6243 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6243 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6245 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6242 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6244 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6245 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6244 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6353 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7089 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7089 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7111 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7090 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7090 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7091 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7091 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7092 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7092 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7093 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7093 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7094 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7094 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7095 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7095 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7096 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7096 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7097 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7097 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7098 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7098 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7099 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7099 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7100 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7100 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7101 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7101 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7102 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7102 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7103 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7103 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6488 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6489 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6489 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6491 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6488 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6490 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6491 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6490 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6617 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [64]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [5]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [4]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [98]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_4067 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [96]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [31]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [95]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [30]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [94]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [29]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [93]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [28]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [92]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [27]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [91]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [26]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [90]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [25]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [89]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [24]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [88]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [23]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [87]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [22]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [86]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [21]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [85]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [20]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [84]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [19]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [83]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [18]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [82]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [17]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [81]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [16]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [80]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [15]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [79]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [14]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [78]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [13]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [77]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [12]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [76]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [11]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [75]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [10]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [74]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [9]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [73]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [72]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [71]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [70]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [69]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [68]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [67]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [66]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [65]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .Q(\NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [65]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6789 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_6788 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6790 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6789 ) - ); - FDP #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ) - ); - FDP \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/inverted_reset ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6790 ) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full<0><0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [0]) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full<1><1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [1]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ) - ); - LUT3 #( - .INIT ( 8'h80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb1 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I2(m_axis_tready), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_mcdf_tvalid1 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(m_axis_tready), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [3]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [2]) - ); - LUT5 #( - .INIT ( 32'h3222F222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_start_of_pkt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [1]) - ); - LUT4 #( - .INIT ( 16'h8F88 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ) - ); - LUT3 #( - .INIT ( 8'h10 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ) - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(s_axis_tvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ) - ); - LUT3 #( - .INIT ( 8'h51 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/s_ready_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(s_axis_tready) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ) - ); - LUT6 #( - .INIT ( 64'h0000020000020202 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/valid_to_mtf_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hCFAAC0AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [24]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [10]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [12]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn210 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [11]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [13]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [14]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [15]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [16]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [17]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [19]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [18]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [20]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [21]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [22]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [23]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [26]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [25]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [27]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [28]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [29]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [30]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [31]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [3]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [4]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [5]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [6]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [7]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [8]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [9]) - ); - LUT3 #( - .INIT ( 8'h2F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt1 ( - .I0(m_axi_bvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [15]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<10> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<12> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<14> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_ar_txn11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_arcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_bcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/s_axis_tready_arb_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ) - ); - LUT3 #( - .INIT ( 8'h51 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_valid_to_mpf_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_4612 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_4616 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_4620 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_4624 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_4628 ) - ); - LUT3 #( - .INIT ( 8'hAC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]) - ); - LUT3 #( - .INIT ( 8'hAC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[14] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ) - ); - LUT4 #( - .INIT ( 16'h0023 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i1 ( - .I0(m_axis_tready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ) - ); - LUT6 #( - .INIT ( 64'h8888888828888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [1]) - ); - LUT4 #( - .INIT ( 16'h96AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/Mxor_n0004_xo<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF01010155 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ) - ); - LUT4 #( - .INIT ( 16'h8288 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]) - ); - LUT4 #( - .INIT ( 16'h2888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]) - ); - LUT5 #( - .INIT ( 32'hAAAAAAAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_addr_gcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [0]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_addr_mm2s_cnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ) - ); - LUT4 #( - .INIT ( 16'h8222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut [0]) - ); - LUT6 #( - .INIT ( 64'hAAAA6AAAAA6A6A6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/Mmux_S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [18]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [17]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [16]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [15]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<24> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<23> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25]) - ); - LUT5 #( - .INIT ( 32'hFD5DA808 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [24]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [23]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [22]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [21]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [20]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [19]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<9>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [9]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<8>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [8]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<15>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [15]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<14>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [14]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<13>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [13]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<12>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [12]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<11>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [11]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<10>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [10]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<11> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<9> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<28> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<27> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<26> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<25> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5135 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5134 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5135 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5134 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5135 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5134 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5135 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5134 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) - - ); - LUT5 #( - .INIT ( 32'hFFFFFFFB )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [18]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [17]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [16]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [15]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [14]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [13]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [12]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [9]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [8]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [7]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [6]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [5]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [4]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [3]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<28> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<27> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [11]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<26> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<25> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [27]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [26]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [25]) - ); - LUT5 #( - .INIT ( 32'hFD5DA808 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [24]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [23]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [22]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [21]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [20]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [10]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [19]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<9>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [19]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [9]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<8>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [8]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<15>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [15]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<14>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [29]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [14]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<13>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [13]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<12>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [12]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<11>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [23]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [11]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<10>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [21]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [10]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5548 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5547 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5548 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5547 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5548 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5547 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5548 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5547 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) - - ); - LUT5 #( - .INIT ( 32'h00000100 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [4]) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [5]) - ); - LUT3 #( - .INIT ( 8'h7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ) - ); - LUT5 #( - .INIT ( 32'hA9AAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [6]) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [3]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [3]) - ); - LUT6 #( - .INIT ( 64'h7DF5F5F5F5F5F5F5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ) - ); - LUT5 #( - .INIT ( 32'h8000FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [6]) - ); - LUT5 #( - .INIT ( 32'hA9AAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6679 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]) - ); - LUT4 #( - .INIT ( 16'hFFEA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6678 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ) - ); - LUT5 #( - .INIT ( 32'hFFFFFF80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6679 ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n02851 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [2]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/rstblk/Mmux_wr_rst_asreg_GND_10_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6789 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6790 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_6788 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6790 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt2_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(N2) - ); - LUT6 #( - .INIT ( 64'h00011011FFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt2 ( - .I0(N2), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6794 ) - ); - LUT6 #( - .INIT ( 64'h0001000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6796 ) - ); - LUT6 #( - .INIT ( 64'h0004000455550004 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo13 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6796 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]) - ); - LUT6 #( - .INIT ( 64'h444444444444444E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_read_fifo1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ), - .I2(N4), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hFFFF6FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<1>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .O(N10) - ); - LUT6 #( - .INIT ( 64'h0041410000001111 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<1>1 ( - .I0(N10), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [1]) - ); - LUT5 #( - .INIT ( 32'hFFFFFF6F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<0>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(N12) - ); - LUT6 #( - .INIT ( 64'h0041410000001111 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<0>1 ( - .I0(N12), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFF6A6FFA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I5(N14), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int15_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ), - .O(N20) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i<97>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(N22) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i<97> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(N22), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i [97]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int15_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ), - .O(N24) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6806 ) - - ); - LUT4 #( - .INIT ( 16'hFDDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6806 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ) - ); - LUT5 #( - .INIT ( 32'h80008080 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6808 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6808 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6809 ) - ); - LUT6 #( - .INIT ( 64'hF222222222222222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6809 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6811 ) - ); - LUT5 #( - .INIT ( 32'h80808000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6812 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6813 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr25 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6813 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6814 ) - ); - LUT5 #( - .INIT ( 32'hEAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr26 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6814 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6811 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h15FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6816 ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6816 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6818 ) - - ); - LUT4 #( - .INIT ( 16'hFDDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6818 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ) - ); - LUT5 #( - .INIT ( 32'h80008080 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6820 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6820 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6821 ) - ); - LUT6 #( - .INIT ( 64'hF222222222222222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6821 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6823 ) - ); - LUT5 #( - .INIT ( 32'h80808000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6824 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6825 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr25 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6825 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6826 ) - ); - LUT5 #( - .INIT ( 32'hEAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr26 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6826 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6823 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h15FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6828 ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6828 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'hAAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_4214 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [97]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ) - ); - LUT2 #( - .INIT ( 4'h7 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .O(N26) - ); - LUT6 #( - .INIT ( 64'hAAAA6AAAFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(N26), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_6647 ) - ); - LUT6 #( - .INIT ( 64'h8808AAAAFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe [0]) - ); - LUT3 #( - .INIT ( 8'h8F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<0>2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<1>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .O(N28) - ); - LUT6 #( - .INIT ( 64'hAA2A2A2AFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<1> ( - .I0(N28), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [5]) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6834 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6835 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6836 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6837 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6838 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6839 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6840 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6841 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6842 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6843 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6844 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6845 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_4214 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6846 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6848 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6849 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6850 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6851 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6852 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6853 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6854 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6856 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5541 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6862 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6863 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6865 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6867 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6868 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6869 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6870 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6871 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6872 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6873 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6874 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6875 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6876 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6877 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6878 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6879 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6679 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6880 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6881 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6678 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [5]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [0]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [4]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6882 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6883 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6884 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6885 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6886 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6887 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6888 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6889 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6890 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6891 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6892 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6893 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6894 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6895 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6896 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6897 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6898 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6899 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6900 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6901 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6902 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6903 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6904 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6905 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6906 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6907 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6908 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6909 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6910 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6911 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6912 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6913 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6914 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6915 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6916 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6917 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6918 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6919 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6920 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6921 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6922 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6923 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6924 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6925 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6926 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6927 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6928 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6929 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6930 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6931 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6932 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6933 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6934 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6935 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6936 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6937 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6938 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6939 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6940 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6941 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6942 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6943 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6944 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6945 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6946 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6947 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6948 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6949 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6950 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6951 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6952 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6953 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6954 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6955 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6956 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6957 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6958 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6959 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6960 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6961 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6962 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6963 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6964 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6965 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6966 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6967 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6968 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6969 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6970 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6971 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6972 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6973 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6974 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6975 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6976 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6977 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6978 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6979 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6980 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6981 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6982 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6983 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6984 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6985 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6986 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6987 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6988 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6989 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6990 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6991 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6992 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6993 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6994 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6995 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6996 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6997 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_6998 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_6999 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7000 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7001 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7002 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7003 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7004 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7005 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7006 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7007 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7008 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7009 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7010 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7011 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7012 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7013 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7014 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7015 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7016 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7017 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7018 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7019 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7020 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7021 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7022 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7023 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7024 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7025 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7026 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7027 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7028 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7029 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7030 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7031 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7032 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7033 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7034 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7035 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7036 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7037 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7038 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7039 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7040 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7041 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7042 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7043 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7044 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7045 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7046 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7047 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7048 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7049 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7050 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7051 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7052 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7053 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7054 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7055 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7056 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7057 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7058 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6859 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7059 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7060 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7061 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7062 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7063 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7064 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7065 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7066 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7067 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7068 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7069 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7070 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7071 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7072 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7073 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7074 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7075 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7076 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7077 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7078 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7079 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7080 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7081 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7082 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7083 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7084 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7085 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7086 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7087 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7088 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7089 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7090 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7091 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7092 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7093 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7094 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7095 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7096 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7097 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7098 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7099 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7100 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7101 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7102 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7103 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt_7104 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7105 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt_7106 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7107 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7108 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7109 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7110 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7111 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_7112 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_7113 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_7114 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ) - ); - FD \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_7115 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7116 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7117 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_7119 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6836 ) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [6]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [5]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [4]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [3]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [2]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [1]) - ); - LUT5 #( - .INIT ( 32'h81092103 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF55575555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<0>1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(m_axi_bvalid), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(N31) - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<1>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I2(m_axi_bvalid), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .O(N33) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF55755555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<1>1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(m_axi_bvalid), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(N34) - ); - LUT6 #( - .INIT ( 64'hAA00BA10AA00AA00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(N33), - .I4(N34), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6848 ) - ); - LUT4 #( - .INIT ( 16'h0001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(N31), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_7123 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_cy ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_7123 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_cy1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_7125 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ) - ); - LUT3 #( - .INIT ( 8'h82 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h82 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'hA3 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7134 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'hC5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h3A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6812 ) - ); - LUT3 #( - .INIT ( 8'h3A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6824 ) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT5 #( - .INIT ( 32'hF5C505C5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(N20), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]) - ); - LUT5 #( - .INIT ( 32'hF5C505C5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(N24), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]) - ); - LUT5 #( - .INIT ( 32'hFFFF888A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6878 ) - ); - LUT6 #( - .INIT ( 64'hFFFF222A222A222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_7113 ) - ); - LUT5 #( - .INIT ( 32'hF3FFA2AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6679 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6879 ) - ); - LUT4 #( - .INIT ( 16'hCF8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6678 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6881 ) - ); - LUT6 #( - .INIT ( 64'hAA8AAA8AAADFAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6794 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6849 ) - ); - LUT4 #( - .INIT ( 16'h7D28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6870 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6871 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6872 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6873 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6874 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6875 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6876 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6877 ) - ); - LUT6 #( - .INIT ( 64'h7DDDDDDD6CCCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6864 ) - ); - LUT5 #( - .INIT ( 32'h6FAF6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6866 ) - ); - LUT4 #( - .INIT ( 16'h5410 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_6647 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6862 ) - ); - LUT4 #( - .INIT ( 16'h5410 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6863 ) - ); - LUT5 #( - .INIT ( 32'hFFFF8880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set ( - .I0(NlwRenamedSig_OI_m_axi_rready), - .I1(m_axi_rvalid), - .I2(m_axi_rresp[0]), - .I3(m_axi_rresp[1]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6834 ) - ); - LUT5 #( - .INIT ( 32'hDDDF8880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_7114 ) - ); - LUT5 #( - .INIT ( 32'h0004FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I1(m_axi_bvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_7125 ) - ); - LUT4 #( - .INIT ( 16'hBA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7117 ) - ); - LUT3 #( - .INIT ( 8'hF4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(s_axis_tvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6845 ) - ); - LUT5 #( - .INIT ( 32'hFFFF4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I1(m_axi_bvalid), - .I2(m_axi_bresp[0]), - .I3(m_axi_bresp[1]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6835 ) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_SW0 ( - .I0(N6), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .O(N38) - ); - LUT6 #( - .INIT ( 64'h0444044404441454 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I3(N38), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_7115 ) - ); - LUT6 #( - .INIT ( 64'h2000FFFF20002000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(N40), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6852 ) - ); - LUT6 #( - .INIT ( 64'h80008000FFFF8000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(N42), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6853 ) - ); - LUT6 #( - .INIT ( 64'hFFF9FFFFFFFFFFF9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_next_state1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[3] ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(N6) - ); - LUT6 #( - .INIT ( 64'hF30CAF50F30CFF00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .O(N44) - ); - LUT6 #( - .INIT ( 64'h0000000000004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I5(N44), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_next_state1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .O(N46) - ); - LUT6 #( - .INIT ( 64'hFF88FF88FF887F88 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_next_state1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I5(N46), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .O(N48) - ); - LUT6 #( - .INIT ( 64'h0001000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ), - .I3(N48), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [7]) - ); - LUT5 #( - .INIT ( 32'hA8FFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [5]) - ); - LUT5 #( - .INIT ( 32'hFEFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [1]) - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [2]) - ); - LUT5 #( - .INIT ( 32'hFDDDFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [3]) - ); - LUT3 #( - .INIT ( 8'hDF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [4]) - ); - LUT4 #( - .INIT ( 16'h8FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [6]) - ); - LUT5 #( - .INIT ( 32'h80FFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [7]) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[3] ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT5 #( - .INIT ( 32'hAAA8AAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ) - ); - LUT5 #( - .INIT ( 32'h11015555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/s_ready_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(m_axis_tready), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .O(NlwRenamedSig_OI_m_axi_rready) - ); - LUT4 #( - .INIT ( 16'h2888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [0]) - ); - LUT6 #( - .INIT ( 64'hA9AAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6679 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [2]) - ); - LUT5 #( - .INIT ( 32'h28888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [3]) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA00000008 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ) - ); - LUT5 #( - .INIT ( 32'h44444044 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ) - ); - LUT4 #( - .INIT ( 16'h555D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ) - ); - LUT4 #( - .INIT ( 16'h80FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid1 ( - .I0(m_axis_tready), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ) - ); - LUT3 #( - .INIT ( 8'hF8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ) - ); - LUT6 #( - .INIT ( 64'h0404000444444444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(m_axi_rvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I4(m_axis_tready), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ) - ); - LUT5 #( - .INIT ( 32'hAAEAAA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_tstart_reg[0]_tstart_reg[0]_MUX_40_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_40_o ) - ); - LUT5 #( - .INIT ( 32'hEAAA2AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_tstart_reg[1]_tstart_reg[1]_MUX_39_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_39_o ) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F200000002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/Mmux_S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ) - ); - LUT4 #( - .INIT ( 16'hEA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_7112 ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5754 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5755 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT112 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6003 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6004 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6270 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6271 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT112 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6516 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6517 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'h3A00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ) - ); - LUT4 #( - .INIT ( 16'h3A00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF7FFFFF7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_SW0 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I2(m_axis_tready), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .O(N14) - ); - LUT5 #( - .INIT ( 32'hAAAA222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6864 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6865 ) - ); - LUT5 #( - .INIT ( 32'hAAAA222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6866 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6867 ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [5]) - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [4]) - ); - LUT5 #( - .INIT ( 32'h222F222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ) - ); - LUT6 #( - .INIT ( 64'hFFFFA8FFFFFEA8AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ) - ); - LUT6 #( - .INIT ( 64'hAFACAAA8AAA8AAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<5>11_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(N50) - ); - LUT6 #( - .INIT ( 64'hDDDDDDD788888882 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .I5(N50), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]) - ); - LUT5 #( - .INIT ( 32'h51500100 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_7119 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFEAA2EAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6854 ) - ); - LUT5 #( - .INIT ( 32'hFFFF0020 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6880 ) - ); - LUT6 #( - .INIT ( 64'h7B6A7B6A3322336A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I5(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6868 ) - ); - LUT5 #( - .INIT ( 32'h76765456 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6869 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5446 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5475 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5023 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5030 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6837 ) - ); - LUT5 #( - .INIT ( 32'hBBBB0B00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5446 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5475 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5023 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5030 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6838 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6599 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6617 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6335 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6353 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6839 ) - ); - LUT5 #( - .INIT ( 32'hBBBB0B00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6599 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6617 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6335 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6353 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6840 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6086 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6104 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5819 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5837 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6841 ) - ); - LUT5 #( - .INIT ( 32'hBBBB0B00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6086 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6104 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5819 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5837 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6842 ) - ); - LUT6 #( - .INIT ( 64'hFFF0FFFF44404444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5448 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5451 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5027 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6843 ) - ); - LUT6 #( - .INIT ( 64'hF0FFFFFF80888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5448 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5451 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5027 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6844 ) - ); - LUT4 #( - .INIT ( 16'hB14E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]) - ); - LUT6 #( - .INIT ( 64'h4444444444404444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ) - ); - LUT5 #( - .INIT ( 32'hA5335533 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ) - ); - LUT6 #( - .INIT ( 64'h555555556AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6811 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6814 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT6 #( - .INIT ( 64'h555555556AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6823 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6826 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT5 #( - .INIT ( 32'hFFFFAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA88888088 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6677 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hAAA2AAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n02981 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6619 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ) - ); - LUT5 #( - .INIT ( 32'h00002030 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/S_VALID_s_ready_i_AND_155_o1 ( - .I0(m_axis_tready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ) - ); - LUT5 #( - .INIT ( 32'h222222F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(m_axis_tready), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6851 ) - ); - LUT6 #( - .INIT ( 64'hA5A533CCAAAA33CC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [1]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFAAAA88A8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(m_axis_tready), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I5(m_axi_rvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6850 ) - ); - LUT5 #( - .INIT ( 32'hAAEAAA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .I1(m_axis_tready), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7116 ) - ); - LUT6 #( - .INIT ( 64'hAAAABBABAAAA88A8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ) - ); - LUT4 #( - .INIT ( 16'h1110 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(N40) - ); - LUT4 #( - .INIT ( 16'h1101 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ), - .O(N42) - ); - LUT4 #( - .INIT ( 16'h5444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFDF7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_read_fifo1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .O(N4) - ); - LUT6 #( - .INIT ( 64'hAAAAAAA9FFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [3]) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F0FCF0F0A0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]) - ); - LUT6 #( - .INIT ( 64'hAAAA33CCA5A5CCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]) - ); - LUT5 #( - .INIT ( 32'h28887DDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAAA8888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6680 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6830 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ) - ); - LUT6 #( - .INIT ( 64'h8888882888888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [2]) - ); - LUT5 #( - .INIT ( 32'hFFF8F8F8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6784 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6846 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7133 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7134 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7117 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7135 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7137 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7138 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/inverted_reset1_INV_0 ( - .I(aresetn), - .O(\U0/xst_axi_vfifo_ctrl/inverted_reset ) - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/empty_i ), - .O(m_axi_arvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/empty_i ), - .O(m_axi_awvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/w_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/empty_i ), - .O(m_axi_wvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .O(m_axi_bready) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mcount_reset_addr_0_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mcount_reset_addr_0_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<5>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<5>1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [5]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15 ( - .A0(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_7139 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_7139 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_7140 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7141 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7141 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7142 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3 ( - .A0(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_7143 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_7143 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_7144 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7145 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7145 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7146 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7147 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7147 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7148 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7149 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7149 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7150 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_7151 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_7151 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_7152 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_7152 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7153 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7153 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7154 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_7144 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7153 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_7155 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_7155 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0_4210 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7150 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7154 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7156 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7156 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6599 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7148 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7154 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7157 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7157 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6335 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7142 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7154 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7158 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7158 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6086 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7146 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7154 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7159 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7159 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5819 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_7160 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_7160 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_7161 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_7161 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_7162 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_7162 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_7163 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_7163 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_7164 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_7164 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_7165 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_7165 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_7166 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_7166 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_7167 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_7167 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_7168 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_7168 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_7169 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_7169 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_7170 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_7170 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_7171 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_7171 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_7172 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_7140 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_7172 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_7173 ) - ); - FDPE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_7173 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [0]}), - .A({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - - ); - LUT6 #( - .INIT ( 64'h9666999966669666 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_G ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N3 ) - ); - LUT6 #( - .INIT ( 64'h9999669996996696 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_F ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N2 ) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N2 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N3 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - LUT5 #( - .INIT ( 32'h02FDFD02 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'h00000000C4C0C0C0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'h0990000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_987 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_988 ) - - ); - LUT6 #( - .INIT ( 64'h222B222B2BBB222B )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT5 #( - .INIT ( 32'h69669969 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hFF2FFF2FFFFFFF2F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_985 ) - - ); - LUT6 #( - .INIT ( 64'h0990099000000990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_984 ) - - ); - LUT6 #( - .INIT ( 64'h9996999696669996 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - LUT5 #( - .INIT ( 32'h45440444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_971 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_972 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_989 ) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_989 ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ) - ); - LUT5 #( - .INIT ( 32'h4F440F04 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_988 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_986 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_987 ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF4F44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_986 ) - - ); - LUT6 #( - .INIT ( 64'hEEEEEEECAAAAAAA0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_984 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_985 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_982 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ) - - ); - LUT5 #( - .INIT ( 32'h82410000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_982 ) - - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_960 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_914 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_912 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_972 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_971 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_900 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_960 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) - - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]}), - .DID({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0] -}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0] -}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0] -}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0] -}), - .DOA({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0] -}), - .DOB({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2] -}), - .DOC({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4] -}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED -}) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .A0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .A1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .A2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .A3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .A4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]), - .DPRA0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .DPRA1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .DPRA2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .DPRA3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .DPRA4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .SPO -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ) -, - .DPO -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_915 ) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_915 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_914 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_912 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_904 ) - - ); - FDP - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ) - ); - FDP - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_904 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> -}), - .ECCPARITY({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1320 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1320 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1317 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1317 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_13 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [9]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_13 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_13 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [8]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_1279 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_1274 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_1279 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_1274 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_1268 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_1263 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_1268 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_1263 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [7]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_1257 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_1252 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_1257 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_1252 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_1246 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_1241 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_1246 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_1241 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [6]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1235 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1230 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1235 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1230 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1224 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1219 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1224 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1219 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [5]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1213 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1208 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1213 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1208 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1202 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1197 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1202 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1197 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [4]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1191 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1186 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1191 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1186 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1180 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1175 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1180 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1175 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [3]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1169 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1164 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1169 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1164 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1158 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1153 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1158 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1153 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [2]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1147 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1142 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1147 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1142 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1136 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1131 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1136 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1131 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [1]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1125 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1120 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1125 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1120 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1114 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1109 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1114 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1109 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [14]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [13]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [12]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [11]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [10]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1088 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1077 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [0]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1087 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1082 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1088 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1087 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1082 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1075 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1070 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1077 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1075 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1070 ) - - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1718 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1718 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1715 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1715 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [9]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [8]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1677 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1672 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1677 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1672 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1666 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1661 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1666 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1661 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [7]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1655 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1650 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1655 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1650 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1644 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1639 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1644 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1639 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [6]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1633 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1628 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1633 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1628 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1622 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1617 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1622 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1617 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [5]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1611 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1606 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1611 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1606 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1600 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1595 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1600 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1595 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [4]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1589 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1584 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1589 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1584 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1578 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1573 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1578 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1573 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [3]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1567 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1562 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1567 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1562 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1556 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1551 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1556 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1551 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [2]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1545 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1540 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1545 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1540 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1534 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1529 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1534 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1529 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [1]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1523 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1518 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1523 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1518 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1512 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1507 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1512 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1507 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [12]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [11]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [10]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1492 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1481 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [0]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1491 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1486 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1492 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1491 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1486 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1479 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1481 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1479 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ) - - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<0>11_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<5>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hDFFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>111 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_2007 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ) - - ); - LUT6 #( - .INIT ( 64'h4444444400004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2041 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ) - - ); - LUT5 #( - .INIT ( 32'h45440444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2051 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2052 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2066 ) - - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2066 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ) - ); - LUT6 #( - .INIT ( 64'h0000000080000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N01 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8>_SW0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N01 ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<8>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<7>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<7> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<6> ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h5515 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2005 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<8>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<7>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<7> ) - - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>111 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) - - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<5>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<4> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1901 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1899 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT6 #( - .INIT ( 64'hDDD0FDF0D0D0F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) - - ); - LUT6 #( - .INIT ( 64'h003A303A00303030 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<7> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<8> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2052 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2051 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_7 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_8 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_9 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2041 ) -, - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_2006 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<9> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_2006 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_2007 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2005 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) - - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<7> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<8> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[14] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_1902 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_1902 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1901 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1899 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_1892 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_1892 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_1881 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) - - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ) - ); - RAMB18E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 18'h00000 ), - .INIT_B ( 18'h00000 ), - .INIT_FILE ( "NONE" ), - .RAM_MODE ( "SDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 36 ), - .READ_WIDTH_B ( 0 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 18'h00000 ), - .SRVAL_B ( 18'h00000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 0 ), - .WRITE_WIDTH_B ( 36 )) - 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8] -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<0>_UNCONNECTED -}), - .WEA({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }) - ); - GND - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/rd_pntr_wr_inv_pad<6:1><0>1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_2181 ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_2181 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'hA6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'hF078F0F0F0F0F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hC6CCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[5]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'hA6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[5]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'hF078F0F0F0F0F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hC6CCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAEEAEAAAA22A2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I3(m_axi_bvalid), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_2179 ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_2131 ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ) - - ); - LUT6 #( - .INIT ( 64'h0090000000000090 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2174 ) - - ); - LUT5 #( - .INIT ( 32'h45440444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2160 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2161 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2178 ) - - ); - LUT6 #( - .INIT ( 64'h00C400C000C000C0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(m_axi_bvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2153 ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_2179 ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2178 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ) - ); - LUT6 #( - .INIT ( 64'h32222222BAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2177 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2176 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2177 ) - - ); - LUT5 #( - .INIT ( 32'h90090000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2176 ) - - ); - LUT6 #( - .INIT ( 64'h54444444DCCCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_2172 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2174 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_2173 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_2173 ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_2172 ) - - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp03 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_2169 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_2170 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - LUT6 #( - .INIT ( 64'h8421000000008421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_2170 ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_2169 ) - ); - LUT6 #( - .INIT ( 64'h0000000008000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o<5>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I2(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I3(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_bvalid), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2129 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I3(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2106 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2104 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2161 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2160 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2153 ) -, - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_2130 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_2130 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_2131 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2129 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2107 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2107 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2106 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2104 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2097 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2097 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2073 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) - - ); - RAM64X1D #( - .INIT ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM ( - .A0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .A1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .A2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .A3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .A4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .A5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .DPRA0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .DPRA1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .DPRA2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .DPRA3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .DPRA4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .DPRA5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .SPO -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_SPO_UNCONNECTED ) -, - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ) - ); - LUT6 #( - .INIT ( 64'h9666999966669666 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_G ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N3 ) - ); - LUT6 #( - .INIT ( 64'h9999669996996696 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_F ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N2 ) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N2 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N3 ), - .S -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2421 ) - ); - LUT5 #( - .INIT ( 32'h02FDFD02 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'h00000000C4C0C0C0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(m_axi_awready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'h2184000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2426 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2427 ) - ); - LUT6 #( - .INIT ( 64'h0A2B0A2B2BAF0A2B )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT5 #( - .INIT ( 32'h69669969 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hDFFFDDFFDFDFDDDD )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2424 ) - - ); - LUT6 #( - .INIT ( 64'h0000C431C4310000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2423 ) - - ); - LUT6 #( - .INIT ( 64'hA596A596965AA596 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]) - ); - LUT5 #( - .INIT ( 32'h4F440F04 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2427 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2425 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2426 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF7350 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2425 ) - ); - LUT6 #( - .INIT ( 64'hEEEEEEECAAAAAAA0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2423 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2424 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2420 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h77335500F7F3F5F0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2421 ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ) - - ); - LUT5 #( - .INIT ( 32'h82410000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2420 ) - - ); - LUT6 #( - .INIT ( 64'h00AAF0FACCEEFCFE )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Mmux_prog_full_i_GND_34_o_MUX_55_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) - - ); - LUT4 #( - .INIT ( 16'hF6F0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ) - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I2(m_axi_awready), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I3(m_axi_awready), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_awready), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2396 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I3(m_axi_awready), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I3(m_axi_awready), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2282 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2280 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/prog_full_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2268 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2396 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [13]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [15]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [17]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [19]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [21]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], 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-\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [23]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [25]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [27]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [42], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [41]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [44], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [43]}), - .DIC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , 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.DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]}), - .DOC({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [29]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [32], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [31]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [34], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [33]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [36], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [35]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [38], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [37]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [40], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [39]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED -}) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(m_axi_awlen[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(m_axi_awlen[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(m_axi_awlen[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(m_axi_awlen[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(m_axi_awlen[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(m_axi_awlen[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(m_axi_awlen[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]), - .Q(m_axi_awlen[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]), - .Q(m_axi_awaddr[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]), - .Q(m_axi_awaddr[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]), - .Q(m_axi_awaddr[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]), - .Q(m_axi_awaddr[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]), - .Q(m_axi_awaddr[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]), - .Q(m_axi_awaddr[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]), - .Q(m_axi_awaddr[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]), - .Q(m_axi_awaddr[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]), - .Q(m_axi_awaddr[8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]), - .Q(m_axi_awaddr[9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]), - .Q(m_axi_awaddr[10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]), - .Q(m_axi_awaddr[11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]), - .Q(m_axi_awaddr[12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]), - .Q(m_axi_awaddr[13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]), - .Q(m_axi_awaddr[14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]), - .Q(m_axi_awaddr[15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]), - .Q(m_axi_awaddr[16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]), - .Q(m_axi_awaddr[17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]), - .Q(m_axi_awaddr[18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]), - .Q(m_axi_awaddr[19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]), - .Q(m_axi_awaddr[20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]), - .Q(m_axi_awaddr[21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]), - .Q(m_axi_awaddr[22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]), - .Q(m_axi_awaddr[23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]), - .Q(m_axi_awaddr[24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]), - .Q(m_axi_awaddr[25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]), - .Q(m_axi_awaddr[26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]), - .Q(m_axi_awaddr[27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]), - .Q(m_axi_awaddr[28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]), - .Q(m_axi_awaddr[29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]), - .Q(m_axi_awaddr[30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]), - .Q(m_axi_awaddr[31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]), - .Q(m_axi_awid[0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2283 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2283 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2282 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2280 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2272 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2272 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ) - ); - GND \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ) - ); - LUT6 #( - .INIT ( 64'h9666999966669666 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_G ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N3 ) - ); - LUT6 #( - .INIT ( 64'h9999669996996696 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_F ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N2 ) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N2 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N3 ), - .S -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2671 ) - ); - LUT5 #( - .INIT ( 32'h02FDFD02 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'h00000000C4C0C0C0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(m_axi_arready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'h2184000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2676 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2677 ) - ); - LUT6 #( - .INIT ( 64'h0A2B0A2B2BAF0A2B )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT5 #( - .INIT ( 32'h69669969 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hDFFFDDFFDFDFDDDD )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2674 ) - - ); - LUT6 #( - .INIT ( 64'h0000C431C4310000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2673 ) - - ); - LUT6 #( - .INIT ( 64'hA596A596965AA596 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]) - ); - LUT5 #( - .INIT ( 32'h4F440F04 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2677 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2675 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2676 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF7350 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2675 ) - ); - LUT6 #( - .INIT ( 64'hEEEEEEECAAAAAAA0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2673 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2674 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2670 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h77335500F7F3F5F0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2671 ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ) - - ); - LUT5 #( - .INIT ( 32'h82410000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2670 ) - - ); - LUT6 #( - .INIT ( 64'h00AAF0FACCEEFCFE )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Mmux_prog_full_i_GND_34_o_MUX_55_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) - - ); - LUT4 #( - .INIT ( 16'hF6F0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ) - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I2(m_axi_arready), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I3(m_axi_arready), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_arready), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2646 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I3(m_axi_arready), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I3(m_axi_arready), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2532 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2530 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2518 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2646 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]}), - .DID({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], 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-\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]}), - .DID({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], 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-\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]}), - .DID({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED -}) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(m_axi_arlen[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(m_axi_arlen[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(m_axi_arlen[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(m_axi_arlen[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(m_axi_arlen[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(m_axi_arlen[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(m_axi_arlen[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]), - .Q(m_axi_arlen[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]), - .Q(m_axi_araddr[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]), - .Q(m_axi_araddr[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]), - .Q(m_axi_araddr[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]), - .Q(m_axi_araddr[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]), - .Q(m_axi_araddr[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]), - .Q(m_axi_araddr[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]), - .Q(m_axi_araddr[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]), - .Q(m_axi_araddr[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]), - .Q(m_axi_araddr[8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]), - .Q(m_axi_araddr[9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]), - .Q(m_axi_araddr[10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]), - .Q(m_axi_araddr[11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]), - .Q(m_axi_araddr[12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]), - .Q(m_axi_araddr[13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]), - .Q(m_axi_araddr[14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]), - .Q(m_axi_araddr[15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]), - .Q(m_axi_araddr[16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]), - .Q(m_axi_araddr[17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]), - .Q(m_axi_araddr[18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]), - .Q(m_axi_araddr[19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]), - .Q(m_axi_araddr[20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]), - .Q(m_axi_araddr[21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]), - .Q(m_axi_araddr[22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]), - .Q(m_axi_araddr[23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]), - .Q(m_axi_araddr[24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]), - .Q(m_axi_araddr[25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]), - .Q(m_axi_araddr[26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]), - .Q(m_axi_araddr[27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]), - .Q(m_axi_araddr[28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]), - .Q(m_axi_araddr[29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]), - .Q(m_axi_araddr[30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]), - .Q(m_axi_araddr[31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]), - .Q(m_axi_arid[0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2533 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2533 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2532 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2530 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2522 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2522 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ) - ); - GND \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ) - ); - INV \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_3148 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ) - - ); - LUT6 #( - .INIT ( 64'h00C400C000C000C0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(m_axi_wready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_3182 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ) - - ); - LUT5 #( - .INIT ( 32'h00B200F0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3193 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3192 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_3207 ) - - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_3207 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ) - ); - LUT6 #( - .INIT ( 64'h0000000080000000 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]), - .I4 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N01 ), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'hFDFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8>_SW0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N01 ) - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'hA6 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<7> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<6> ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I2(m_axi_wready), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I3(m_axi_wready), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_wready), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3146 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I3(m_axi_wready), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<7> ) - - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) - - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<4> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h2300 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv1 ( - .I0(m_axi_wready), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2992 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2990 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT6 #( - .INIT ( 64'hDDD0FDF0D0D0F0F0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) - - ); - LUT6 #( - .INIT ( 64'h003A303A00303030 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3193 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3192 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_7 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_8 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_9 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .DI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_3182 ) -, - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_3147 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<9> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_3147 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_3148 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3146 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) - - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) -, - 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\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) -, - .Q(m_axi_wlast) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) -, - .Q(m_axi_wdata[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) -, - .Q(m_axi_wdata[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) -, - .Q(m_axi_wdata[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) -, - .Q(m_axi_wdata[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) -, - .Q(m_axi_wdata[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) -, - .Q(m_axi_wdata[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) -, - .Q(m_axi_wdata[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) -, - .Q(m_axi_wdata[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) -, - .Q(m_axi_wdata[8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) -, - .Q(m_axi_wdata[9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) -, - .Q(m_axi_wdata[10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) -, - .Q(m_axi_wdata[11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]) -, - .Q(m_axi_wdata[12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]) -, - .Q(m_axi_wdata[13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [15]) -, - .Q(m_axi_wdata[14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [16]) -, - .Q(m_axi_wdata[15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [17]) -, - .Q(m_axi_wdata[16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [18]) -, - .Q(m_axi_wdata[17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [19]) -, - .Q(m_axi_wdata[18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [20]) -, - .Q(m_axi_wdata[19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [21]) -, - .Q(m_axi_wdata[20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [22]) -, - .Q(m_axi_wdata[21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [23]) -, - .Q(m_axi_wdata[22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [24]) -, - .Q(m_axi_wdata[23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [25]) -, - .Q(m_axi_wdata[24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [26]) -, - .Q(m_axi_wdata[25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [27]) -, - .Q(m_axi_wdata[26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [28]) -, - .Q(m_axi_wdata[27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [29]) -, - .Q(m_axi_wdata[28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [30]) -, - .Q(m_axi_wdata[29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [31]) -, - .Q(m_axi_wdata[30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [32]) -, - .Q(m_axi_wdata[31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [33]) -, - .Q(m_axi_wdata[32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [34]) -, - .Q(m_axi_wdata[33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [35]) -, - .Q(m_axi_wdata[34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [36]) -, - .Q(m_axi_wdata[35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [37]) -, - .Q(m_axi_wdata[36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [38]) -, - .Q(m_axi_wdata[37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [39]) -, - .Q(m_axi_wdata[38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [40]) -, - .Q(m_axi_wdata[39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [41]) -, - .Q(m_axi_wdata[40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [42]) -, - .Q(m_axi_wdata[41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [43]) -, - .Q(m_axi_wdata[42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [44]) -, - .Q(m_axi_wdata[43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [45]) -, - .Q(m_axi_wdata[44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [46]) -, - .Q(m_axi_wdata[45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [47]) -, - .Q(m_axi_wdata[46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [48]) -, - .Q(m_axi_wdata[47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [49]) -, - .Q(m_axi_wdata[48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [50]) -, - .Q(m_axi_wdata[49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [51]) -, - .Q(m_axi_wdata[50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [52]) -, - .Q(m_axi_wdata[51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [53]) -, - .Q(m_axi_wdata[52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [54]) -, - .Q(m_axi_wdata[53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [55]) -, - .Q(m_axi_wdata[54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [56]) -, - .Q(m_axi_wdata[55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [57]) -, - .Q(m_axi_wdata[56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [58]) -, - .Q(m_axi_wdata[57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [59]) -, - .Q(m_axi_wdata[58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [60]) -, - .Q(m_axi_wdata[59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [61]) -, - .Q(m_axi_wdata[60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [62]) -, - .Q(m_axi_wdata[61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [63]) -, - .Q(m_axi_wdata[62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [64]) -, - .Q(m_axi_wdata[63]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2993 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2993 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2992 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2990 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2983 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2983 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2972 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) - ); - GND \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ) - ); - VCC \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "SDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 72 ), - .READ_WIDTH_B ( 0 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 0 ), - .WRITE_WIDTH_B ( 72 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEAREGCE -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .RSTRAMB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .ADDRBWRADDR({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [48], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [47], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [46], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [45], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [44], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [43], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [42], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [41], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [40], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [39], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [38], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [37], 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-\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }) - ); - GND - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - - ); - VCC - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.veo b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.veo deleted file mode 100644 index 69d29a79f..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.veo +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2013 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 * -* * -* Rev 1. The AXI Virtual FIFO Controller is a parameterizable number of * -* multi channel FIFO. * -*******************************************************************************/ - -// Interfaces: -// AXI4Stream_MASTER_M_AXIS -// AXI4Stream_SLAVE_S_AXIS -// AXI4_MASTER_M_AXI - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_vfifo_64_0x0 your_instance_name ( - .aclk(aclk), // input aclk - .aresetn(aresetn), // input aresetn - .m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid - .m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr - .m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen - .m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize - .m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst - .m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock - .m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache - .m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot - .m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos - .m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion - .m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser - .m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid - .m_axi_awready(m_axi_awready), // input m_axi_awready - .m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb - .m_axi_wlast(m_axi_wlast), // output m_axi_wlast - .m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser - .m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid - .m_axi_wready(m_axi_wready), // input m_axi_wready - .m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid - .m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp - .m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser - .m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid - .m_axi_bready(m_axi_bready), // output m_axi_bready - .m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid - .m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr - .m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen - .m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize - .m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst - .m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock - .m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache - .m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot - .m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos - .m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion - .m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser - .m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid - .m_axi_arready(m_axi_arready), // input m_axi_arready - .m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid - .m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp - .m_axi_rlast(m_axi_rlast), // input m_axi_rlast - .m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser - .m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid - .m_axi_rready(m_axi_rready), // output m_axi_rready - .s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid - .s_axis_tready(s_axis_tready), // output s_axis_tready - .s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata - .s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb - .s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep - .s_axis_tlast(s_axis_tlast), // input s_axis_tlast - .s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid - .s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest - .m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid - .m_axis_tready(m_axis_tready), // input m_axis_tready - .m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata - .m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb - .m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep - .m_axis_tlast(m_axis_tlast), // output m_axis_tlast - .m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid - .m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest - .vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full - .vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full - .vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty - .vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr - .vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr - .vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr - .vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_vfifo_64_0x0.v when simulating -// the core, axi_vfifo_64_0x0. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.xco b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.xco deleted file mode 100644 index d0ac82911..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.xco +++ /dev/null @@ -1,75 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Fri Jan 18 18:05:21 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:axi_vfifo_ctrl:1.1 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT AXI_Virtual_FIFO_Controller xilinx.com:ip:axi_vfifo_ctrl:1.1 -# END Select -# BEGIN Parameters -CSET ar_weight_ch0=8 -CSET ar_weight_ch1=8 -CSET ar_weight_ch2=8 -CSET ar_weight_ch3=8 -CSET ar_weight_ch4=8 -CSET ar_weight_ch5=8 -CSET ar_weight_ch6=8 -CSET ar_weight_ch7=8 -CSET axi_burst_size=512 -CSET axis_tdata_width=64 -CSET axis_tuser_width=1 -CSET component_name=axi_vfifo_64_0x0 -CSET deassert_tready=false -CSET dram_base_addr=00000000 -CSET enable_axis_tid=true -CSET enable_axis_tuser=false -CSET enable_interrupt=true -CSET implementation_type=Burst_Mode -CSET number_of_channel=2 -CSET number_of_page_ch0=4096 -CSET number_of_page_ch1=4096 -CSET number_of_page_ch2=8 -CSET number_of_page_ch3=8 -CSET number_of_page_ch4=8 -CSET number_of_page_ch5=8 -CSET number_of_page_ch6=8 -CSET number_of_page_ch7=8 -CSET s2mm_txn_timeout_value=8 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T22:37:34Z -# END Extra information -GENERATE -# CRC: 175980fe diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.xise b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.xise deleted file mode 100644 index de5b1eab9..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt deleted file mode 100644 index 2fbc94c40..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt +++ /dev/null @@ -1,189 +0,0 @@ -CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 - - Core name: Xilinx LogiCORE AXI Virtual FIFO Controller - Version: 1.1 - Release: ISE 14.2 / Vivado 2012.2 - Release Date: July 25, 2012 - --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURES HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm - -................................................................................ - - -2. DEVICE SUPPORT - - - 2.1 ISE - - The following device families are supported by the core for this release. - - - All 7 Series devices - Zynq-7000 devices - All Virtex-6 devices - All Spartan-6 devices - - - 2.2 Vivado - - All 7 Series devices - Zynq-7000 devices - -................................................................................ - - -3. NEW FEATURES HISTORY - - - 3.1 ISE - - - First release - - ISE 14.2 software support - - - 3.2 Vivado - - - First release - - 2012.2 software support - -................................................................................ - - -4. RESOLVED ISSUES - - - 4.1 ISE - - - N/A - - - 4.2 Vivado - - - N/A - - -................................................................................ - - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - N/A - - - 5.2 Vivado - - - N/A - - -The most recent information, including known issues, workarounds, and -resolutions for this version is provided in the IP Release Notes User Guide -located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -................................................................................ - - -6. TECHNICAL SUPPORT & FEEDBACK - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -................................................................................ - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support. -04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support. -================================================================================ - -................................................................................ - - -8. LEGAL DISCLAIMER - -(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html deleted file mode 100644 index 7ad3604b5..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html +++ /dev/null @@ -1,200 +0,0 @@ - - -axi_vfifo_ctrl_v1_1_vinfo - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf deleted file mode 100644 index 99f1cfca9..000000000 Binary files a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf and /dev/null differ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf deleted file mode 100755 index 4b89dc81c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf +++ /dev/null @@ -1,56 +0,0 @@ -################################################################################ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - - NET "ACLK" TNM_NET = "ACLK"; - TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ; - -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd deleted file mode 100755 index 696a60687..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd +++ /dev/null @@ -1,370 +0,0 @@ --------------------------------------------------------------------------------- --- --- AXI Virtual FIFO Controller Core - core top file for implementation --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: axi_vfifo_64_0x0_exdes.vhd --- --- Description: --- This is the VFIFO core wrapper with BUFG instances for clock connections. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library unisim; -use unisim.vcomponents.all; - --------------------------------------------------------------------------------- --- Entity Declaration --------------------------------------------------------------------------------- -entity axi_vfifo_64_0x0_exdes is - PORT ( - - -- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC) - S_AXIS_TVALID : IN STD_LOGIC := '0'; - S_AXIS_TREADY : OUT STD_LOGIC := '0'; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TLAST : IN STD_LOGIC := '0'; - S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - - -- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch - M_AXIS_TVALID : OUT STD_LOGIC := '0'; - M_AXIS_TREADY : IN STD_LOGIC := '0'; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1'); - M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TLAST : OUT STD_LOGIC := '0'; - M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Write Address Channel Signals - M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWVALID : OUT STD_LOGIC := '0'; - M_AXI_AWREADY : IN STD_LOGIC := '0'; - - -- Write Data Channel Signals - M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WLAST : OUT STD_LOGIC := '0'; - M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WVALID : OUT STD_LOGIC := '0'; - M_AXI_WREADY : IN STD_LOGIC := '0'; - - -- Write Response Channel Signals - M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BVALID : IN STD_LOGIC := '0'; - M_AXI_BREADY : OUT STD_LOGIC := '1'; - - -- Read Address Channel Signals - M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARVALID : OUT STD_LOGIC := '0'; - M_AXI_ARREADY : IN STD_LOGIC := '0'; - - -- Read Data Channel Signals - M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RLAST : IN STD_LOGIC := '0'; - M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RVALID : IN STD_LOGIC := '0'; - M_AXI_RREADY : OUT STD_LOGIC := '0'; - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Status Signal - VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0'; - - -- Global Signals - ACLK : IN STD_LOGIC := '0'; - ARESETN : IN STD_LOGIC := '0' - ); - -end axi_vfifo_64_0x0_exdes; - - - -architecture xilinx of axi_vfifo_64_0x0_exdes is - - signal s_aclk_i : std_logic; - - component axi_vfifo_64_0x0 is - PORT ( - - -- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC) - S_AXIS_TVALID : IN STD_LOGIC := '0'; - S_AXIS_TREADY : OUT STD_LOGIC := '0'; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TLAST : IN STD_LOGIC := '0'; - S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - - -- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch - M_AXIS_TVALID : OUT STD_LOGIC := '0'; - M_AXIS_TREADY : IN STD_LOGIC := '0'; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1'); - M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TLAST : OUT STD_LOGIC := '0'; - M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Write Address Channel Signals - M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWVALID : OUT STD_LOGIC := '0'; - M_AXI_AWREADY : IN STD_LOGIC := '0'; - - -- Write Data Channel Signals - M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WLAST : OUT STD_LOGIC := '0'; - M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WVALID : OUT STD_LOGIC := '0'; - M_AXI_WREADY : IN STD_LOGIC := '0'; - - -- Write Response Channel Signals - M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BVALID : IN STD_LOGIC := '0'; - M_AXI_BREADY : OUT STD_LOGIC := '1'; - - -- Read Address Channel Signals - M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARVALID : OUT STD_LOGIC := '0'; - M_AXI_ARREADY : IN STD_LOGIC := '0'; - - -- Read Data Channel Signals - M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RLAST : IN STD_LOGIC := '0'; - M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RVALID : IN STD_LOGIC := '0'; - M_AXI_RREADY : OUT STD_LOGIC := '0'; - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Status Signal - VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0'; - - -- Global Signals - ACLK : IN STD_LOGIC := '0'; - ARESETN : IN STD_LOGIC := '0' - ); - - end component; - - -begin - - s_aclk_buf: bufg - PORT map( - i => ACLK, - o => s_aclk_i - ); - - exdes_inst : axi_vfifo_64_0x0 - PORT MAP ( - - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TREADY => S_AXIS_TREADY, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TSTRB => S_AXIS_TSTRB, - S_AXIS_TKEEP => S_AXIS_TKEEP, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TID => S_AXIS_TID, - S_AXIS_TDEST => S_AXIS_TDEST, - - M_AXIS_TVALID => M_AXIS_TVALID, - M_AXIS_TREADY => M_AXIS_TREADY, - M_AXIS_TDATA => M_AXIS_TDATA, - M_AXIS_TSTRB => M_AXIS_TSTRB, - M_AXIS_TKEEP => M_AXIS_TKEEP, - M_AXIS_TLAST => M_AXIS_TLAST, - M_AXIS_TID => M_AXIS_TID, - M_AXIS_TDEST => M_AXIS_TDEST, - - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => M_AXI_AWLOCK, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWUSER => M_AXI_AWUSER, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WUSER => M_AXI_WUSER, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BUSER => M_AXI_BUSER, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => M_AXI_ARLOCK, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARUSER => M_AXI_ARUSER, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RUSER => M_AXI_RUSER, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL, - VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY, - VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL, - - -- Status Signal - VFIFO_IDLE => VFIFO_IDLE, - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR, - VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR, - VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR, - - ACLK => s_aclk_i, - ARESETN => ARESETN - ); - -end xilinx; diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc deleted file mode 100755 index 94c78f7c9..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc +++ /dev/null @@ -1,55 +0,0 @@ -################################################################################ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - -create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ] - -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement.bat deleted file mode 100755 index 2384fd085..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement.bat +++ /dev/null @@ -1,88 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -copy axi_vfifo_64_0x0_exdes.ngc .\results\ - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\axi_vfifo_64_0x0.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\axi_vfifo_64_0x0_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes - -echo 'Running map' -map axi_vfifo_64_0x0_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement.sh deleted file mode 100755 index b53f3e4f0..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -cp axi_vfifo_64_0x0_exdes.ngc ./results/ - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../axi_vfifo_64_0x0.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/axi_vfifo_64_0x0_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes - -echo 'Running map' -map axi_vfifo_64_0x0_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.bat deleted file mode 100755 index 1a2dbea25..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.bat +++ /dev/null @@ -1,87 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\axi_vfifo_64_0x0.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\axi_vfifo_64_0x0_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes - -echo 'Running map' -map axi_vfifo_64_0x0_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.sh deleted file mode 100755 index 4080ad3fd..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.sh +++ /dev/null @@ -1,86 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../axi_vfifo_64_0x0.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/axi_vfifo_64_0x0_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes - -echo 'Running map' -map axi_vfifo_64_0x0_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.bat deleted file mode 100755 index 287a9068b..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.bat +++ /dev/null @@ -1,54 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem ----------------------------------------------------------------------------- -rem Script to synthesize and implement the Coregen FIFO Generator -rem ----------------------------------------------------------------------------- -rmdir /S /Q results -mkdir results -cd results -copy ..\..\..\axi_vfifo_64_0x0.ngc . -planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.sh deleted file mode 100755 index 4c0cd79b7..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.sh +++ /dev/null @@ -1,55 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the Coregen FIFO Generator -#----------------------------------------------------------------------------- -rm -rf results -mkdir results -cd results -cp ../../../axi_vfifo_64_0x0.ngc . -planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.tcl b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.tcl deleted file mode 100755 index fe88bfef8..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.tcl +++ /dev/null @@ -1,67 +0,0 @@ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - - -set device xc7k410tffg900-2 -set projName axi_vfifo_64_0x0 -set design axi_vfifo_64_0x0 -set projDir [file dirname [info script]] -create_project $projName $projDir/results/$projName -part $device -force -set_property design_mode RTL [current_fileset -srcset] -set top_module axi_vfifo_64_0x0_exdes -add_files -norecurse {../../example_design/axi_vfifo_64_0x0_exdes.vhd} -add_files -norecurse {./axi_vfifo_64_0x0.ngc} -import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_0x0_exdes.xdc} -set_property top axi_vfifo_64_0x0_exdes [get_property srcset [current_run]] -synth_design -opt_design -place_design -route_design -write_sdf -rename_top_module axi_vfifo_64_0x0_exdes -file routed.sdf -write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_0x0_exdes routed.v -report_timing -nworst 30 -path_type full -file routed.twr -report_drc -file report.drc -write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/xst.prj b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/xst.prj deleted file mode 100755 index 762d5d5f3..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/xst.prj +++ /dev/null @@ -1 +0,0 @@ -work ../example_design/axi_vfifo_64_0x0_exdes.vhd diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/xst.scr b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/xst.scr deleted file mode 100755 index fc9cf7a00..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0/implement/xst.scr +++ /dev/null @@ -1,13 +0,0 @@ -run --ifmt VHDL --ent axi_vfifo_64_0x0_exdes --p xc7k410t-ffg900-2 --ifn xst.prj --write_timing_constraints No --iobuf YES --max_fanout 100 --ofn axi_vfifo_64_0x0_exdes --ofmt NGC --bus_delimiter () --hierarchy_separator / --case Maintain diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0_flist.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0_flist.txt deleted file mode 100644 index ed74eb357..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0_flist.txt +++ /dev/null @@ -1,25 +0,0 @@ -# Output products list for -axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt -axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html -axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf -axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf -axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd -axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc -axi_vfifo_64_0x0/implement/implement.bat -axi_vfifo_64_0x0/implement/implement.sh -axi_vfifo_64_0x0/implement/implement_synplify.bat -axi_vfifo_64_0x0/implement/implement_synplify.sh -axi_vfifo_64_0x0/implement/planAhead_ise.bat -axi_vfifo_64_0x0/implement/planAhead_ise.sh -axi_vfifo_64_0x0/implement/planAhead_ise.tcl -axi_vfifo_64_0x0/implement/xst.prj -axi_vfifo_64_0x0/implement/xst.scr -axi_vfifo_64_0x0.gise -axi_vfifo_64_0x0.ngc -axi_vfifo_64_0x0.v -axi_vfifo_64_0x0.veo -axi_vfifo_64_0x0.xco -axi_vfifo_64_0x0.xise -axi_vfifo_64_0x0_flist.txt -axi_vfifo_64_0x0_xmdf.tcl -axi_vfifo_ctrl_v1_1_readme.txt diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0_xmdf.tcl b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0_xmdf.tcl deleted file mode 100644 index 0a7a3ee4d..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x0_xmdf.tcl +++ /dev/null @@ -1,127 +0,0 @@ -# The package naming convention is _xmdf -package provide axi_vfifo_64_0x0_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::axi_vfifo_64_0x0_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::axi_vfifo_64_0x0_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name axi_vfifo_64_0x0 -} -# ::axi_vfifo_64_0x0_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::axi_vfifo_64_0x0_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement_synplify.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement_synplify.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/planAhead_ise.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/planAhead_ise.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/planAhead_ise.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_ctrl_v1_1_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type text -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi_vfifo_64_0x0 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.gise b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.gise deleted file mode 100644 index 268b1f741..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.ncf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.ngc b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.ngc deleted file mode 100644 index f04f0b3e9..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e -$3fb<~753-Xnzd}foo8#5+421).97 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93:1=vF=7268ykba0;0;6{ilo2?6=4>{I0471=zfml397>51zJ13620qcji8`83>4}O:>9?7p`kf9`94?7|@;=886sadg:`>5<6sA8:4}ofe<`<728qC>:=;;|lgb=`=83;pD?9<4:m`c?7290:wE<8359~ja`>93:1=vF=7268ykba1;0;6{ilo3?6=4>{I0471=zfml297>51zJ13620qcji9`83>4}O:>9?7p`kf8`94?7|@;=886sadg;`>5<6sA8:4}ofe=`<728qC>:=;;|lgb<`=83;pD?9<4:m`cg7290:wE<8359~ja`f93:1=vF=7268ykbai;0;6{ilok?6=4>{I0471=zfmlj97>51zJ13620qcjia`83>4}O:>9?7p`kf``94?7|@;=886sadgc`>5<6sA8:4}ofee`<728qC>:=;;|lgbd`=83;pD?9<4:m`cd7290:wE<8359~ja`e93:1=vF=7268ykbaj;0;6{iloh?6=4>{I0471=zfmli97>51zJ13620qcjib`83>4}O:>9?7p`kfc`94?7|@;=886sadg``>5<6sA8:4}ofef`<728qC>:=;;|lgbg`=83;pD?9<4:m`ce7290:wE<8359~ja`d93:1=vF=7268ykbak;0;6{iloi?6=4>{I0471=zfmlh97>51zJ13620qcjic`83>4}O:>9?7p`kfb`94?7|@;=886sadga`>5<6sA8:4}ofeg`<728qC>:=;;|lgbf`=83;pD?9<4:m`cb7290:wE<8359~ja`c93:1=vF=7268ykbal;0;6{ilon?6=4>{I0471=zfmlo97>51zJ13620qcjid`83>4}O:>9?7p`kfe`94?7|@;=886sadgf`>5<6sA8:4}ofe``<728qC>:=;;|lgba`=83;pD?9<4:m`cc7290:wE<8359~ja`b93:1=vF=7268ykbam;0;6{iloo?6=4>{I0471=zfmln97>51zJ13620qcjie`83>4}O:>9?7p`j97`94?7|@;=886sae84f>5<6sA8:4}og:35<728qC>:=;;|lf=27=83;pD?9<4:ma<15290:wE<8359~j`?0;3:1=vF=7268ykc>?=0;6?1<7?tH3500>{im0==6=4>{I0471=zfl3<;7>51zJ13620qck67b83>4}O:>9?7p`j96f94?7|@;=886sae85f>5<6sA8:4}og:<5<728qC>:=;;|lf==7=83;pD?9<4:ma<>5290:wE<8359~j`??;3:1=vF=7268ykc>0=0;6{im02=6=4>{I0471=zfl33;7>51zJ13620qck68b83>4}O:>9?7p`j99f94?7|@;=886sae8:f>5<6sA8:4}og:=5<728qC>:=;;|lf=<7=83;pD?9<4:ma;3:1=vF=7268ykc>1=0;6{im03=6=4>{I0471=zfl32;7>51zJ13620qck69b83>4}O:>9?7p`j98f94?7|@;=886sae8;f>5<6sA8:4}og:e5<728qC>:=;;|lf=d7=83;pD?9<4:mai=0;6{im0k=6=4>{I0471=zfl3j;7>51zJ13620qck6ab83>4}O:>9?7p`j9`f94?7|@;=886sae8cf>5<6sA8:4}og:f5<728qC>:=;;|lf=g7=83;pD?9<4:maj=0;6{im0h=6=4>{I0471=zfl3i;7>51zJ13620qck6bb83>4}O:>9?7p`j9cf94?7|@;=886sae8`f>5<6sA8:4}og:g5<728qC>:=;;|lf=f7=83;pD?9<4:mak=0;6{im0i=6=4>{I0471=zfl3h;7>51zJ13620qck6cb83>4}O:>9?7p`j9bf94?7|@;=886sae8af>5<6sA8:4}og:`5<728qC>:=;;|lf=a7=83;pD?9<4:mal=0;6{im0n=6=4>{I0471=zfl3o;7>51zJ13620qck6db83>4}O:>9?7p`j9ef94?7|@;=886sae8ff>5<6sA8:4}og:a5<728qC>:=;;|lf=`7=83;pD?9<4:mam=0;6{im0o=6=4>{I0471=zfl3n;7>51zJ13620qck6eb83>4}O:>9?7p`j9df94?7|@;=886sae8gf>5<6sA8:4}og:b5<728qC>:=;;|lf=c7=83;pD?9<4:ma<`5290:wE<8359~j`?a;3:1=vF=7268ykc>n=0;6{im0l=6=4>{I0471=zfl3m;7>51zJ13620qck6fb83>4}O:>9?7p`j9gf94?7|@;=886sae8df>5<6sA8:4}ogb45<728qC>:=;;|lfe57=83;pD?9<4:mad65290:wE<8359~j`g7;3:1=vF=7268ykcf8=0;6{imh:=6=4>{I0471=zflk;;7>51zJ1362n:182M40;=1vbho?b;295~N5?:>0qckn0b83>4}O:>9?7p`ja1f94?7|@;=886sae`2f>5<6sA8:4}od4:=;;|le3=c=838pD?9<4:mb2>a290:wE<8359~jc1>83:1=vF=7268yk`0180;6{in>386=4>{I0471=zfo=287>51zJ13620qch89883>4}O:>9?7p`i78c94?7|@;=886saf6;a>5<6sA8:4}od4=a<728qC>:=;;|le3{in>k86=4>{I0471=zfo=j87>51zJ13620qch8a883>7}O:>9?7p`i7`c94?4|@;=886saf6ca>5<5sA8:4}od4ea<72;qC>:=;;|le3dc=838pD?9<4:mb2ga2909wE<8359~jc1e83:1>vF=7268yk`0j80;6?uG2617?xha?k81<7{in>h86=4={I0471=zfo=i87>52zJ13620qch8b883>7}O:>9?7p`i7cc94?4|@;=886saf6`a>5<5sA8:4}od4fa<72;qC>:=;;|le3gc=838pD?9<4:mb2da2909wE<8359~jc1d83:1>vF=7268yk`0k80;6?uG2617?xha?j81<7{in>i86=4={I0471=zfo=h87>52zJ13620qch8c883>7}O:>9?7p`i7bc94?4|@;=886saf6aa>5<5sA8:4}od4ga<72;qC>:=;;|le3fc=838pD?9<4:mb2ea2909wE<8359~jc1c83:1>vF=7268yk`0l80;6?uG2617?xha?m81<7{in>n86=4={I0471=zfo=o87>52zJ13620qch8d883>7}O:>9?7p`i7ec94?4|@;=886saf6fa>5<5sA8:4}od4`a<72;qC>:=;;|le3ac=838pD?9<4:mb2ba2909wE<8359~jc1b83:1>vF=7268yk`0m80;6?uG2617?xha?l81<7{in>o86=4={I0471=zfo=n87>52zJ13620qch8e883>7}O:>9?7p`i7dc94?4|@;=886saf6ga>5<5sA8:4}od4aa<72;qC>:=;;|le3`c=838pD?9<4:mb2ca2909wE<8359~jc1a83:1>vF=7268yk`0n80;6?uG2617?xha?o81<7{in>l86=4={I0471=zfo=m87>52zJ13620qch8f883>7}O:>9?7p`i39g94?7|@;=886saf2f3>5<6sA8:4}od4bg<728qC>:=;;|le3ce=83;pD?9<4:mb2`c290:wE<8359~jc1am3:1=vF=7268yk`0no0;6{in1::6=4>{I0471=zfo2;>7>51zJ13624?:0yK62533tdm4=:50;3xL714<2wej5>::182M40;=1vbk6?6;295~N5?:>0qch70683>4}O:>9?7p`i81:94?7|@;=886saf92:>5<6sA8:4}od;4g<728qC>:=;;|le<5e=83;pD?9<4:mb=6c290:wE<8359~jc>7m3:1=vF=7268yk`?8o0;6{in1;:6=4>{I0471=zfo2:>7>51zJ13624?:0yK62533tdm4<:50;3xL714<2wej5?::182M40;=1vbk6>6;295~N5?:>0qch71683>4}O:>9?7p`i80:94?7|@;=886saf93:>5<6sA8:4}od;5g<728qC>:=;;|le<4e=83;pD?9<4:mb=7c290:wE<8359~jc>6m3:1=vF=7268yk`?9o0;6{in18:6=4>{I0471=zfo29>7>51zJ1362>4?:0yK62533tdm4?:50;3xL714<2wej5<::182M40;=1vbk6=6;295~N5?:>0qch72683>4}O:>9?7p`i83:94?7|@;=886saf90:>5<6sA8:4}od;6g<728qC>:=;;|le<7e=83;pD?9<4:mb=4c290:wE<8359~jc>5m3:1=vF=7268yk`?:o0;6{in19:6=4>{I0471=zfo28>7>51zJ13624?:0yK62533tdm4>:50;3xL714<2wej5=::182M40;=1vbk6<6;295~N5?:>0qch73683>4}O:>9?7p`i82:94?7|@;=886saf91:>5<6sA8:4}od;7g<728qC>:=;;|le<6e=83;pD?9<4:mb=5c290:wE<8359~jc>4m3:1=vF=7268yk`?;o0;6{in1>:6=4>{I0471=zfo2?>7>51zJ13624?:0yK62533tdm49:50;3xL714<2wej5:::182M40;=1vbk6;6;295~N5?:>0qch74683>4}O:>9?7p`i85:94?7|@;=886saf96:>5<6sA8:4}od;0g<728qC>:=;;|le<1e=83;pD?9<4:mb=2c290:wE<8359~jc>3m3:1=vF=7268yk`?{in1?:6=4>{I0471=zfo2>>7>51zJ13624?:0yK62533tdm48:50;3xL714<2wej5;::182M40;=1vbk6:6;295~N5?:>0qch75683>4}O:>9?7p`i84:94?7|@;=886saf97:>5<6sA8:4}od;1g<728qC>:=;;|le<0e=83;pD?9<4:mb=3c290:wE<8359~jc>2m3:1=vF=7268yk`?=o0;6{in1<:6=4>{I0471=zfo2=>7>51zJ13624?:0yK62533tdm4;:50;3xL714<2wej58::182M40;=1vbk696;295~N5?:>0qch76683>4}O:>9?7p`i87:94?7|@;=886saf94:>5<6sA8:4}od;2g<728qC>:=;;|le<3e=83;pD?9<4:mb=0c290:wE<8359~jc>1m3:1=vF=7268yk`?>o0;6:1<7?tH3500>{in1=:6=4>{I0471=zfo2<>7>51zJ13624?:0yK62533tdm4::50;3xL714<2wej59::182M40;=1vqpsO@By25ag12oh;;9?l6|BCF~6zHIZpqMN \ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.v b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.v deleted file mode 100644 index f6e45e485..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.v +++ /dev/null @@ -1,88129 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -//////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version: P.49d -// \ \ Application: netgen -// / / Filename: axi_vfifo_64_0x2000000.v -// /___/ /\ Timestamp: Fri Jan 18 10:30:11 2013 -// \ \ / \ -// \___\/\___\ -// -// Command : -w -sim -ofmt verilog /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/axi_vfifo_64_0x2000000.ngc /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/axi_vfifo_64_0x2000000.v -// Device : 7k410tffg900-2 -// Input file : /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/axi_vfifo_64_0x2000000.ngc -// Output file : /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/axi_vfifo_64_0x2000000.v -// # of Modules : 1 -// Design Name : axi_vfifo_64_0x2000000 -// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ -// -// Purpose: -// This verilog netlist is a verification model and uses simulation -// primitives which may not represent the true implementation of the -// device, however the netlist is functionally correct and should not -// be modified. This file cannot be synthesized and should only be used -// with supported simulation tools. -// -// Reference: -// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 -// -//////////////////////////////////////////////////////////////////////////////// - -`timescale 1 ns/1 ps - -module axi_vfifo_64_0x2000000 ( - aclk, aresetn, m_axi_awready, m_axi_wready, m_axi_bvalid, m_axi_arready, m_axi_rlast, m_axi_rvalid, s_axis_tvalid, s_axis_tlast, m_axis_tready, -m_axi_awvalid, m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arvalid, m_axi_rready, s_axis_tready, m_axis_tvalid, m_axis_tlast, -vfifo_mm2s_rresp_err_intr, vfifo_s2mm_bresp_err_intr, vfifo_s2mm_overrun_err_intr, m_axi_bid, m_axi_bresp, m_axi_buser, m_axi_rid, m_axi_rdata, -m_axi_rresp, m_axi_ruser, s_axis_tdata, s_axis_tstrb, s_axis_tkeep, s_axis_tid, s_axis_tdest, vfifo_mm2s_channel_full, m_axi_awid, m_axi_awaddr, -m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awregion, m_axi_awuser, m_axi_wdata, -m_axi_wstrb, m_axi_wuser, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, -m_axi_arregion, m_axi_aruser, m_axis_tdata, m_axis_tstrb, m_axis_tkeep, m_axis_tid, m_axis_tdest, vfifo_s2mm_channel_full, vfifo_mm2s_channel_empty, -vfifo_idle -)/* synthesis syn_black_box syn_noprune=1 */; - input aclk; - input aresetn; - input m_axi_awready; - input m_axi_wready; - input m_axi_bvalid; - input m_axi_arready; - input m_axi_rlast; - input m_axi_rvalid; - input s_axis_tvalid; - input s_axis_tlast; - input m_axis_tready; - output m_axi_awvalid; - output m_axi_wlast; - output m_axi_wvalid; - output m_axi_bready; - output m_axi_arvalid; - output m_axi_rready; - output s_axis_tready; - output m_axis_tvalid; - output m_axis_tlast; - output vfifo_mm2s_rresp_err_intr; - output vfifo_s2mm_bresp_err_intr; - output vfifo_s2mm_overrun_err_intr; - input [0 : 0] m_axi_bid; - input [1 : 0] m_axi_bresp; - input [0 : 0] m_axi_buser; - input [0 : 0] m_axi_rid; - input [63 : 0] m_axi_rdata; - input [1 : 0] m_axi_rresp; - input [0 : 0] m_axi_ruser; - input [63 : 0] s_axis_tdata; - input [7 : 0] s_axis_tstrb; - input [7 : 0] s_axis_tkeep; - input [0 : 0] s_axis_tid; - input [0 : 0] s_axis_tdest; - input [1 : 0] vfifo_mm2s_channel_full; - output [0 : 0] m_axi_awid; - output [31 : 0] m_axi_awaddr; - output [7 : 0] m_axi_awlen; - output [2 : 0] m_axi_awsize; - output [1 : 0] m_axi_awburst; - output [0 : 0] m_axi_awlock; - output [3 : 0] m_axi_awcache; - output [2 : 0] m_axi_awprot; - output [3 : 0] m_axi_awqos; - output [3 : 0] m_axi_awregion; - output [0 : 0] m_axi_awuser; - output [63 : 0] m_axi_wdata; - output [7 : 0] m_axi_wstrb; - output [0 : 0] m_axi_wuser; - output [0 : 0] m_axi_arid; - output [31 : 0] m_axi_araddr; - output [7 : 0] m_axi_arlen; - output [2 : 0] m_axi_arsize; - output [1 : 0] m_axi_arburst; - output [0 : 0] m_axi_arlock; - output [3 : 0] m_axi_arcache; - output [2 : 0] m_axi_arprot; - output [3 : 0] m_axi_arqos; - output [3 : 0] m_axi_arregion; - output [0 : 0] m_axi_aruser; - output [63 : 0] m_axis_tdata; - output [7 : 0] m_axis_tstrb; - output [7 : 0] m_axis_tkeep; - output [0 : 0] m_axis_tid; - output [0 : 0] m_axis_tdest; - output [1 : 0] vfifo_s2mm_channel_full; - output [1 : 0] vfifo_mm2s_channel_empty; - output [1 : 0] vfifo_idle; - - // synthesis translate_off - - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] ; - wire NlwRenamedSig_OI_m_axi_rready; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ; - wire \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ; - wire \U0/xst_axi_vfifo_ctrl/inverted_reset ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3848 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3849 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_4067 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4196 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0_4210 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_4214 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_40_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_39_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_4380 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_4396 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_4612 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_4616 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_4620 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_4624 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_4628 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4_4812 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3_4815 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2_4818 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1_4821 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi_4824 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_4825 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<23> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<24> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<25> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<26> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<27> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<28> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5024 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_5027 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5028 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_5029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_5030 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5031 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5135 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5136 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5145 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5146 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5148 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4_5221 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3_5224 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2_5227 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1_5230 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi_5233 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_5234 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5235 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5236 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5237 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5238 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5239 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5240 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5241 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5242 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5243 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5244 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5245 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5247 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5248 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5249 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5250 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5251 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5252 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5253 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5254 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5255 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5256 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5257 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5258 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5259 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5260 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5261 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<25> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<26> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<27> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<28> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5448 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_5449 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5450 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_5451 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_5452 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5453 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5478 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5550 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5551 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5560 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5561 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5564 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5565 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5728 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5729 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5730 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5731 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5821 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5839 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5977 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5978 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5979 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5980 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6106 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6244 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6245 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6247 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6337 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6355 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6490 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6491 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6492 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6493 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6601 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6619 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_6649 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6680 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6681 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_6790 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6791 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6792 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ; - wire N2; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6796 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6798 ; - wire N4; - wire N6; - wire N10; - wire N12; - wire N14; - wire N20; - wire N22; - wire N24; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6808 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6810 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6811 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6813 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6814 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6815 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6816 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6818 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6820 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6822 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6823 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6825 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6826 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6827 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6828 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6830 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ; - wire N26; - wire N28; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6836 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6837 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6838 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6839 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6840 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6841 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6842 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6843 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6844 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6845 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6846 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6847 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6848 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6850 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6851 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6852 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6853 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6854 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6855 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6856 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6864 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6865 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6866 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6867 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6868 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6869 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6870 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6871 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6872 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6873 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6874 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6875 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6876 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6877 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6878 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6879 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6880 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6881 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6882 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6883 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6884 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6885 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6886 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6887 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6889 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6890 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6891 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6892 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6893 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6894 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6895 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6896 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6897 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6898 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6899 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6900 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6901 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6902 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6903 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6904 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6905 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6906 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6907 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6908 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6909 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6910 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6911 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6912 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6913 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6914 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6915 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6916 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6917 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6918 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6919 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6920 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6921 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6922 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6923 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6924 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6925 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6926 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6927 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6928 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6929 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6930 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6931 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6932 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6933 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6934 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6935 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6936 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6937 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6938 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6939 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6940 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6941 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6942 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6943 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6944 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6945 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6946 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6947 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6948 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6949 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6950 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6951 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6952 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6953 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6954 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6955 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6956 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6957 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6958 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6959 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6960 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6961 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6962 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6963 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6964 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6965 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6966 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6967 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6968 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6969 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6970 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6971 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6972 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6973 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6974 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6975 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6976 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6977 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6978 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6979 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6980 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6981 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6982 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6983 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6984 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6985 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6986 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6987 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6988 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6989 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6990 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6991 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6992 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6993 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6994 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6995 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6996 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6997 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6998 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6999 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_7000 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_7001 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7002 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7003 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7004 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7005 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7006 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7007 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7008 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7009 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7011 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7012 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7013 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7014 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7015 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7016 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7017 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7018 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7019 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7020 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7021 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7022 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7023 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7024 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7025 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7026 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7027 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7028 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7030 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7031 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7032 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7033 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7034 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7035 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7036 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7037 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7038 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7039 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7040 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7042 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7043 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7044 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7045 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7046 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7047 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7048 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7049 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7050 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7051 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7052 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7053 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7054 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7055 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7056 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7057 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7058 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7059 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7060 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7061 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7062 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7063 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7064 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7065 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7066 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7067 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7068 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7069 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7070 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7071 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7072 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7073 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7074 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7075 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7076 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7077 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7078 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7079 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7080 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7081 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7082 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7083 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7084 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7085 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7086 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7087 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7089 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7090 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7091 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7092 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7093 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7094 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7095 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7096 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7097 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7098 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7099 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7100 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7101 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7102 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7103 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7104 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7105 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt_7106 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7107 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt_7108 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7109 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7110 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7111 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7112 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7113 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_7114 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_7115 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_7116 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_7117 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7119 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7120 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_7121 ; - wire N31; - wire N33; - wire N34; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_7125 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_7127 ; - wire N38; - wire N40; - wire N42; - wire N44; - wire N46; - wire N48; - wire N50; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7135 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7137 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7138 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7139 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7140 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_7141 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_7142 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7143 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7144 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_7145 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_7146 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7148 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7149 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7150 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7151 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7152 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_7153 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_7154 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7155 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7156 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_7157 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7158 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7159 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7160 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7161 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_7162 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_7163 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_7164 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_7165 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_7166 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_7167 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_7168 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_7169 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_7170 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_7171 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_7172 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_7173 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_7174 ; - wire \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_7175 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_989 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_988 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_987 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_986 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_985 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_984 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_982 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_972 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_971 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_960 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_915 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_914 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_912 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_904 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_900 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1320 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1317 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_1279 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_1274 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_1268 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_1263 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_1257 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_1252 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_1246 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_1241 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1235 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1230 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1224 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1219 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1213 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1208 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1202 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1197 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1191 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1186 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1180 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1175 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1169 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1164 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1158 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1153 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1147 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1142 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1136 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1131 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1125 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1120 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1114 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1109 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1088 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1087 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1082 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1077 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1075 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1070 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1718 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1715 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1677 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1672 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1666 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1661 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1655 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1650 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1644 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1639 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1633 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1628 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1622 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1617 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1611 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1606 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1600 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1595 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1589 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1584 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1578 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1573 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1567 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1562 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1556 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1551 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1545 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1540 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1534 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1529 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1523 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1518 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1512 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1507 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1492 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1491 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1486 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1481 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1479 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2066 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N01 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2052 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2051 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2041 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_2007 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_2006 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2005 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_1902 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1901 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1899 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_1892 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_1881 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[1] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[13] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_2181 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_2179 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2178 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2177 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2176 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2174 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_2173 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_2172 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_2170 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_2169 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2161 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2160 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2153 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_2131 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_2130 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2129 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2107 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2106 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2104 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2097 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2073 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N3 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N2 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2427 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2426 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2425 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2424 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2423 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2421 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2420 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2396 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2283 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2282 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2280 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2272 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2268 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N3 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N2 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2677 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2676 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2675 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2674 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2673 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2671 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2670 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2646 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2533 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2532 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2530 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2522 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2518 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_3207 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N01 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3193 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3192 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_3182 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_3148 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_3147 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3146 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<1> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<2> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<3> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<4> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<5> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<6> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<7> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<8> ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2993 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2992 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2990 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2983 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2972 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ; - wire \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOADO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<15>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<14>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<13>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<12>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<11>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOBDO<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_SPO_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPADOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DOPBDOP<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED ; - wire \NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED ; - wire [72 : 72] \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 ; - wire [0 : 0] \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL ; - wire [0 : 0] NlwRenamedSig_OI_m_axis_tstrb; - wire [65 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i ; - wire [44 : 13] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i ; - wire [28 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [16 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [16 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i ; - wire [6 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload ; - wire [8 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly ; - wire [98 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg ; - wire [27 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut ; - wire [28 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload ; - wire [2 : 2] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr ; - wire [7 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i ; - wire [2 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg ; - wire [63 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [97 : 97] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i ; - wire [25 : 15] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [1 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly ; - wire [10 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut ; - wire [30 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [31 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [27 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [25 : 3] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly ; - wire [0 : 0] NlwRenamedSig_OI_m_axi_aruser; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [12 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [12 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [12 : 11] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 ; - wire [9 : 9] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly ; - wire [15 : 4] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split ; - wire [15 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result ; - wire [7 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy ; - wire [31 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r ; - wire [64 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/S ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [6 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - wire [15 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [9 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [14 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [5 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [6 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [5 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [5 : 0] \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [4 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 ; - wire [3 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [40 : 0] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count ; - wire [9 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 ; - wire [0 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet ; - wire [4 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ; - wire [3 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet ; - wire [8 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 ; - wire [8 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 ; - wire [64 : 0] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i ; - wire [1 : 1] \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg ; - assign - m_axi_awsize[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awsize[1] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awsize[0] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awburst[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awburst[0] = \NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0], - m_axi_awlock[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awcache[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awprot[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awqos[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awregion[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_awuser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_wstrb[7] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[6] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[5] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[4] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[3] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[2] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wstrb[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_wuser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arsize[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arsize[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arsize[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arburst[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arburst[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axi_arlock[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arcache[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arprot[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arqos[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[3] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[2] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[1] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_arregion[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axi_aruser[0] = NlwRenamedSig_OI_m_axi_aruser[0], - m_axis_tdata[63] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] , - m_axis_tdata[62] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] , - m_axis_tdata[61] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] , - m_axis_tdata[60] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] , - m_axis_tdata[59] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] , - m_axis_tdata[58] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] , - m_axis_tdata[57] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] , - m_axis_tdata[56] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] , - m_axis_tdata[55] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] , - m_axis_tdata[54] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] , - m_axis_tdata[53] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] , - m_axis_tdata[52] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] , - m_axis_tdata[51] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] , - m_axis_tdata[50] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] , - m_axis_tdata[49] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] , - m_axis_tdata[48] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] , - m_axis_tdata[47] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] , - m_axis_tdata[46] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] , - m_axis_tdata[45] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] , - m_axis_tdata[44] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] , - m_axis_tdata[43] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] , - m_axis_tdata[42] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] , - m_axis_tdata[41] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] , - m_axis_tdata[40] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] , - m_axis_tdata[39] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] , - m_axis_tdata[38] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] , - m_axis_tdata[37] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] , - m_axis_tdata[36] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] , - m_axis_tdata[35] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] , - m_axis_tdata[34] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] , - m_axis_tdata[33] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] , - m_axis_tdata[32] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] , - m_axis_tdata[31] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] , - m_axis_tdata[30] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] , - m_axis_tdata[29] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] , - m_axis_tdata[28] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] , - m_axis_tdata[27] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] , - m_axis_tdata[26] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] , - m_axis_tdata[25] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] , - m_axis_tdata[24] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] , - m_axis_tdata[23] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] , - m_axis_tdata[22] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] , - m_axis_tdata[21] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] , - m_axis_tdata[20] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] , - m_axis_tdata[19] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] , - m_axis_tdata[18] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] , - m_axis_tdata[17] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] , - m_axis_tdata[16] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] , - m_axis_tdata[15] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] , - m_axis_tdata[14] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] , - m_axis_tdata[13] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] , - m_axis_tdata[12] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] , - m_axis_tdata[11] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] , - m_axis_tdata[10] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] , - m_axis_tdata[9] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] , - m_axis_tdata[8] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] , - m_axis_tdata[7] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] , - m_axis_tdata[6] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] , - m_axis_tdata[5] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] , - m_axis_tdata[4] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] , - m_axis_tdata[3] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] , - m_axis_tdata[2] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] , - m_axis_tdata[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] , - m_axis_tdata[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] , - m_axis_tstrb[7] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[6] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[5] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[4] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[3] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[2] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[1] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tstrb[0] = NlwRenamedSig_OI_m_axis_tstrb[0], - m_axis_tkeep[7] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] , - m_axis_tkeep[6] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] , - m_axis_tkeep[5] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] , - m_axis_tkeep[4] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] , - m_axis_tkeep[3] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] , - m_axis_tkeep[2] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] , - m_axis_tkeep[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] , - m_axis_tkeep[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] , - m_axis_tid[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] , - m_axis_tdest[0] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72], - vfifo_s2mm_channel_full[1] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [1], - vfifo_s2mm_channel_full[0] = \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [0], - vfifo_mm2s_channel_empty[1] = -\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q , - vfifo_mm2s_channel_empty[0] = -\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q , - vfifo_idle[1] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q , - vfifo_idle[0] = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q , - m_axi_rready = NlwRenamedSig_OI_m_axi_rready, - m_axis_tvalid = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i , - m_axis_tlast = \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] , - vfifo_mm2s_rresp_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR , - vfifo_s2mm_bresp_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR , - vfifo_s2mm_overrun_err_intr = \NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ; - VCC XST_VCC ( - .P(NlwRenamedSig_OI_m_axis_tstrb[0]) - ); - GND XST_GND ( - .G(NlwRenamedSig_OI_m_axi_aruser[0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/VFIFO_CHANNEL_FULL [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3848 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4196 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3848 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3849 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3849 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3850 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<0>_0_3850 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3851 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<0>_0_3851 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_39_o ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_40_o ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ) - ); - FD #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tid[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_73 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tkeep[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tlast), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdata[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ), - .D(s_axis_tdest[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[74] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[73] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[72] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[71] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[70] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[69] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[68] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[67] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[75] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/storage_data1[0] ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6884 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6884 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6885 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6885 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6886 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6886 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6887 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6887 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6888 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6888 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6889 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6889 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6890 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6890 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6891 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6891 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6892 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6892 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6893 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6893 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6894 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6894 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6895 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6895 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6896 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6896 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6897 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6897 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6898 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6898 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6899 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6899 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6900 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6900 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6901 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6901 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6902 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6902 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6903 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6903 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [7]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [6]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [5]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [4]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [3]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [2]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [1]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_xor<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy [0]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]), - .I1(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_lut [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_4380 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6904 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6904 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_4380 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6905 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6905 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_4381 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6906 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6906 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_4382 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6907 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6907 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_4383 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6908 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6908 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_4384 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6909 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6909 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_4385 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6910 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6910 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_4386 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6911 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6911 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_4387 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6912 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6912 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_4388 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6913 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6913 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_4389 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6914 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6914 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_4390 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6915 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6915 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_4391 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6916 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6916 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_4392 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6917 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6917 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_4393 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<0>_4394 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_4396 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<15> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6918 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6918 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_4396 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6919 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6919 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_4397 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6920 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6920 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_4398 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6921 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6921 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_4399 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6922 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6922 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_4400 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6923 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6923 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_4401 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6924 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_4402 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6925 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6925 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_4403 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6926 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6926 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_4404 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6927 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6927 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_4405 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6928 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6928 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_4406 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6929 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6929 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_4407 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6930 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6930 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_4408 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6931 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6931 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_4409 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<0>_4410 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [12]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [7], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [9], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn }), - .DOA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [1], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [3], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [5], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_ar_addr/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_arcnt/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/sdpram_bcnt2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/gmux.carrynet [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_4612 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_4616 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_4620 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_4624 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_xor<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_4628 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_cy [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ), - .D(m_axi_rdata[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_76 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[75] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[74] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[0] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[71] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[70] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[69] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[68] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[67] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_66 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[66] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[65] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[64] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[63] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[62] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[61] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[60] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[59] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[58] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[57] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[56] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[55] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[54] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[53] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[52] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[51] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[50] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[49] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[48] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[47] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[46] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[45] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[44] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[43] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[42] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[41] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[40] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[39] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[38] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[37] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[36] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[35] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[34] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[33] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[32] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[31] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[30] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[29] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[28] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[27] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[26] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[25] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[24] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[23] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[22] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[21] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[20] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[19] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[18] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[17] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[16] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[15] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[14] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[0] ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<3> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_gcnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [1]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [3]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram4_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram3_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_gcnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [1]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram2_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [0]), - .DPRA0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/sdpram_mm2s_cnt/Mram_ram1_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]) - ); - FDSE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]) - ); - FDRE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg_1 ( - .C(aclk), - .D(vfifo_mm2s_channel_full[1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg_0 ( - .C(aclk), - .D(vfifo_mm2s_channel_full[0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [0]) - ); - FD #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[8].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[9].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[10].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[11].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[12].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[13].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[14].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]) - ); - LUT5 #( - .INIT ( 32'h00000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4_4812 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [4]) - ); - LUT5 #( - .INIT ( 32'h40000040 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [4]) - ); - LUT5 #( - .INIT ( 32'h04455555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi4_4812 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3_4815 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [3]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [3]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi3_4815 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2_4818 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [2]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [2]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi2_4818 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1_4821 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [1]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [1]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi1_4821 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi_4824 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [0]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lut [0]) - ); - LUT4 #( - .INIT ( 16'h7FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_lutdi_4824 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_4825 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt_7106 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<28> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6932 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<27> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6932 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_4825 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6933 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<26> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6933 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_4826 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6934 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<25> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6934 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_4827 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6935 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<24> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6935 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_4828 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<23> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_4829 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_4830 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6938 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6938 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_4831 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6939 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6939 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_4832 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6940 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6940 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_4833 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6941 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6941 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_4834 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6942 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6942 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_4835 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6943 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6943 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_4836 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6944 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6944 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_4837 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6945 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6945 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_4838 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6946 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6946 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_4839 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6947 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6947 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_4840 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6948 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6948 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_4841 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6949 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6949 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_4842 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6950 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6950 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_4843 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6951 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6951 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_4844 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6952 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6952 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_4845 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6953 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6953 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_4846 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6954 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6954 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_4847 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6955 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6955 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_4848 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6956 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6956 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_4849 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6957 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6957 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_4850 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6958 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6958 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_4851 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<0>_4852 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7107 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [31]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6959 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [30]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6959 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6960 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [29]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6960 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6961 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6961 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6962 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6962 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6963 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6963 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6964 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6964 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6965 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6965 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6966 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6966 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6967 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6967 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6968 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6968 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6969 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6969 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6970 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6970 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6971 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6971 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6972 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6972 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6973 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6973 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6974 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6974 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6975 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6975 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6976 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6976 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6977 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6977 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6978 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6978 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6979 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6979 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6980 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6980 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6981 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6981 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6982 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6982 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6983 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6983 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6984 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6984 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6985 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6985 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6986 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6986 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6987 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6987 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6988 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6988 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_5030 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5024 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_5029 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<3>_0_5030 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5028 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<2>_0_5029 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_5027 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5028 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<0>_0_5027 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[64] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[63] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[62] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[61] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[60] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[59] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[58] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[57] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[56] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[55] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[54] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[53] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[52] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[51] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[50] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[49] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[48] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[47] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[46] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[45] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[44] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[43] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[42] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[41] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[40] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[39] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[38] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[37] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[36] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[35] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[34] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[33] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[32] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[31] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[30] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[29] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[28] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[27] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[26] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[25] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[24] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[23] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[22] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[21] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[20] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[19] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[18] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[17] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[16] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[14] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[9] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5031 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5146 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5136 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5145 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5135 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5148 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5146 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_1 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5147 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5145 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5147 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5148 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_98 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [98]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_97 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i [97]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [97]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_96 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [96]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_95 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [95]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_94 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [94]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_93 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [93]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_92 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [92]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_91 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [91]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_90 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [90]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_89 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [89]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_88 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [88]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_87 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [87]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_86 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [86]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_85 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [85]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_84 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [84]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_83 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [83]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_82 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [82]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_81 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [81]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_80 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [80]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_79 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [79]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_78 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [78]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_77 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [77]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_76 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [76]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_75 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [75]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_74 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [74]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_73 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [73]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_72 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [72]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_71 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [71]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_70 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [70]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_69 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [69]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_68 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [68]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_67 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [67]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_66 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [66]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [65]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[8].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[9].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[10].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[11].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[12].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[13].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[14].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [15]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[15].gms.ms_O_UNCONNECTED ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [4]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [14]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [3]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [11]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [2]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [1]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_cy [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [2]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [1]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_cy [0]) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]) - ); - LUT5 #( - .INIT ( 32'h00000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [3]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4_5221 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [4]) - ); - LUT5 #( - .INIT ( 32'h40000040 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [4]) - ); - LUT5 #( - .INIT ( 32'h04455555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi4_5221 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [2]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3_5224 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [3]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [3]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi3_5224 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [1]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2_5227 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [2]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [2]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi2_5227 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1_5230 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [1]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [1]) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi1_5230 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy<0> ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi_5233 ), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [0]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lut [0]) - ); - LUT4 #( - .INIT ( 16'h7FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_lutdi_5233 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_5234 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt_7108 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<28> ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5235 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6989 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<27> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5235 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6989 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_5234 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5236 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6990 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<26> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5236 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6990 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_5235 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5237 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6991 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<25> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5237 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6991 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_5236 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5238 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6992 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5238 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6992 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_5237 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5239 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6993 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5239 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6993 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_5238 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5240 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6994 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5240 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6994 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_5239 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5241 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6995 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5241 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6995 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_5240 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5242 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6996 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5242 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6996 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_5241 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5243 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6997 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5243 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6997 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_5242 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5244 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6998 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5244 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6998 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_5243 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5245 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6999 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5245 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6999 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_5244 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5246 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_7000 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5246 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_7000 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_5245 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5247 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_7001 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5247 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_7001 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_5246 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5248 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7002 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5248 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7002 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_5247 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5249 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7003 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5249 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7003 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_5248 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5250 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7004 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5250 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7004 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_5249 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5251 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7005 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5251 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7005 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_5250 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5252 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7006 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5252 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7006 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_5251 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5253 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7007 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5253 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7007 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_5252 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5254 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7008 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5254 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7008 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_5253 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5255 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7009 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5255 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7009 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_5254 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5256 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7010 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5256 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7010 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_5255 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5257 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7011 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5257 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7011 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_5256 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5258 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7012 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5258 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7012 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_5257 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5259 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7013 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5259 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7013 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_5258 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5260 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7014 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5260 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7014 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_5259 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5261 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7015 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5261 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7015 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_5260 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<0>_5261 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7109 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [31]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7016 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [30]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7016 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [30]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7017 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [29]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7017 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [29]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7018 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [28]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7018 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [28]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7019 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [27]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7019 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [27]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7020 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [26]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7020 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [26]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7021 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [25]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7021 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [25]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7022 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [24]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7022 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [24]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7023 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [23]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7023 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [23]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7024 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [22]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7024 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [22]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7025 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [21]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7025 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [21]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7026 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [20]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7026 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [20]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7027 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [19]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7027 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [19]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7028 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [18]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7028 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [18]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7029 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [17]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7029 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [17]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7030 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [16]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7030 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [16]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7031 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7031 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7032 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7032 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7033 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7033 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7034 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7034 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7035 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7035 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7036 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7036 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7037 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7037 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7038 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7038 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7039 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7039 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7040 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7040 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7041 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7041 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7043 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7043 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7044 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7044 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7045 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7045 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [30]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram62_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram61_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [29], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [13], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [7], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [9], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [11], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [1], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [3], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [5], \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram4_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram3_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram5_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5453 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_5452 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5448 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_5451 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<3>_0_5452 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5450 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<2>_0_5451 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_5449 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5450 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<0>_0_5449 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_25 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_24 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_23 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_22 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_21 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_20 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_19 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_18 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_17 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_16 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_31 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [31]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_30 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [30]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_29 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [29]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_28 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [28]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_27 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_26 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_25 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_24 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_23 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_22 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_21 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_20 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_19 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_18 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_17 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_16 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5478 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5561 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5551 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5560 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5550 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5565 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d1_5561 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5564 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d1_5560 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_dly_5564 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_dly_5565 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [27]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [26]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7046 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7046 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7110 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7047 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7047 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7048 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7048 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7049 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7049 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7050 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7050 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7051 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7051 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7052 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7052 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7053 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7053 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7054 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7054 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7055 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7055 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7056 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7056 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7057 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7057 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7058 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7058 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7059 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7059 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7060 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7060 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7139 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5728 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5729 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5729 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5731 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5728 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5730 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5731 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5730 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5839 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_4067 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7061 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7061 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7111 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7062 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7062 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7063 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7063 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7064 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7064 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7065 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7065 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7066 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7066 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7067 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7067 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7068 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7068 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7069 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7069 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7070 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7070 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7071 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7071 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7072 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7072 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7073 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7073 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7074 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7074 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7075 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7075 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7137 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_rover_i ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5977 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5978 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_5978 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5980 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_5977 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5979 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_5980 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_5979 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6106 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7076 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7076 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7112 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7077 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7077 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7078 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7078 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7079 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7079 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7080 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7080 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7081 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7081 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7082 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7082 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7083 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7083 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7084 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7084 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7085 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7085 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7086 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7086 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7087 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7087 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7089 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7089 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7090 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7090 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7140 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7135 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6244 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6245 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6245 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6247 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6244 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6246 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6247 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6246 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6355 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[13] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[12] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[11] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[10] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[9] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[8] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[7] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[6] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[5] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[4] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[3] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[0].gm1.m1 ( - .CI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[5].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[6].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.carrynet [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]), - .O(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/gmux.gm[7].gms.ms_O_UNCONNECTED ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7091 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7091 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_cy [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7113 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7092 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7092 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [14]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7093 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7093 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [13]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7094 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7094 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [12]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7095 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7095 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [11]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7096 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7096 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [10]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7097 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7097 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [9]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7098 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7098 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [8]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7099 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7099 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [7]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7100 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7100 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7101 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7101 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7102 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7102 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7103 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7103 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7104 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7104 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7105 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7105 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<0> ( - .CI(NlwRenamedSig_OI_m_axi_aruser[0]), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy [0]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram31_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram34_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram33_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32 ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7138 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram32_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst2/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram1_DOD<0>_UNCONNECTED }) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]}), - .DID({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .ADDRA({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRB({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRC({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 }), - .ADDRD({NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int }), - .DOA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]}), - .DOD({\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<1>_UNCONNECTED , -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdpram_inst1/Mram_ram2_DOD<0>_UNCONNECTED }) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst1/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram ( - .A0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .A4(NlwRenamedSig_OI_m_axi_aruser[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ), - .DPRA0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .DPRA1(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA2(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA3(NlwRenamedSig_OI_m_axi_aruser[0]), - .DPRA4(NlwRenamedSig_OI_m_axi_aruser[0]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ), - .SPO(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/sdp_rover_inst2/Mram_ram_SPO_UNCONNECTED ), - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_rover_i ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6490 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_rover_i ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6491 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_dly_6491 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6493 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_dly_6490 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6492 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_13 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [13]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_14 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [14]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly_15 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_minus_rd_pntr [15]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d1_6493 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d1_6492 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_4 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_5 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_6 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_7 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_8 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_9 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_10 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_11 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_12 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_13 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_14 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr_15 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) -, - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6619 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_12 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [12]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [12]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_11 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [11]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_10 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [10]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_9 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [9]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [8]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [7]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [6]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [5]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [4]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [3]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [2]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [1]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [64]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [5]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [4]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [3]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [2]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [1]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [0]), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<7> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [6]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<6> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [6]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<5> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [5]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<4> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [4]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<3> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [3]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<2> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [2]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<1> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [1]) - ); - XORCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_xor<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .LI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_cy [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [98]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_rollover_r_4067 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [96]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [31]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [95]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [30]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [94]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [29]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [93]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [28]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [92]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [27]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [91]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [26]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [90]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [25]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [89]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [24]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [88]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [23]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [87]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [22]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [86]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [21]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [85]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [20]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [84]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [19]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [83]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [18]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [82]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [17]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [81]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [16]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [80]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [15]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [79]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [14]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [78]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [13]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [77]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [12]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [76]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [11]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [75]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [10]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [74]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [9]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [73]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [8]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [72]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [71]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [70]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [69]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [68]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [67]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [66]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [65]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [0]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[8] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [7]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[7] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[6] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[5] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[4] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[3] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[2] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[1] ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_addr_r [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .Q(\NlwRenamedSignal_U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_65 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [65]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [64]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [64]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [63]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [63]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [62]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [61]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [60]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [59]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [58]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [57]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [56]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [55]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [54]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [53]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [52]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [51]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [50]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [49]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [48]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [47]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [46]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [45]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [44]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [43]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [42]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [41]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/storage_data1 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6791 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_6790 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6792 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6791 ) - ); - FDP #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_0 ( - .C(aclk), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[0] ) - ); - FDP \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/inverted_reset ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6792 ) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full<0><0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [0]) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full<1><1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/final_full [1]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/aw_w_fifo_ready_to_awgen ) - ); - LUT3 #( - .INIT ( 8'h80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb1 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I2(m_axis_tready), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_mcdf_tvalid1 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(m_axis_tready), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [3]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [2]) - ); - LUT5 #( - .INIT ( 32'h3222F222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2-In ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_start_of_pkt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_pkt ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/start_of_txn ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [1]) - ); - LUT4 #( - .INIT ( 16'h8F88 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1_4297 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/PWR_27_o_arb_granularity[3]_equal_16_o ) - ); - LUT3 #( - .INIT ( 8'h10 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tvalid_i_arb_granularity[3]_AND_49_o ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ) - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(s_axis_tvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/S_VALID_s_ready_i_AND_52_o ) - ); - LUT3 #( - .INIT ( 8'h51 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/s_ready_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(s_axis_tready) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/S_VALID_s_ready_i_AND_54_o ) - ); - LUT6 #( - .INIT ( 64'h0000020000020202 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/valid_to_mtf_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hCFAAC0AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [24]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [10]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [12]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn210 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [11]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [13]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [14]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [15]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [16]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [17]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [19]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [18]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [20]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [21]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [22]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [23]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [26]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [27]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [28]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [29]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [30]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [31]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [3]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [4]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [5]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [6]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [7]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [8]) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [9]) - ); - LUT3 #( - .INIT ( 8'hFD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_ar_txn161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/ar_address_inc [22]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_ar_txn [25]) - ); - LUT3 #( - .INIT ( 8'h2F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt1 ( - .I0(m_axi_bvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_bcnt ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [15]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_arcnt161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_arcnt [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<10> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<12> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<14> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [15]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<4> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<6> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<8> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_data_bcnt161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt[15]_GND_1800_o_add_12_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_data_bcnt [9]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_ar_txn11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_ar_txn ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_arcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_arcnt ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mmux_wr_addr_bcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/wr_addr_bcnt ) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/s_axis_tready_arb_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_ar_txn ) - ); - LUT3 #( - .INIT ( 8'h51 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_valid_to_mpf_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_4_mand1_4612 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_3_mand1_4616 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_2_mand1_4620 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_1_mand1_4624 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Eqn_0_mand1_4628 ) - ); - LUT3 #( - .INIT ( 8'hAC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]) - ); - LUT3 #( - .INIT ( 8'hAC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlast_to_switch ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[14] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/trans_to_switch ) - ); - LUT4 #( - .INIT ( 16'h0023 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i1 ( - .I0(m_axis_tready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ) - ); - LUT6 #( - .INIT ( 64'h8888888828888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [3]) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<2> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [2]) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [1]) - ); - LUT4 #( - .INIT ( 16'h96AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/Mxor_n0004_xo<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF01010155 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in_s_axis_tvalid_arb_rs_in_OR_6_o ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ) - ); - LUT4 #( - .INIT ( 16'h8288 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<1> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [1]) - ); - LUT4 #( - .INIT ( 16'h2888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]) - ); - LUT5 #( - .INIT ( 32'hAAAAAAAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_addr_gcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_gcnt ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_gcnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_gcnt [0]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [0]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_addr_mm2s_cnt11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_addr_mm2s_cnt ) - ); - LUT4 #( - .INIT ( 16'h8222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut [0]) - ); - LUT6 #( - .INIT ( 64'hAAAA6AAAAA6A6A6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_gcnt [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_gcnt[3]_GND_1097_o_add_3_OUT_lut<0> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/Mmux_S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<1> ) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [18]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<15> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [18]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [17]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<14> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [17]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [16]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<13> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [16]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<12> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [15]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<24> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [27]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<23> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [26]) - ); - LUT5 #( - .INIT ( 32'hFD5DA808 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [24]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [23]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<20> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [23]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [22]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<19> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [22]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [21]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<18> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [21]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [20]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<17> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [20]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [19]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<16> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [19]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<9>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [18]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [9]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<8>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [8]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<15>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [15]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<14>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [14]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<13>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [13]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<12>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [24]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [12]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<11>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [22]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [11]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<10>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [20]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [10]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<11> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<9> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<28> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [31]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<27> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [30]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<26> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [29]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<25> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [28]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT5 #( - .INIT ( 32'hFB73FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [25]) - ); - LUT4 #( - .INIT ( 16'hE4FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<22> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/wr_data_i [25]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5136 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5135 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5136 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5135 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5136 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5135 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5136 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5135 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) - - ); - LUT5 #( - .INIT ( 32'hFFFFFFFB )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly[2][12]_diff_pntr[12]_LessThan_20_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_63_o ) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [18]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<15> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [18]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [17]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<14> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [17]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [16]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<13> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [16]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<12> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [15]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<11> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [14]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<10> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [13]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<9> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [12]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i291 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<6> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [9]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i281 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<5> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [8]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i271 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<4> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [7]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i261 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [6]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i251 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<2> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [5]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i241 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<1> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [4]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i231 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [3]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int221 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<28> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [31]) - ); - LUT5 #( - .INIT ( 32'h88088000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int211 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<27> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [30]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<8> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [11]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int201 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<26> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [29]) - ); - LUT5 #( - .INIT ( 32'hC8004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int191 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<25> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [28]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [27]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i181 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<24> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [27]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [26]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<23> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [26]) - ); - LUT5 #( - .INIT ( 32'hFD5DA808 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [24]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [23]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<20> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [23]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [22]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<19> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [22]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [21]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<18> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [21]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [20]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<17> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [20]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<7> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [10]) - ); - LUT5 #( - .INIT ( 32'hC8400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [19]) - ); - LUT4 #( - .INIT ( 16'hA280 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<16> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [19]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<9>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [19]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [19]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [18]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [9]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<8>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [17]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [17]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [8]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<15>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [31]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [31]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [15]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<14>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [29]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [14]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<13>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [13]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<12>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [24]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [12]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<11>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [23]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [23]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [22]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [11]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<10>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [21]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [21]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [20]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [10]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT5 #( - .INIT ( 32'hFB73FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [25]) - ); - LUT4 #( - .INIT ( 16'hE4FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<22> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/wr_data_i [25]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.msb_eql ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.lsb_eql ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntrs_eql ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5551 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5550 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5551 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5550 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5551 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5550 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/Mmux_wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_roll_over_d2_5551 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_roll_over_d2_5550 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd_dly[12]_ch_depth_minus_rd_m_wr[12]_mux_16_OUT<9> ) - - ); - LUT5 #( - .INIT ( 32'h00000100 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/diff_pntr[12]_pf_thresh_dly[2][12]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_91_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_in_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_107_o ) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [5]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [6]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/sdpo_rd_data_out_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.overrun_compare_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'hF0F0EE44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [15]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_lut [0]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [10]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [11]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [12]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [13]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [14]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [1]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [2]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [3]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [4]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [5]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [6]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [7]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [8]) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_rs_A [9]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int17 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [0]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [10]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [11]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [12]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [13]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [14]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int91 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [2]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int101 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [3]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [5]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [6]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [7]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [8]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [9]) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/S_VALID_s_ready_i_AND_102_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/we_int ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice1/S_VALID_s_ready_i_AND_56_o ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [4]) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [5]) - ); - LUT3 #( - .INIT ( 8'h7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ) - ); - LUT5 #( - .INIT ( 32'hA9AAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [6]) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [3]) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<2>1 ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [3]) - ); - LUT6 #( - .INIT ( 64'h7DF5F5F5F5F5F5F5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ) - ); - LUT5 #( - .INIT ( 32'h8000FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [6]) - ); - LUT5 #( - .INIT ( 32'hA9AAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6681 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]) - ); - LUT4 #( - .INIT ( 16'hFFEA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6680 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_val ) - ); - LUT5 #( - .INIT ( 32'hFFFFFF80 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6681 ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_val ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n02851 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ) - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [2]) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<1>1 ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [1]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/txn_from_mcf_tlast_i_AND_119_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/rstblk/Mmux_wr_rst_asreg_GND_10_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d1_6791 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6792 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_GND_10_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_d2_6790 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_asreg_6792 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt2_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(N2) - ); - LUT6 #( - .INIT ( 64'h00011011FFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt2 ( - .I0(N2), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/we_arcnt ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6796 ) - ); - LUT6 #( - .INIT ( 64'h0001000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6798 ) - ); - LUT6 #( - .INIT ( 64'h0004000455550004 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo13 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo11_6798 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_read_ar_fifo1 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]) - ); - LUT6 #( - .INIT ( 64'h444444444444444E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_read_fifo1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ), - .I2(N4), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hFFFF6FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<1>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .O(N10) - ); - LUT6 #( - .INIT ( 64'h0041410000001111 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<1>1 ( - .I0(N10), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [1]) - ); - LUT5 #( - .INIT ( 32'hFFFFFF6F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<0>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_trans_last_arb ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(N12) - ); - LUT6 #( - .INIT ( 64'h0041410000001111 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_clr_mm2s_mask<0>1 ( - .I0(N12), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFF6A6FFA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I5(N14), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int15_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i[31]_GND_1143_o_add_8_OUT<21> ), - .O(N20) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i<97>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(N22) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i<97> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(N22), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/m_axis_payload_wr_out_i [97]) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int15_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i[31]_GND_1305_o_add_8_OUT<21> ), - .O(N24) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6808 ) - - ); - LUT4 #( - .INIT ( 16'hFDDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6808 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ) - ); - LUT5 #( - .INIT ( 32'h80008080 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6810 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6810 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6811 ) - ); - LUT6 #( - .INIT ( 64'hF222222222222222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6811 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6813 ) - ); - LUT5 #( - .INIT ( 32'h80808000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6814 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6815 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr25 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6815 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6816 ) - ); - LUT5 #( - .INIT ( 32'hEAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr26 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6816 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6813 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h15FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6818 ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6818 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6820 ) - - ); - LUT4 #( - .INIT ( 16'hFDDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o3 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o31_6820 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/pf_thresh_dly[2][15]_diff_pntr[15]_LessThan_20_o ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ) - ); - LUT5 #( - .INIT ( 32'h80008080 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6822 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr21_6822 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6823 ) - ); - LUT6 #( - .INIT ( 64'hF222222222222222 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr22_6823 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6825 ) - ); - LUT5 #( - .INIT ( 32'h80808000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6826 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6827 ) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr25 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23_6827 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6828 ) - ); - LUT5 #( - .INIT ( 32'hEAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr26 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6828 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6825 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ) - ); - LUT5 #( - .INIT ( 32'h7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [12]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [11]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) - - ); - LUT6 #( - .INIT ( 64'h15FFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [9]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [8]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6830 ) - - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_2 [9]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o31_6830 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o3 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/diff_pntr[15]_pf_thresh_dly[2][15]_LessThan_20_o ) - ); - LUT4 #( - .INIT ( 16'hAAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_4214 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [97]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[12] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[13] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ) - ); - LUT2 #( - .INIT ( 4'h7 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .O(N26) - ); - LUT6 #( - .INIT ( 64'hAAAA6AAAFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(N26), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_6649 ) - ); - LUT6 #( - .INIT ( 64'h8808AAAAFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [7]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe [0]) - ); - LUT3 #( - .INIT ( 8'h8F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<0>2 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [4]) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<1>_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [1]), - .O(N28) - ); - LUT6 #( - .INIT ( 64'hAA2A2A2AFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/append_strobe<1> ( - .I0(N28), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [6]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstrb_r [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_payload [5]) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6836 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6837 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6838 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6839 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6840 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6841 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6842 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6843 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6844 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6845 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6846 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6847 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/m_valid_i_4214 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6848 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6850 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ) - ); - FDR \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6851 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6852 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6853 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6854 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6855 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6856 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6858 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_glue_set ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_5544 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_tvalid ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6864 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6865 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6867 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6869 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6870 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6871 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6872 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6873 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6874 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6875 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6876 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6877 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6878 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6879 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6880 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6881 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6681 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6882 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ) - ); - FDS #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6883 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6680 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ), - .R(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [5]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [4]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [3]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [2]) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [1]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.lsb_eql_lut [0]) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [4]) - ); - LUT4 #( - .INIT ( 16'h1001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [3]) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<27>_rt_6884 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<26>_rt_6885 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<25>_rt_6886 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<24>_rt_6887 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<23>_rt_6888 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<22>_rt_6889 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<21>_rt_6890 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<20>_rt_6891 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<19>_rt_6892 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<18>_rt_6893 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<17>_rt_6894 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<16>_rt_6895 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<15>_rt_6896 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<14>_rt_6897 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<13>_rt_6898 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<12>_rt_6899 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<11>_rt_6900 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<10>_rt_6901 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<9>_rt_6902 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_ar_address_inc_Madd_cy<8>_rt_6903 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<14>_rt_6904 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<13>_rt_6905 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<12>_rt_6906 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<11>_rt_6907 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<10>_rt_6908 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<9>_rt_6909 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<8>_rt_6910 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<7>_rt_6911 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<6>_rt_6912 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<5>_rt_6913 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<4>_rt_6914 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<3>_rt_6915 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<2>_rt_6916 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_cy<1>_rt_6917 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<14>_rt_6918 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<13>_rt_6919 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<12>_rt_6920 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<11>_rt_6921 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<10>_rt_6922 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<9>_rt_6923 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<8>_rt_6924 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<7>_rt_6925 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<6>_rt_6926 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<5>_rt_6927 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<4>_rt_6928 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<3>_rt_6929 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<2>_rt_6930 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_cy<1>_rt_6931 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<27>_rt_6932 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<26>_rt_6933 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<25>_rt_6934 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<24>_rt_6935 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<23>_rt_6936 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<22>_rt_6937 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<21>_rt_6938 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<20>_rt_6939 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<19>_rt_6940 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<18>_rt_6941 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<17>_rt_6942 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<16>_rt_6943 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<15>_rt_6944 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<14>_rt_6945 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<13>_rt_6946 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<12>_rt_6947 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<11>_rt_6948 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<10>_rt_6949 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<9>_rt_6950 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<8>_rt_6951 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<7>_rt_6952 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<6>_rt_6953 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<5>_rt_6954 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<4>_rt_6955 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<3>_rt_6956 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<2>_rt_6957 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_cy<1>_rt_6958 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_6959 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_6960 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_6961 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_6962 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_6963 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_6964 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_6965 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_6966 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_6967 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_6968 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_6969 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_6970 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_6971 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_6972 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_6973 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_6974 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_6975 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_6976 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_6977 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_6978 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_6979 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_6980 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_6981 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_6982 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_6983 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_6984 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_6985 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_6986 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_6987 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_6988 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<27>_rt_6989 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<26>_rt_6990 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<25>_rt_6991 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<24>_rt_6992 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<23>_rt_6993 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<22>_rt_6994 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<21>_rt_6995 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<20>_rt_6996 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<19>_rt_6997 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<18>_rt_6998 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<17>_rt_6999 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<16>_rt_7000 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<15>_rt_7001 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<14>_rt_7002 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<13>_rt_7003 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<12>_rt_7004 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<11>_rt_7005 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<10>_rt_7006 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<9>_rt_7007 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<8>_rt_7008 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<7>_rt_7009 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<6>_rt_7010 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<5>_rt_7011 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<4>_rt_7012 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<3>_rt_7013 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<2>_rt_7014 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_cy<1>_rt_7015 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [30]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<30>_rt_7016 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [29]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<29>_rt_7017 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [28]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<28>_rt_7018 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [27]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<27>_rt_7019 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [26]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<26>_rt_7020 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [25]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<25>_rt_7021 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [24]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<24>_rt_7022 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [23]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<23>_rt_7023 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [22]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<22>_rt_7024 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [21]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<21>_rt_7025 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [20]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<20>_rt_7026 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [19]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<19>_rt_7027 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [18]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<18>_rt_7028 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [17]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<17>_rt_7029 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [16]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<16>_rt_7030 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<15>_rt_7031 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7032 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7033 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7034 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7035 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7036 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7037 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7038 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7039 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7040 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7041 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7042 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7043 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7044 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7045 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7046 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7047 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7048 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7049 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7050 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7051 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7052 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7053 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7054 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7055 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7056 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7057 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7058 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7059 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7060 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6861 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7061 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7062 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7063 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7064 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7065 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7066 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7067 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7068 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7069 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7070 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7071 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7072 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7073 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7074 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7075 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6862 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_A17_7076 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7077 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7078 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7079 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7080 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7081 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7082 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7083 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7084 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7085 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7086 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7087 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7088 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7089 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7090 ) - ); - LUT4 #( - .INIT ( 16'h00E4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A171 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/m_valid_i_6863 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gov_err_flag.wr_pntr_plus1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_A17_7091 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [14]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<14>_rt_7092 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [13]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<13>_rt_7093 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<12>_rt_7094 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [11]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<11>_rt_7095 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [10]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<10>_rt_7096 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<9>_rt_7097 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [8]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<8>_rt_7098 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<7>_rt_7099 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<6>_rt_7100 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<5>_rt_7101 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<4>_rt_7102 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<3>_rt_7103 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<2>_rt_7104 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_cy<1>_rt_7105 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_xor<28>_rt_7106 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7107 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_xor<28>_rt_7108 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<31>_rt_7109 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7110 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7111 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7112 ) - ); - LUT1 #( - .INIT ( 2'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_xor<15>_rt_7113 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_7114 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ) - ); - FDS #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_7115 ), - .S(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_7116 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ) - ); - FD \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_7117 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7119 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7120 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_7121 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcpf_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mctf_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/overrun_err_mcdf_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_OVERRUN_ERR_INTR_glue_set_6838 ) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<7>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<14> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<15> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [7]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<6>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [12]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<12> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<13> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [6]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<5>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [11]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<10> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<11> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [5]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [8]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<8> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<9> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [4]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<6> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<7> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [3]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<4> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<5> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [2]) - ); - LUT5 #( - .INIT ( 32'h81210903 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<2> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<3> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [1]) - ); - LUT5 #( - .INIT ( 32'h81092103 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt_arb [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<0> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt[15]_GND_1800_o_add_14_OUT<1> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/comp1_inst/v1 [0]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF55575555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<0>1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(m_axi_bvalid), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(N31) - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<1>1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I2(m_axi_bvalid), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .O(N33) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF55755555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/set_empty<1>1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(m_axi_bvalid), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(N34) - ); - LUT6 #( - .INIT ( 64'hAA00BA10AA00AA00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I3(N33), - .I4(N34), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6850 ) - ); - LUT4 #( - .INIT ( 16'h0001 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(N31), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_7125 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_cy ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched ), - .DI(NlwRenamedSig_OI_m_axi_aruser[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut_7125 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ) - ); - MUXCY \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_cy1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/counts_matched_l1 ), - .DI(NlwRenamedSig_OI_m_axis_tstrb[0]), - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_7127 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ) - ); - LUT3 #( - .INIT ( 8'h82 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h82 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'hA3 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'hC5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h3A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6814 ) - ); - LUT3 #( - .INIT ( 8'h3A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr22_6826 ) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT3 #( - .INIT ( 8'hD1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_wr_data_i3_split [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [15]) - ); - LUT5 #( - .INIT ( 32'hF5C505C5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_wr_data_int15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(N20), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/sdpram_top_inst/wr_data_int [24]) - ); - LUT5 #( - .INIT ( 32'hF5C505C5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_wr_data_int15 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .I4(N24), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/sdpram_top_inst/wr_data_int [24]) - ); - LUT5 #( - .INIT ( 32'hFFFF888A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_glue_rst_6880 ) - ); - LUT6 #( - .INIT ( 64'hFFFF222A222A222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_4052 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tstart_rstpot_7115 ) - ); - LUT5 #( - .INIT ( 32'hF3FFA2AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6681 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_glue_rst_6881 ) - ); - LUT4 #( - .INIT ( 16'hCF8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_6680 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_byte_glue_rst_6883 ) - ); - LUT6 #( - .INIT ( 64'hAA8AAA8AAADFAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state1 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Mmux_next_state11_6796 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_glue_set_6851 ) - ); - LUT4 #( - .INIT ( 16'h7D28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/pkt_cnt_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/Maccum_pkt_cnt_reg_lut [0]) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i7 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_7_glue_rst_6872 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i6 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_6_glue_rst_6873 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i5 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_5_glue_rst_6874 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i4 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_4_glue_rst_6875 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i3 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_3_glue_rst_6876 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i2 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_2_glue_rst_6877 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i1 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_1_glue_rst_6878 ) - ); - LUT6 #( - .INIT ( 64'hDD0DDDDD88088888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i_0_glue_rst_6879 ) - ); - LUT6 #( - .INIT ( 64'h7DDDDDDD6CCCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [6]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6866 ) - ); - LUT5 #( - .INIT ( 32'h6FAF6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6868 ) - ); - LUT4 #( - .INIT ( 16'h5410 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [8]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes5_6649 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_8_glue_rst_6864 ) - ); - LUT4 #( - .INIT ( 16'h5410 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0285 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [7]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_no_of_bytes4 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_7_glue_rst_6865 ) - ); - LUT5 #( - .INIT ( 32'hFFFF8880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set ( - .I0(NlwRenamedSig_OI_m_axi_rready), - .I1(m_axi_rvalid), - .I2(m_axi_rresp[0]), - .I3(m_axi_rresp[1]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/MM2S_RRESP_ERR_INTR_glue_set_6836 ) - ); - LUT5 #( - .INIT ( 32'hDDDF8880 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_4041 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tdest_r_0_rstpot_7116 ) - ); - LUT5 #( - .INIT ( 32'h0004FFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I1(m_axi_bvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I3(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_lut1_7127 ) - ); - LUT4 #( - .INIT ( 16'hBA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7119 ) - ); - LUT3 #( - .INIT ( 8'hF4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(s_axis_tvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_glue_set_6847 ) - ); - LUT5 #( - .INIT ( 32'hFFFF4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .I1(m_axi_bvalid), - .I2(m_axi_bresp[0]), - .I3(m_axi_bresp[1]), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gintr.intr_inst/S2MM_BRESP_ERR_INTR_glue_set_6837 ) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_SW0 ( - .I0(N6), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]), - .O(N38) - ); - LUT6 #( - .INIT ( 64'h0444044404441454 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .I3(N38), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_rstpot_7117 ) - ); - LUT6 #( - .INIT ( 64'h2000FFFF20002000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(N40), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6854 ) - ); - LUT6 #( - .INIT ( 64'h80008000FFFF8000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(N42), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/storage_data1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/clr_mm2s_mask [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6855 ) - ); - LUT6 #( - .INIT ( 64'hFFF9FFFFFFFFFFF9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_next_state1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[3] ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(N6) - ); - LUT6 #( - .INIT ( 64'hF30CAF50F30CFF00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .O(N44) - ); - LUT6 #( - .INIT ( 64'h0000000000004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I5(N44), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_channel_4774 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_next_state1_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .O(N46) - ); - LUT6 #( - .INIT ( 64'hFF88FF88FF887F88 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_next_state1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I5(N46), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/next_state ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_SW1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .O(N48) - ); - LUT6 #( - .INIT ( 64'h0001000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ), - .I3(N48), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/_n005811_4645 ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<0> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [0]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [1]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [2]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [3]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [4]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [5]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [6]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [6]) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_len_i [7]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_aw_len_i_lut [7]) - ); - LUT5 #( - .INIT ( 32'hA8FFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [5]) - ); - LUT5 #( - .INIT ( 32'hFEFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [1]) - ); - LUT4 #( - .INIT ( 16'hFFBF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [2]) - ); - LUT5 #( - .INIT ( 32'hFDDDFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [3]) - ); - LUT3 #( - .INIT ( 8'hDF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [4]) - ); - LUT4 #( - .INIT ( 16'h8FFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [6]) - ); - LUT5 #( - .INIT ( 32'h80FFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tstrb_i81 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tstrb_i [7]) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/Mmux_roll_over_int11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/sdpram_top_inst/roll_over_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[3] ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT3 #( - .INIT ( 8'h8D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rom_rd_addr_int ) - ); - LUT5 #( - .INIT ( 32'hAAA8AAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/tvalid_w_rs2 ) - ); - LUT4 #( - .INIT ( 16'h4440 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ) - ); - LUT5 #( - .INIT ( 32'h11015555 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/s_ready_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(m_axis_tready), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .O(NlwRenamedSig_OI_m_axi_rready) - ); - LUT4 #( - .INIT ( 16'h2888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [0]) - ); - LUT6 #( - .INIT ( 64'hA9AAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/first_txn_6681 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [2]) - ); - LUT5 #( - .INIT ( 32'h28888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mmux_wr_data_mm2s_cnt41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<3> ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_cy<0> ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<1> ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Madd_rd_data_mm2s_cnt[3]_GND_1097_o_add_5_OUT_lut<2> ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [3]) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA00000008 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_4790 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s2 ) - ); - LUT5 #( - .INIT ( 32'h44444044 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ) - ); - LUT4 #( - .INIT ( 16'h555D )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_gcnt ) - ); - LUT4 #( - .INIT ( 16'h80FF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid1 ( - .I0(m_axis_tready), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/we_mm2s_valid ) - ); - LUT3 #( - .INIT ( 8'hF8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_val ) - ); - LUT6 #( - .INIT ( 64'h0404000444444444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(m_axi_rvalid), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I4(m_axis_tready), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/S_VALID_s_ready_i_AND_145_o ) - ); - LUT3 #( - .INIT ( 8'h40 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_56_o ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<3>1 ) - ); - LUT5 #( - .INIT ( 32'hAAEAAA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_tstart_reg[0]_tstart_reg[0]_MUX_40_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[0]_tstart_reg[0]_MUX_40_o ) - ); - LUT5 #( - .INIT ( 32'hEAAA2AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mmux_tstart_reg[1]_tstart_reg[1]_MUX_39_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[65] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tstart_reg[1]_tstart_reg[1]_MUX_39_o ) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F200000002 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/Mmux_S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_mask [1]), - .I1(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/vfifo_mm2s_channel_full_reg [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_4789 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.storage_data2 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/S_PAYLOAD_DATA[1]_gfwd_rev.storage_data2[1]_mux_0_OUT<0> ) - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<4>1 ) - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<5>1 ) - ); - LUT4 #( - .INIT ( 16'hEA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_4311 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/storage_data1[0] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/tid_r_0_rstpot_7114 ) - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_5756 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_5757 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT112 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6005 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6006 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT111 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6272 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6273 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [10]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<10> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT41 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [12]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<12> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [11]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<11> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT51 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [13]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<13> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT71 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [15]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<15> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT61 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [14]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<14> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT112 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT131 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT121 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<5> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT141 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<7> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT161 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [9]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<9> ) - - ); - LUT4 #( - .INIT ( 16'hEB28 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/Mmux_wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT151 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_roll_over_d2_6518 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_roll_over_d2_6519 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly [8]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd_dly[15]_ch_depth_minus_rd_m_wr[15]_mux_16_OUT<8> ) - - ); - LUT4 #( - .INIT ( 16'h3A00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ) - ); - LUT4 #( - .INIT ( 16'h3A00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/pf_thresh_dly_0 [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [15]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF7FFFFF7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_SW0 ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1[76] ), - .I2(m_axis_tready), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/rd_data_mm2s_gcnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/wr_data_mm2s_cnt [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/comp1_inst/n0004 ), - .O(N14) - ); - LUT5 #( - .INIT ( 32'hAAAA222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_ce_6866 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_6_glue_rst_6867 ) - ); - LUT5 #( - .INIT ( 32'hAAAA222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_ce_6868 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_5_glue_rst_6869 ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [5]) - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [1]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_payload [4]) - ); - LUT5 #( - .INIT ( 32'h222F222A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.load_s1 ) - ); - LUT6 #( - .INIT ( 64'hFFFFA8FFFFFEA8AA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2-In ) - ); - LUT6 #( - .INIT ( 64'hAFACAAA8AAA8AAA8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<5>11_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(N50) - ); - LUT6 #( - .INIT ( 64'hDDDDDDD788888882 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .I5(N50), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [5]) - ); - LUT5 #( - .INIT ( 32'h51500100 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[10] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_rstpot1_7121 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFEAA2EAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd2_4188 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/gfwd_rev.state_FSM_FFd1_4802 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/s_axis_tready_arb_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_glue_set_6856 ) - ); - LUT5 #( - .INIT ( 32'hFFFF0020 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_glue_set_6882 ) - ); - LUT6 #( - .INIT ( 64'h7B6A7B6A3322336A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I5(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_4_glue_rst_6870 ) - ); - LUT5 #( - .INIT ( 32'h76765456 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice2/storage_data1[11] ), - .I4(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/no_of_bytes_3_glue_rst_6871 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5448 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5478 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_3743 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5024 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5031 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6839 ) - ); - LUT5 #( - .INIT ( 32'hBBBB0B00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_5448 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5478 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5024 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/prog_full_i_5031 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_3742 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mcdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6840 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6601 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6619 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_3745 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6337 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6355 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6841 ) - ); - LUT5 #( - .INIT ( 32'hBBBB0B00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6601 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6619 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6337 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6355 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_3744 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mpdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6842 ) - ); - LUT5 #( - .INIT ( 32'h77707070 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6106 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_3747 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5821 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5839 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_6843 ) - ); - LUT5 #( - .INIT ( 32'hBBBB0B00 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_6106 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5821 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/prog_full_i_5839 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_3746 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/flag_gen_inst/gflag_gen_mtdf/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_6844 ) - ); - LUT6 #( - .INIT ( 64'hFFF0FFFF44404444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5450 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5453 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5028 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[1].set_clr_ff_inst/Q_glue_rst_6845 ) - ); - LUT6 #( - .INIT ( 64'hF0FFFFFF80888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/active_ch_dly<1>_0_5450 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.pntr_eql_inst/gstage1.q_dly_0_5453 ), - .I2(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/active_ch_dly<1>_0_5028 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gch_idle.active_ch_valid_dly [1]), - .I5(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/vfifo_idle_gen_inst/gch_flag_gen[2].set_clr_ff_inst/Q_glue_rst_6846 ) - ); - LUT4 #( - .INIT ( 16'hB14E )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [3]) - ); - LUT6 #( - .INIT ( 64'h4444444444404444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/S_VALID_s_ready_i_AND_127_o ) - ); - LUT5 #( - .INIT ( 32'hA5335533 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ) - ); - LUT6 #( - .INIT ( 64'h555555556AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6813 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6816 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT6 #( - .INIT ( 64'h555555556AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mmux_pntr_roll_over11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over_reg ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr21_6825 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [5]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [2]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr24_6828 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_rchd_end_addr2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/pntr_roll_over ) - ); - LUT5 #( - .INIT ( 32'hFFFFAA8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0339_inv ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA88888088 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_chk_6679 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/valid_pkt_r_4042 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mcpf_tvalid ) - ); - LUT5 #( - .INIT ( 32'hAAA2AAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n02981 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_4088 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Madd_packet_cnt_txn_xor<4>11_6621 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/_n0298 ) - ); - LUT5 #( - .INIT ( 32'h00002030 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/S_VALID_s_ready_i_AND_155_o1 ( - .I0(m_axis_tready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ) - ); - LUT5 #( - .INIT ( 32'h222222F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set ( - .I0(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I1(m_axis_tready), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i_glue_set_6853 ) - ); - LUT6 #( - .INIT ( 64'hA5A533CCAAAA33CC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/accept_data ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [1]) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFAAAA88A8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(m_axis_tready), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I5(m_axi_rvalid), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_glue_set_6852 ) - ); - LUT5 #( - .INIT ( 32'hAAEAAA2A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3987 ), - .I1(m_axis_tready), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/m_valid_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I4(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7118 ) - ); - LUT6 #( - .INIT ( 64'hAAAABBABAAAA88A8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/curr_state_4638 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7120 ) - ); - LUT4 #( - .INIT ( 16'h1110 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/Q_glue_set_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ), - .I3(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .O(N40) - ); - LUT4 #( - .INIT ( 16'h1101 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[2].set_clr_ff_inst/Q_glue_set_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2(\NlwRenamedSig_OI_U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_out_reg_slice_inst/storage_data1 [72]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/empty_set_clr/gch_flag_gen[1].set_clr_ff_inst/_n000511_4741 ), - .O(N42) - ); - LUT4 #( - .INIT ( 16'h5444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/S_VALID_s_ready_i_AND_54_o ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFDF7F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_read_fifo1_SW0 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [1]), - .O(N4) - ); - LUT6 #( - .INIT ( 64'hAAAAAAA9FFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [3]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_lut [0]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [3]) - ); - LUT6 #( - .INIT ( 64'hF0F0F0F0FCF0F0A0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy<2>12 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [1]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_A [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_lut[0] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]) - ); - LUT6 #( - .INIT ( 64'hAAAA33CCA5A5CCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [4]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [3]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_cy [2]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [4]) - ); - LUT5 #( - .INIT ( 32'h28887DDD )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/Mmux_tlen_cntr_rs_xor<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/curr_state_4649 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr_reg [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/m_axis_tready_wr_in_i ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/mm2s_in_reg_slice_inst/m_valid_i_4675 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_inst/tlen_cntr [0]) - ); - LUT6 #( - .INIT ( 64'hAAAAAAAAA8888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/addr_ready_6682 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn1_6832 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [1]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_txn ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ) - ); - LUT6 #( - .INIT ( 64'h8888882888888888 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Maccum_ch_arb_cntr_reg_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/curr_state_4743 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [2]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/s_ready_i_4786 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [0]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_arb_cntr_reg [1]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/s_axis_tvalid_arb_rs_in ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result_0 [2]) - ); - LUT5 #( - .INIT ( 32'hFFF8F8F8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/m_valid_i_4330 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s_axis_tready_i_4315 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/end_of_txn_FSM_FFd2_4312 ), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/gno_bkp_on_tready.s2mm_input_rslice/areset_d1_6786 ), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_4316 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/s2mm_awgen_rslice1/m_valid_i_glue_set_6848 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7135 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_1_7136 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7119 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7137 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_rstpot_7120 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_1_7138 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_86_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7139 ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/S_VALID_s_ready_i_AND_104_o ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1_0_2_7140 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_arcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_arcnt[15]_GND_1800_o_add_14_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/rd_data_bcnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Madd_rd_data_bcnt[15]_GND_1800_o_add_12_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_rd_data_wr_i[31]_GND_1143_o_add_8_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [3]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_rd_data_wr_i[31]_GND_1305_o_add_8_OUT_lut<0> ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut<0>_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/rd_data_wr_i [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Madd_gov_err_flag.wr_pntr_plus1_lut [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/inverted_reset1_INV_0 ( - .I(aresetn), - .O(\U0/xst_axi_vfifo_ctrl/inverted_reset ) - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/empty_i ), - .O(m_axi_arvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/empty_i ), - .O(m_axi_awvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/w_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/empty_i ), - .O(m_axi_wvalid) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/M_VALID1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ), - .O(m_axi_bready) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Mcount_arb_granularity_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/arb_granularity [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/gs2mm/Result [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Mcount_reset_addr_0_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/reset_addr_0_4540 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/Result ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_4541 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_txn_inst/mem_init_done_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Mcount_reset_addr_0_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/reset_addr_0_4781 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/Result ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_4780 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/mem_init_done_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy<5>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/Mcompar_pntr_rchd_end_addr_cy [5]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/pntr_rchd_end_addr ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_packet_cnt_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/packet_cnt [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result<0>1 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Mcount_burst_count_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/burst_count [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/Result [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_4803 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/garb/ch_req_rgslice/areset_d1_inv ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut<5>1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [31]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/Mcompar_gptr_mcdf.gch_idle.msb_eql_lut [5]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15 ( - .A0(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_7141 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/Mshreg_wr_rst_reg_15_7141 ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_7142 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3870 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7143 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7143 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7144 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3 ( - .A0(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A1(NlwRenamedSig_OI_m_axi_aruser[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_7145 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/Mshreg_gnstage1.q_dly_3_7145 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_7146 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7147 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7147 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7148 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1[0] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7149 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/Mshreg_active_ch_dly_4_7149 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7150 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4 ( - .A0(NlwRenamedSig_OI_m_axi_aruser[0]), - .A1(NlwRenamedSig_OI_m_axis_tstrb[0]), - .A2(NlwRenamedSig_OI_m_axi_aruser[0]), - .A3(NlwRenamedSig_OI_m_axi_aruser[0]), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .CLK(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/s2mm_reg_slice_inst/storage_data1_0_3770 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7151 ), - .Q15(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_Q15_UNCONNECTED ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/Mshreg_active_ch_dly_4_7151 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7152 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(NlwRenamedSig_OI_m_axis_tstrb[0]), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_7153 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift1_7153 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_7154 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift2_7154 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7155 ) - ); - FDRE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7155 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7156 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_31_7146 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift3_7155 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_7157 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly_311_7157 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/trans_dly_inst/gnstage1.q_dly<3>_0_4210 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7152 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7156 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7158 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7158 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6601 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7150 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7156 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7159 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7159 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_6337 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_41_7144 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7156 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7160 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly_411_7160 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/active_ch_dly<4>_0_6088 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_41_7148 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15_shift4_7156 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7161 ) - ); - FDRE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly_411_7161 ), - .R(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/active_ch_dly<4>_0_5821 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(NlwRenamedSig_OI_m_axi_aruser[0]), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_7162 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift1_7162 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_7163 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift2_7163 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_7164 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift3_7164 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_7165 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift4_7165 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_7166 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift5_7166 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_7167 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift6_7167 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_7168 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift7_7168 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_7169 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift8_7169 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_7170 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift9_7170 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_7171 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift10_7171 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_7172 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift11_7172 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_7173 ) - ); - FDPE \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift12_7173 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_7174 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511 ( - .I0(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_151_7142 ), - .I1(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb_shift13_7174 ), - .O(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_7175 ) - ); - FDPE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_15 ( - .C(aclk), - .CE(NlwRenamedSig_OI_m_axis_tstrb[0]), - .D(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg_1511_7175 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) -, - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.rdp_dly_inst/gstage1.q_dly [15]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gch_idle.wrp_dly_inst/gstage1.q_dly [15]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_rd_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<16>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_depth_minus_rd_m_wr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [0]}), - .A({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<37>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ALUMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<0>_UNCONNECTED -}), - .P({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_P<42>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<41>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<40>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<39>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<32>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF }), - .PCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<4>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }), - .PCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<47>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<46>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<45>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_minus_rd/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<0>_UNCONNECTED -}), - .OPMODE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_pf_dly [0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/wr_pntr_pf_dly [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<6>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<0>_UNCONNECTED -}), - .ACIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_minus_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - DSP48E #( - .ACASCREG ( 0 ), - .ALUMODEREG ( 0 ), - .AREG ( 0 ), - .AUTORESET_PATTERN_DETECT ( "FALSE" ), - .AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ), - .A_INPUT ( "DIRECT" ), - .BCASCREG ( 0 ), - .BREG ( 0 ), - .B_INPUT ( "DIRECT" ), - .CARRYINREG ( 0 ), - .CARRYINSELREG ( 0 ), - .CREG ( 0 ), - .MASK ( 48'h3FFFFFFFFFFF ), - .MREG ( 0 ), - .MULTCARRYINREG ( 0 ), - .OPMODEREG ( 0 ), - .PATTERN ( 48'h000000000000 ), - .PREG ( 1 ), - .SEL_MASK ( "MASK" ), - .SEL_PATTERN ( "PATTERN" ), - .SEL_ROUNDING_MASK ( "SEL_MASK" ), - .SIM_MODE ( "SAFE" ), - .USE_MULT ( "NONE" ), - .USE_PATTERN_DETECT ( "NO_PATDET" ), - .USE_SIMD ( "ONE48" )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive ( - .MULTSIGNOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_MULTSIGNOUT_UNCONNECTED ) -, - .CEP -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ), - .CARRYCASCOUT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYCASCOUT_UNCONNECTED ) -, - .CLK(aclk), - .CARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYCASCIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTP(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .PATTERNBDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNBDETECT_UNCONNECTED ) -, - .RSTC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEC(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .MULTSIGNIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEB2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTCTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CECARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .UNDERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_UNDERFLOW_UNCONNECTED ) -, - .PATTERNDETECT -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PATTERNDETECT_UNCONNECTED ) -, - .RSTALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTALLCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .CEALUMODE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEA1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .RSTB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEMULTCARRYIN(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) -, - .OVERFLOW -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_OVERFLOW_UNCONNECTED ) -, - .CECTRL(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CEM(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ), - .CARRYINSEL({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .ACOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_ACOUT<5>_UNCONNECTED -, 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.C({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcdf_inst/mcf_dfl_wr_inst/gptr_mcdf.gwr_data_1.mcdf_pf_gen_inst/channel_depth_dly [9], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], -NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0], NlwRenamedSig_OI_m_axi_aruser[0]}), - .CARRYOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_CARRYOUT<0>_UNCONNECTED -}), - .BCIN({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .B({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/rd_pntr_minus_wr_pntr [0]}), - .BCOUT({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_BCOUT<8>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/S [0]}), - .A({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }), - .PCOUT({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<44>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<43>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<42>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<38>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<37>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<36>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<35>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<34>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_a_b_nogrowth.i_xbip_addsub/addsub_usecase.i_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive_PCOUT<33>_UNCONNECTED -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT }) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/C_OUT ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/gmcpf_pf_gen.mcpf_pf_gen_inst/ch_dpth_rd_wr/xst_addsub/xbip_addsub.i_ADDF ) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - - ); - LUT6 #( - .INIT ( 64'h9666999966669666 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_G ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N3 ) - ); - LUT6 #( - .INIT ( 64'h9999669996996696 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_F ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N2 ) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N2 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N3 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - LUT5 #( - .INIT ( 32'h02FDFD02 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'h00000000C4C0C0C0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'h0990000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_987 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_988 ) - - ); - LUT6 #( - .INIT ( 64'h222B222B2BBB222B )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT5 #( - .INIT ( 32'h69669969 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hFF2FFF2FFFFFFF2F )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_985 ) - - ); - LUT6 #( - .INIT ( 64'h0990099000000990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_984 ) - - ); - LUT6 #( - .INIT ( 64'h9996999696669996 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - LUT5 #( - .INIT ( 32'h45440444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_971 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_972 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_989 ) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_989 ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/prog_full_i ) - ); - LUT5 #( - .INIT ( 32'h4F440F04 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_988 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_986 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_987 ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF4F44 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_986 ) - - ); - LUT6 #( - .INIT ( 64'hEEEEEEECAAAAAAA0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_984 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_985 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_982 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_983 ) - - ); - LUT5 #( - .INIT ( 32'h82410000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_982 ) - - ); - LUT6 #( - .INIT ( 64'h22F222F2FFFF22F2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_981 ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_960 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_914 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_912 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_972 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_971 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_962 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_900 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_960 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_958 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_956 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) -, - .CLR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_946 ) - - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [0], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/tid_dly_inst/gnstage1.q_dly<1>_0_4071 }), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [1]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [3]}), - .DID({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0] -}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0] -}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0] -}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0] -}), - .DOA({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0] -}), - .DOB({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2] -}), - .DOC({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4] -}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED -}) - ); - RAM32X1D #( - .INIT ( 32'h00000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .A0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .A1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .A2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .A3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .A4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [5]), - .DPRA0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) -, - .DPRA1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .DPRA2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .DPRA3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .DPRA4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .SPO -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ) -, - .DPO -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_to_mcpf_payload [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) -, - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_payload [6]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_915 ) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_915 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_913 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_914 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_911 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_912 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_910 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_904 ) - - ); - FDP - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_909 ) - ); - FDP - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_907 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[1] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_904 ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_905 ) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/argen_inst/ar_mpf_inst/ar_fifo_inst/fifo_gen/N1 ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> -}), - .ECCPARITY({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1320 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1320 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1317 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1317 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [29]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [30]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3936 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3937 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_13 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [9]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_13 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f714 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_13 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_414 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f714 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [8]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_1279 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_1274 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f713 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_613_1279 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_527_1274 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_12 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_1268 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_1263 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f713 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_526_1268 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_413_1263 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [7]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_1257 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_1252 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_612_1257 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_525_1252 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_1246 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_1241 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_524_1246 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412_1241 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [6]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1235 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1230 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1235 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1230 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1224 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1219 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1224 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1219 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [5]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1213 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1208 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1213 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1208 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1202 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1197 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1202 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1197 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [4]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1191 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1186 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1191 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1186 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1180 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1175 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1180 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1175 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [3]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1169 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1164 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1169 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1164 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1158 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1153 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1158 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1153 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [2]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1147 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1142 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1147 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1142 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1136 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1131 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1136 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1131 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [1]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1125 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1120 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1125 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1120 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1114 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1109 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1114 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1109 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [14]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [13]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [12]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [11]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [10]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1088 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1077 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_rd_data_i [0]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1087 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1082 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1088 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1087 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1082 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1075 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1070 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1077 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1075 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1070 ) - - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [12]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPBDOP<0>_UNCONNECTED -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [11]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<10>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [10]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "UPPER" ), - .RAM_EXTENSION_B ( "UPPER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOBDO<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_T_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "LOWER" ), - .RAM_EXTENSION_B ( "LOWER" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 1 ), - .READ_WIDTH_B ( 1 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 1 ), - .WRITE_WIDTH_B ( 1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelata_tmp ) -, - .CASCADEOUTB -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/cascadelatb_tmp ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) -, - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) -, - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]}), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1]}), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [9]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<14>_UNCONNECTED -, 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOBDO<0>_UNCONNECTED -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/SDP.CASCADED_PRIM36.ram_B_DOPADOP<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ 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-\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "TDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 9 ), - .READ_WIDTH_B ( 9 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 9 ), - .WRITE_WIDTH_B ( 9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram ( - .CASCADEINA(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEINB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .ENBWREN -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .REGCEAREGCE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMARSTRAM -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTRAMB(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .RSTREGB(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ), - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [23], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [21], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [19], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [18], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [17], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [15], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [13], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .ADDRBWRADDR({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIADI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [6], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [5], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [4], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [3], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [2], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [1], NlwRenamedSig_OI_m_axi_aruser[0]}), - .DIBDI({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DIPADIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [8]}), - .DIPBDIP({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }), - .DOADO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOADO<0>_UNCONNECTED -}), - .DOBDO({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<31>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<30>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<29>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<28>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<27>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<26>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<25>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<24>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<23>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<22>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<21>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<20>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<19>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<18>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<17>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<16>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<15>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<14>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<13>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<12>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<11>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<10>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<9>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOBDO<8>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_DOPBDOP<1>_UNCONNECTED -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> -}), - .ECCPARITY({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_ECCPARITY<0>_UNCONNECTED -}), - .RDADDRECC({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<8>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0], NlwRenamedSig_OI_m_axis_tstrb[0]}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR }) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out33 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1718 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_enb ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out32 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31_1718 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out31 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out3 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out23 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1715 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.ram_ena ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out22 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21_1715 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out21 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]), - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/out2 ) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [25]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [26]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [27]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/storage_data1 [28]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_wr_inst/mcf2awgen_reg_slice_inst/m_valid_i_3833 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array [7]) - ); - LUT5 #( - .INIT ( 32'h00010000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<0>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [0]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [1]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [2]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [3]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [8]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<9>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [9]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<10>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [10]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<11>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [11]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<12>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [12]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<13>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [13]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<14>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [14]) - ); - LUT5 #( - .INIT ( 32'h80000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<15>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [15]) - ); - LUT5 #( - .INIT ( 32'h00100000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [4]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [5]) - ); - LUT5 #( - .INIT ( 32'h00400000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [6]) - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/Mmux_ENOUT<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/enb_array [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [13]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [14]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [15]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/m_valid_i_3834 ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/mcf_inst/mcf_dfl_rd_inst/mcf2awgen_reg_slice_inst/storage_data1 [16]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [9]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f712 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_412 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f712 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [8]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1677 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1672 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_611_1677 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_523_1672 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_10 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1666 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1661 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f711 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_522_1666 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<8> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<8> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<8> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<8> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_411_1661 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [7]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1655 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1650 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_610_1655 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_521_1650 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_9 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1644 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1639 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f710 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_520_1644 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<7> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<7> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<7> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<7> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_410_1639 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [6]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1633 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1628 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_69_1633 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_519_1628 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1622 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1617 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f79 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_518_1622 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<6> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<6> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<6> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<6> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_49_1617 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [5]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1611 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1606 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_68_1611 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_517_1606 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1600 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1595 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f78 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_516_1600 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<5> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<5> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<5> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<5> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_48_1595 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [4]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1589 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1584 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_67_1589 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_515_1584 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1578 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1573 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f77 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_514_1578 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<4> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<4> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<4> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<4> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_47_1573 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [3]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1567 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1562 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_66_1567 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_513_1562 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1556 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1551 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f76 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_512_1556 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<3> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<3> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<3> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<3> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_46_1551 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [2]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1545 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1540 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f75 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_65_1545 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_511_1540 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1534 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1529 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f75 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_510_1534 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<2> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<2> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<2> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<2> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_45_1529 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [1]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1523 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1518 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f74 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_64_1523 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_59_1518 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1512 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1507 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f74 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_58_1512 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<1> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<1> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<1> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<1> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_44_1507 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [12]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f73 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_43 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f73 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [11]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f72 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_42 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f72 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [10]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f71 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_41 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f71 ) - - ); - MUXF8 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_2_f8 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1492 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1481 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [3]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_rd_data_i [0]) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1491 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1486 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_f7_1492 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_6_1491 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_51_1486 ) - - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1479 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_3_f7_1481 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_1479 ) - - ); - LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.ram_doutb<0> ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.ram_doutb<0> ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.ram_doutb<0> ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.ram_doutb<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_4_1474 ) - - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/bram_inst/bmg/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<0>11_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<5>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hDFFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>111 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_2007 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ) - - ); - LUT6 #( - .INIT ( 64'h4444444400004000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2041 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ) - - ); - LUT5 #( - .INIT ( 32'h45440444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2051 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2052 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2066 ) - - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2066 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/prog_full_i ) - ); - LUT6 #( - .INIT ( 64'h0000000080000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N01 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8>_SW0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N01 ) - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<8>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<7>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<7> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_195_o_add_0_OUT_xor<6>11_2063 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<6> ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h5515 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2005 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<8>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<7>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<7> ) - - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<3>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>111 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<6>11_2062 ) - - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<5>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_182_o_add_0_OUT_xor<4>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<4> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<0>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<2>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mm2s_to_tdf_tvalid ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1901 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1899 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT6 #( - .INIT ( 64'hDDD0FDF0D0D0F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) - - ); - LUT6 #( - .INIT ( 64'h003A303A00303030 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mcpf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4193 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<7> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_195_o_add_0_OUT<8> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2052 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2051 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_7 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_8 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_9 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2041 ) -, - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_2037 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_2038 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_2033 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_2034 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_2029 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_2030 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_2025 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_2026 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_2021 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_2022 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_2017 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_2018 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_2013 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_2014 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_2006 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_2009 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_2010 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<9> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_2006 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_2007 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2005 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2003 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2001 ) - - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<7> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_182_o_add_0_OUT<8> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[0] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[1] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[2] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[3] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[4] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[5] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[6] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[7] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[8] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[9] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[10] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[11] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[12] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[13] ) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_dout[14] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_1902 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_1902 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1900 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1901 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1898 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1899 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_1892 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1897 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1895 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_1892 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1893 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1891 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_1890 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_1881 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1888 ) - - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N1 ) - ); - VCC \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/N0 ) - ); - RAMB18E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 18'h00000 ), - .INIT_B ( 18'h00000 ), - .INIT_FILE ( "NONE" ), - .RAM_MODE ( "SDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 36 ), - .READ_WIDTH_B ( 0 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 18'h00000 ), - .SRVAL_B ( 18'h00000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 0 ), - .WRITE_WIDTH_B ( 36 )) - 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9] -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8] -}), - .DOPADOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPADOP<0>_UNCONNECTED -}), - .DOPBDOP({ -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_DOPBDOP<0>_UNCONNECTED -}), - .WEA({ -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }) - ); - GND - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tdest_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - - ); - INV \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/rd_pntr_wr_inv_pad<6:1><0>1_INV_0 ( - .I -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_2181 ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_rstpot_2181 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'hA6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[5]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'hF078F0F0F0F0F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hC6CCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[5]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'hA6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[5]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'hF078F0F0F0F0F0F0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hC6CCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAEEAEAAAA22A2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I3(m_axi_bvalid), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0_2180 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_2179 ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_2131 ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ) - - ); - LUT6 #( - .INIT ( 64'h0090000000000090 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2174 ) - - ); - LUT5 #( - .INIT ( 32'h45440444 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2160 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2161 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2178 ) - - ); - LUT6 #( - .INIT ( 64'h00C400C000C000C0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(m_axi_bvalid), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2153 ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ) - - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0_rstpot_2179 ) -, - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_dout ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_2178 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/prog_full_i ) - ); - LUT6 #( - .INIT ( 64'h32222222BAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2177 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2176 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2177 ) - - ); - LUT5 #( - .INIT ( 32'h90090000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I4(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2176 ) - - ); - LUT6 #( - .INIT ( 64'h54444444DCCCCCCC )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_2172 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2174 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_2173 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb2_2173 ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1_2172 ) - - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp03 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_2169 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_2170 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - LUT6 #( - .INIT ( 64'h8421000000008421 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp02_2170 ) - ); - LUT6 #( - .INIT ( 64'h9009000000009009 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp01_2169 ) - ); - LUT6 #( - .INIT ( 64'h0000000008000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o<5>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[5]_PWR_27_o_equal_7_o ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I2(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I3(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_bvalid), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2129 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) -, - .I3(m_axi_bvalid), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2106 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2104 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ), - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_to_mctf_tvalid ), - .I1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) -, - .O(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[5]_GND_30_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2161 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2160 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_2153 ) -, - .S(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<0>_2149 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<1>_2150 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<1>_2145 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<2>_2146 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<2>_2141 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<3>_2142 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<3>_2137 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<4>_2138 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ) -, - .DI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) -, - .S -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_2130 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<4>_2133 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<5>_2134 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<5> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_cy<5>_2130 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT_lut<6>_2131 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[6]_rd_pntr_wr_inv_pad[6]_add_2_OUT<6> ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2129 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2127 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2125 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[5]_GND_21_o_add_0_OUT<5> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2107 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2107 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2105 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2106 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2103 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2104 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2097 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2102 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2100 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2097 ), - .Q(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2098 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2096 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2095 ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2073 ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2093 ) - - ); - RAM64X1D #( - .INIT ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM ( - .A0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) -, - .A1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) -, - .A2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) -, - .A3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) -, - .A4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) -, - .A5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) -, - .D(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_id_r_0_4040 ), - .DPRA0 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .DPRA1 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .DPRA2 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .DPRA3 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .DPRA4 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .DPRA5 -(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .SPO -(\NLW_U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_SPO_UNCONNECTED ) -, - .DPO(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0010 ) - ); - GND \U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/gvfifo_top/tid_fifo_inst/fifo_gen/N1 ) - ); - LUT6 #( - .INIT ( 64'h9666999966669666 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_G ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N3 ) - ); - LUT6 #( - .INIT ( 64'h9999669996996696 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_F ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N2 ) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N2 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N3 ), - .S -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2421 ) - ); - LUT5 #( - .INIT ( 32'h02FDFD02 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'h00000000C4C0C0C0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(m_axi_awready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'h2184000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2426 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2427 ) - ); - LUT6 #( - .INIT ( 64'h0A2B0A2B2BAF0A2B )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT5 #( - .INIT ( 32'h69669969 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hDFFFDDFFDFDFDDDD )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2424 ) - - ); - LUT6 #( - .INIT ( 64'h0000C431C4310000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2423 ) - - ); - LUT6 #( - .INIT ( 64'hA596A596965AA596 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]) - ); - LUT5 #( - .INIT ( 32'h4F440F04 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2427 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2425 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2426 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF7350 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2425 ) - ); - LUT6 #( - .INIT ( 64'hEEEEEEECAAAAAAA0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2423 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2424 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2420 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h77335500F7F3F5F0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2421 ), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2422 ) - - ); - LUT5 #( - .INIT ( 32'h82410000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2420 ) - - ); - LUT6 #( - .INIT ( 64'h00AAF0FACCEEFCFE )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2419 ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Mmux_prog_full_i_GND_34_o_MUX_55_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) - - ); - LUT4 #( - .INIT ( 16'hF6F0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ), - .I2(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ) - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I2(m_axi_awready), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I3(m_axi_awready), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_awready), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2396 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I3(m_axi_awready), - .O -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) -, - .I3(m_axi_awready), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2282 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2280 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ), - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/m_valid_i_6860 ), - .I1(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) -, - .O(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2410 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2409 ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/prog_full_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2398 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2268 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2396 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2394 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2392 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2382 ) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [8], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [7]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [10], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [9]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [12], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [11]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [13]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [14], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [13]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [16], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [15]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11], 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [17]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [20], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [19]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [22], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [21]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], 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-\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [24], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [23]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [26], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [25]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [28], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [27]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [42], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [41]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [44], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [43]}), - .DIC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/mcf_inst/mcf_dfl_wr_inst/s2mm_reg_slice_inst/storage_data1 [0]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , 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.DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]}), - .DOC({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOC<1>_UNCONNECTED -, \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [30], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [29]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [32], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [31]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [34], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [33]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [36], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [35]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [38], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [37]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [40], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/aw_rslice1/storage_data1 [39]}), - .DID({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]}), - .DOB({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]}), - .DOC({\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35], -\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED -}) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(m_axi_awlen[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(m_axi_awlen[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(m_axi_awlen[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(m_axi_awlen[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(m_axi_awlen[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(m_axi_awlen[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(m_axi_awlen[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]), - .Q(m_axi_awlen[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]), - .Q(m_axi_awaddr[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]), - .Q(m_axi_awaddr[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]), - .Q(m_axi_awaddr[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]), - .Q(m_axi_awaddr[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]), - .Q(m_axi_awaddr[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]), - .Q(m_axi_awaddr[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]), - .Q(m_axi_awaddr[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]), - .Q(m_axi_awaddr[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]), - .Q(m_axi_awaddr[8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]), - .Q(m_axi_awaddr[9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]), - .Q(m_axi_awaddr[10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]), - .Q(m_axi_awaddr[11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]), - .Q(m_axi_awaddr[12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]), - .Q(m_axi_awaddr[13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]), - .Q(m_axi_awaddr[14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]), - .Q(m_axi_awaddr[15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]), - .Q(m_axi_awaddr[16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]), - .Q(m_axi_awaddr[17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]), - .Q(m_axi_awaddr[18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]), - .Q(m_axi_awaddr[19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]), - .Q(m_axi_awaddr[20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]), - .Q(m_axi_awaddr[21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]), - .Q(m_axi_awaddr[22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]), - .Q(m_axi_awaddr[23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]), - .Q(m_axi_awaddr[24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]), - .Q(m_axi_awaddr[25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]), - .Q(m_axi_awaddr[26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]), - .Q(m_axi_awaddr[27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]), - .Q(m_axi_awaddr[28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]), - .Q(m_axi_awaddr[29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]), - .Q(m_axi_awaddr[30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]), - .Q(m_axi_awaddr[31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]), - .Q(m_axi_awid[0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2283 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2283 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2281 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2282 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2279 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2280 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2278 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2272 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2277 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2275 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2272 ), - .Q(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2273 ) - ); - GND \U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/aw_fifo_inst/fifo_gen/N1 ) - ); - LUT6 #( - .INIT ( 64'h9666999966669666 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_G ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N3 ) - ); - LUT6 #( - .INIT ( 64'h9999669996996696 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11_F ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N2 ) - ); - MUXF7 - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N2 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N3 ), - .S -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) - - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rd_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]) - ); - INV \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2671 ) - ); - LUT5 #( - .INIT ( 32'h02FDFD02 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[3]_GND_30_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[3]_GND_21_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) - - ); - LUT6 #( - .INIT ( 64'h00000000C4C0C0C0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>1 ( - .I0(m_axi_arready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<0> ) - - ); - LUT6 #( - .INIT ( 64'h2184000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2676 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2677 ) - ); - LUT6 #( - .INIT ( 64'h0A2B0A2B2BAF0A2B )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) - - ); - LUT5 #( - .INIT ( 32'h69669969 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_cy<3>1 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hDFFFDDFFDFDFDDDD )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2674 ) - - ); - LUT6 #( - .INIT ( 64'h0000C431C4310000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2673 ) - - ); - LUT6 #( - .INIT ( 64'hA596A596965AA596 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) - - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [4]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [5]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [6]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [7]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [8]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [9]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [10]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [11]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [12]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [13]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [14]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [15]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [16]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [17]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [18]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [19]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [20]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [21]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [22]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [23]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [36]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [37]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [38]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [39]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [40]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]) - ); - LUT5 #( - .INIT ( 32'h4F440F04 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb6 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_2677 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2675 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT4 #( - .INIT ( 16'h8421 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb4_2676 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF7350 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb3_2675 ) - ); - LUT6 #( - .INIT ( 64'hEEEEEEECAAAAAAA0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o6 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o3_2673 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o5_2674 ) -, - .I4 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2670 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) - - ); - LUT6 #( - .INIT ( 64'h77335500F7F3F5F0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3_1_2671 ), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o4_2672 ) - - ); - LUT5 #( - .INIT ( 32'h82410000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o2_2670 ) - - ); - LUT6 #( - .INIT ( 64'h00AAF0FACCEEFCFE )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I3(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I4(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I5(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o1_2669 ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o<3>1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'h0400 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Mmux_prog_full_i_GND_34_o_MUX_55_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) - - ); - LUT4 #( - .INIT ( 16'hF6F0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ), - .I2(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ), - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[3]_GND_34_o_equal_7_o ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ) - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I2(m_axi_arready), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I3(m_axi_arready), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_arready), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ), - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2646 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I3(m_axi_arready), - .O -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) - - ); - LUT4 #( - .INIT ( 16'h4404 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I1 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) -, - .I3(m_axi_arready), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2532 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2530 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ), - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/vld_dly_inst/gnstage1.q_dly<1>_0_4070 ), - .I1(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) -, - .O(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[3]_GND_30_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_2660 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_2659 ) - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/_n0048_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_GND_34_o_MUX_55_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/prog_full_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<1> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<2> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<3> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT<4> ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2648 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2518 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_2646 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_5_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_2644 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_2642 ) - - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[3]_GND_21_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ), - .CLR(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_3_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2632 ) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [7], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [6]}), - .DIB({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [9], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [8]}), - .DIC({\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [11], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/mctf_inst/gbmg_do.bram_dout_dly_inst/gstage1.q_dly [10]}), - .DID({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], 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-\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [17], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [16]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [19], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [18]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [21], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [20]}), - .DID({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], 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-\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [25], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [24]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [27], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [26]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [29], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [28]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_DOD<0>_UNCONNECTED -}) - ); - RAM32M #( - .INIT_A ( 64'h0000000000000000 ), - .INIT_B ( 64'h0000000000000000 ), - .INIT_C ( 64'h0000000000000000 ), - .INIT_D ( 64'h0000000000000000 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6 ( - .WCLK(aclk), - .WE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .DIA({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [23], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [22]}), - .DIB({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [25], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [24]}), - .DIC({\U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [27], \U0/xst_axi_vfifo_ctrl/m_axi_araddr_i [26]}), - .DID({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 }), - .ADDRA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [0]}), - .ADDRD({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 , -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]}), - .DOA({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [31], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [30]}), - .DOB({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [33], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [32]}), - .DOC({\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [35], -\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014 [34]}), - .DOD({ -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_DOD<0>_UNCONNECTED -}) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [0]), - .Q(m_axi_arlen[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [1]), - .Q(m_axi_arlen[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [2]), - .Q(m_axi_arlen[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [3]), - .Q(m_axi_arlen[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [4]), - .Q(m_axi_arlen[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [5]), - .Q(m_axi_arlen[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [6]), - .Q(m_axi_arlen[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [7]), - .Q(m_axi_arlen[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [8]), - .Q(m_axi_araddr[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [9]), - .Q(m_axi_araddr[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [10]), - .Q(m_axi_araddr[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [11]), - .Q(m_axi_araddr[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [12]), - .Q(m_axi_araddr[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [13]), - .Q(m_axi_araddr[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [14]), - .Q(m_axi_araddr[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [15]), - .Q(m_axi_araddr[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [16]), - .Q(m_axi_araddr[8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [17]), - .Q(m_axi_araddr[9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [18]), - .Q(m_axi_araddr[10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [19]), - .Q(m_axi_araddr[11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [20]), - .Q(m_axi_araddr[12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [21]), - .Q(m_axi_araddr[13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [22]), - .Q(m_axi_araddr[14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [23]), - .Q(m_axi_araddr[15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [24]), - .Q(m_axi_araddr[16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [25]), - .Q(m_axi_araddr[17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [26]), - .Q(m_axi_araddr[18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [27]), - .Q(m_axi_araddr[19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [28]), - .Q(m_axi_araddr[20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [29]), - .Q(m_axi_araddr[21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [30]), - .Q(m_axi_araddr[22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [31]), - .Q(m_axi_araddr[23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [32]), - .Q(m_axi_araddr[24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [33]), - .Q(m_axi_araddr[25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [34]), - .Q(m_axi_araddr[26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [35]), - .Q(m_axi_araddr[27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [36]), - .Q(m_axi_araddr[28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [37]), - .Q(m_axi_araddr[29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [38]), - .Q(m_axi_araddr[30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [39]), - .Q(m_axi_araddr[31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0019_inv ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i [40]), - .Q(m_axi_arid[0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2533 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2533 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2531 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2532 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2529 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2530 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2528 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2522 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2527 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2525 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2522 ), - .Q(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2523 ) - ); - GND \U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/ar_fifo_inst/fifo_gen/N1 ) - ); - INV \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/wr_pntr<0>_inv1_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]) - ); - INV - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<0>11_INV_0 ( - .I(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<1> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<2> ) - - ); - LUT4 #( - .INIT ( 16'h9AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'hAAAA6AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<4> ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF7FFFFFFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_3148 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ) - - ); - LUT6 #( - .INIT ( 64'h00C400C000C000C0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1 ( - .I0(m_axi_wready), - .I1(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I5 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_3182 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2> ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ) - - ); - LUT5 #( - .INIT ( 32'h00B200F0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3193 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3192 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ), - .I4 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_3207 ) - - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h0990 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/prog_full_i_rstpot_3207 ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/prog_full_i ) - ); - LUT6 #( - .INIT ( 64'h0000000080000000 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8> ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]), - .I4 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N01 ), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o ) - - ); - LUT4 #( - .INIT ( 16'hFDFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr[8]_PWR_40_o_equal_7_o<8>_SW0 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N01 ) - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'hA6 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<7> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Madd_gcc0.gc0.count[8]_GND_301_o_add_0_OUT_xor<6>11_3204 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<6> ) - - ); - LUT3 #( - .INIT ( 8'hAE )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 ( - .I0 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I2(m_axi_wready), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]) - ); - LUT4 #( - .INIT ( 16'h55D5 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I3(m_axi_wready), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) - - ); - LUT4 #( - .INIT ( 16'h2333 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT11 ( - .I0(m_axi_wready), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ) - ); - LUT4 #( - .INIT ( 16'h8E8A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3146 ), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .I3(m_axi_wready), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) - - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<1>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<1> ) - - ); - LUT4 #( - .INIT ( 16'hAA6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<8>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<8> ) - - ); - LUT3 #( - .INIT ( 8'h9A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<7>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) -, - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<7> ) - - ); - LUT3 #( - .INIT ( 8'h6A )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<2>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<2> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I1 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<6> ) - - ); - LUT4 #( - .INIT ( 16'h6AAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<3>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<3> ) - - ); - LUT6 #( - .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>111 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<6>11_3203 ) - - ); - LUT6 #( - .INIT ( 64'h6AAAAAAAAAAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<5>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<5> ) - - ); - LUT5 #( - .INIT ( 32'h6AAAAAAA )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Madd_gc0.count[8]_GND_288_o_add_0_OUT_xor<4>11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<4> ) - - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<0>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]) - ); - LUT2 #( - .INIT ( 4'h9 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<4>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<1>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<2>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]) - ); - LUT4 #( - .INIT ( 16'h9009 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1<3>1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]) - ); - LUT4 #( - .INIT ( 16'h2300 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv1 ( - .I0(m_axi_wready), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ), - .I2 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) -, - .I3 -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) -, - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2992 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2990 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 ( - .I0(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ) - ); - LUT6 #( - .INIT ( 64'hDDD0FDF0D0D0F0F0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) -, - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) - - ); - LUT6 #( - .INIT ( 64'h003A303A00303030 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ), - .I2(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .I3(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .I4(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ), - .I5(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ) - ); - LUT2 #( - .INIT ( 4'h2 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 ( - .I0(\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/m_valid_i_3604 ), - .I1(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count[8]_GND_301_o_add_0_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_wr_en_i_3193 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/ram_rd_en_i_3192 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [1]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [2]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_3 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [3]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_4 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [4]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_5 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [5]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_6 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [6]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_7 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [7]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_8 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [8]) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad_9 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/diff_pntr_pad [9]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0> ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .DI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad<0>_mand1_3182 ) -, - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus1 [0]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<1> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<0>_3178 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<1>_3179 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<1> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [1]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<2> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<1>_3174 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<2>_3175 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<2> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [2]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<3> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<2>_3170 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<3>_3171 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<3> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [3]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<4> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<3>_3166 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<4>_3167 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<4> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [4]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<5> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<4>_3162 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<5>_3163 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<5> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [5]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<6> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<5>_3158 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<6>_3159 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<6> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [6]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<7> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<6>_3154 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<7>_3155 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<7> ) - - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count [7]), - .S -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_3147 ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<8> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<7>_3150 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<8>_3151 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<8> ) - - ); - XORCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_xor<9> ( - .CI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_cy<8>_3147 ) -, - .LI -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/Madd_wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT_lut<9>_3148 ) -, - .O -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/wr_pntr_plus1_pad[9]_rd_pntr_wr_inv_pad[9]_add_2_OUT<9> ) - - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_3146 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/going_empty_fwft_leaving_empty_fwft_OR_8_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/empty_i ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) -, - .Q -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3144 ) - - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/next_fwft_state [0]), - .Q -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_3142 ) - - ); - FDPE #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [0]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<1> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<2> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<3> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<4> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<5> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<6> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<7> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[8]_GND_288_o_add_0_OUT<8> ) -, - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [1]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [2]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [3]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [4]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [5]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [6]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [7]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7]) - ); - FDCE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .CLR(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count [8]), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.carrynet [3]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.carrynet [2]) -, - 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\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.carrynet [3]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ), - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [0]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [1]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) - ); - MUXCY - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms ( - .CI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [2]) -, - .DI(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .S(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]), - .O(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.carrynet [3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [0]) -, - .Q(m_axi_wlast) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [1]) -, - .Q(m_axi_wdata[0]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [2]) -, - .Q(m_axi_wdata[1]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [3]) -, - .Q(m_axi_wdata[2]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [4]) -, - .Q(m_axi_wdata[3]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [5]) -, - .Q(m_axi_wdata[4]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [6]) -, - .Q(m_axi_wdata[5]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [7]) -, - .Q(m_axi_wdata[6]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [8]) -, - .Q(m_axi_wdata[7]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [9]) -, - .Q(m_axi_wdata[8]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [10]) -, - .Q(m_axi_wdata[9]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [11]) -, - .Q(m_axi_wdata[10]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [12]) -, - .Q(m_axi_wdata[11]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [13]) -, - .Q(m_axi_wdata[12]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [14]) -, - .Q(m_axi_wdata[13]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [15]) -, - .Q(m_axi_wdata[14]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [16]) -, - .Q(m_axi_wdata[15]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [17]) -, - .Q(m_axi_wdata[16]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [18]) -, - .Q(m_axi_wdata[17]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [19]) -, - .Q(m_axi_wdata[18]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [20]) -, - .Q(m_axi_wdata[19]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [21]) -, - .Q(m_axi_wdata[20]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [22]) -, - .Q(m_axi_wdata[21]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [23]) -, - .Q(m_axi_wdata[22]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [24]) -, - .Q(m_axi_wdata[23]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [25]) -, - .Q(m_axi_wdata[24]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [26]) -, - .Q(m_axi_wdata[25]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [27]) -, - .Q(m_axi_wdata[26]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [28]) -, - .Q(m_axi_wdata[27]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [29]) -, - .Q(m_axi_wdata[28]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [30]) -, - .Q(m_axi_wdata[29]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [31]) -, - .Q(m_axi_wdata[30]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [32]) -, - .Q(m_axi_wdata[31]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [33]) -, - .Q(m_axi_wdata[32]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [34]) -, - .Q(m_axi_wdata[33]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [35]) -, - .Q(m_axi_wdata[34]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [36]) -, - .Q(m_axi_wdata[35]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [37]) -, - .Q(m_axi_wdata[36]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [38]) -, - .Q(m_axi_wdata[37]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [39]) -, - .Q(m_axi_wdata[38]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [40]) -, - .Q(m_axi_wdata[39]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_41 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [41]) -, - .Q(m_axi_wdata[40]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_42 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [42]) -, - .Q(m_axi_wdata[41]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_43 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [43]) -, - .Q(m_axi_wdata[42]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_44 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [44]) -, - .Q(m_axi_wdata[43]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_45 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [45]) -, - .Q(m_axi_wdata[44]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_46 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [46]) -, - .Q(m_axi_wdata[45]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_47 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [47]) -, - .Q(m_axi_wdata[46]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_48 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [48]) -, - .Q(m_axi_wdata[47]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_49 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [49]) -, - .Q(m_axi_wdata[48]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_50 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [50]) -, - .Q(m_axi_wdata[49]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_51 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [51]) -, - .Q(m_axi_wdata[50]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_52 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [52]) -, - .Q(m_axi_wdata[51]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_53 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [53]) -, - .Q(m_axi_wdata[52]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_54 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [54]) -, - .Q(m_axi_wdata[53]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_55 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [55]) -, - .Q(m_axi_wdata[54]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_56 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [56]) -, - .Q(m_axi_wdata[55]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_57 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [57]) -, - .Q(m_axi_wdata[56]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_58 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [58]) -, - .Q(m_axi_wdata[57]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_59 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [59]) -, - .Q(m_axi_wdata[58]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_60 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [60]) -, - .Q(m_axi_wdata[59]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_61 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [61]) -, - .Q(m_axi_wdata[60]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_62 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [62]) -, - .Q(m_axi_wdata[61]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_63 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [63]) -, - .Q(m_axi_wdata[62]) - ); - FDE #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_64 ( - .C(aclk), - .CE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/_n0025_inv ), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/doutb_i [64]) -, - .Q(m_axi_wdata[63]) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2993 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg [1]) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1_2993 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_2991 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_2992 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_2989 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_2990 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3 ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2983 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_GND_12_o_MUX_1_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_2988 ) - ); - FDP \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_GND_12_o_MUX_2_o ), - .PRE(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_2986 ) - ); - FDC #( - .INIT ( 1'b0 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN ( - .C(aclk), - .CLR(\U0/xst_axi_vfifo_ctrl/rstblk/wr_rst_reg[15] ), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3_2983 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_2984 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_2982 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i ( - .C(aclk), - .D(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ), - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2_2981 ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_2972 ) - ); - FDP #( - .INIT ( 1'b1 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i ( - .C(aclk), - .D -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/going_empty_leaving_empty_OR_6_o ) -, - .PRE(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] ), - .Q(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_2979 ) - ); - GND \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/XST_GND ( - .G(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ) - ); - VCC \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/XST_VCC ( - .P(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N0 ) - ); - RAMB36E1 #( - .DOA_REG ( 0 ), - .DOB_REG ( 0 ), - .EN_ECC_READ ( "FALSE" ), - .EN_ECC_WRITE ( "FALSE" ), - .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), - .INIT_A ( 36'h000000000 ), - .INIT_B ( 36'h000000000 ), - .INIT_FILE ( "NONE" ), - .RAM_EXTENSION_A ( "NONE" ), - .RAM_EXTENSION_B ( "NONE" ), - .RAM_MODE ( "SDP" ), - .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ), - .READ_WIDTH_A ( 72 ), - .READ_WIDTH_B ( 0 ), - .RSTREG_PRIORITY_A ( "REGCE" ), - .RSTREG_PRIORITY_B ( "REGCE" ), - .SIM_COLLISION_CHECK ( "ALL" ), - .SIM_DEVICE ( "7SERIES" ), - .SRVAL_A ( 36'h000000000 ), - .SRVAL_B ( 36'h000000000 ), - .WRITE_MODE_A ( "READ_FIRST" ), - .WRITE_MODE_B ( "READ_FIRST" ), - .WRITE_WIDTH_A ( 0 ), - .WRITE_WIDTH_B ( 72 )) - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram ( - .CASCADEINA -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .CASCADEINB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .CASCADEOUTA -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ) -, - .CASCADEOUTB -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ) -, - .CLKARDCLK(aclk), - .CLKBWRCLK(aclk), - .DBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED ) -, - .ENARDEN(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ), - .ENBWREN(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ), - .INJECTDBITERR -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .INJECTSBITERR -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEAREGCE -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .REGCEB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTRAMARSTRAM(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/N1 ), - .RSTRAMB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGARSTREG -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .RSTREGB -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) -, - .SBITERR -(\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED ) -, - .ADDRARDADDR({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rd_pntr_plus1<0>_inv , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .ADDRBWRADDR({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 -, \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [8], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [7], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [6], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [5], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [4], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [3], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [2], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [1], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1 [0], -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, 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-\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [48], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [47], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [46], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [45], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [44], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [43], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [42], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [41], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [40], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [39], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [38], -\U0/xst_axi_vfifo_ctrl/gvfifo_top/awgen_inst/wdata_rslice2/storage_data1 [37], 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-\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<7>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<6>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<5>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<4>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<3>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<2>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<1>_UNCONNECTED -, -\NLW_U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_RDADDRECC<0>_UNCONNECTED -}), - .WEA({ -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -, -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR -}), - .WEBWE({\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , -\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }) - ); - GND - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND ( - .G -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR ) - - ); - VCC - \U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC ( - .P -(\U0/xst_axi_vfifo_ctrl/w_fifo_inst/fifo_gen/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/N0 ) - - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.veo b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.veo deleted file mode 100644 index 32f089ada..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.veo +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2013 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 * -* * -* Rev 1. The AXI Virtual FIFO Controller is a parameterizable number of * -* multi channel FIFO. * -*******************************************************************************/ - -// Interfaces: -// AXI4Stream_MASTER_M_AXIS -// AXI4Stream_SLAVE_S_AXIS -// AXI4_MASTER_M_AXI - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_vfifo_64_0x2000000 your_instance_name ( - .aclk(aclk), // input aclk - .aresetn(aresetn), // input aresetn - .m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid - .m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr - .m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen - .m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize - .m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst - .m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock - .m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache - .m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot - .m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos - .m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion - .m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser - .m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid - .m_axi_awready(m_axi_awready), // input m_axi_awready - .m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb - .m_axi_wlast(m_axi_wlast), // output m_axi_wlast - .m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser - .m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid - .m_axi_wready(m_axi_wready), // input m_axi_wready - .m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid - .m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp - .m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser - .m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid - .m_axi_bready(m_axi_bready), // output m_axi_bready - .m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid - .m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr - .m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen - .m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize - .m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst - .m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock - .m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache - .m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot - .m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos - .m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion - .m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser - .m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid - .m_axi_arready(m_axi_arready), // input m_axi_arready - .m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid - .m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp - .m_axi_rlast(m_axi_rlast), // input m_axi_rlast - .m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser - .m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid - .m_axi_rready(m_axi_rready), // output m_axi_rready - .s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid - .s_axis_tready(s_axis_tready), // output s_axis_tready - .s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata - .s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb - .s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep - .s_axis_tlast(s_axis_tlast), // input s_axis_tlast - .s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid - .s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest - .m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid - .m_axis_tready(m_axis_tready), // input m_axis_tready - .m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata - .m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb - .m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep - .m_axis_tlast(m_axis_tlast), // output m_axis_tlast - .m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid - .m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest - .vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full - .vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full - .vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty - .vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr - .vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr - .vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr - .vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_vfifo_64_0x2000000.v when simulating -// the core, axi_vfifo_64_0x2000000. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.xco b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.xco deleted file mode 100644 index 9bcc2cccc..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.xco +++ /dev/null @@ -1,75 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Fri Jan 18 18:20:30 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:axi_vfifo_ctrl:1.1 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT AXI_Virtual_FIFO_Controller xilinx.com:ip:axi_vfifo_ctrl:1.1 -# END Select -# BEGIN Parameters -CSET ar_weight_ch0=8 -CSET ar_weight_ch1=8 -CSET ar_weight_ch2=8 -CSET ar_weight_ch3=8 -CSET ar_weight_ch4=8 -CSET ar_weight_ch5=8 -CSET ar_weight_ch6=8 -CSET ar_weight_ch7=8 -CSET axi_burst_size=512 -CSET axis_tdata_width=64 -CSET axis_tuser_width=1 -CSET component_name=axi_vfifo_64_0x2000000 -CSET deassert_tready=false -CSET dram_base_addr=02000000 -CSET enable_axis_tid=true -CSET enable_axis_tuser=false -CSET enable_interrupt=true -CSET implementation_type=Burst_Mode -CSET number_of_channel=2 -CSET number_of_page_ch0=4096 -CSET number_of_page_ch1=4096 -CSET number_of_page_ch2=8 -CSET number_of_page_ch3=8 -CSET number_of_page_ch4=8 -CSET number_of_page_ch5=8 -CSET number_of_page_ch6=8 -CSET number_of_page_ch7=8 -CSET s2mm_txn_timeout_value=8 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T22:37:34Z -# END Extra information -GENERATE -# CRC: cae4af68 diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.xise b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.xise deleted file mode 100644 index c242b26d0..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -

- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt deleted file mode 100644 index 2fbc94c40..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt +++ /dev/null @@ -1,189 +0,0 @@ -CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 - - Core name: Xilinx LogiCORE AXI Virtual FIFO Controller - Version: 1.1 - Release: ISE 14.2 / Vivado 2012.2 - Release Date: July 25, 2012 - --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURES HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm - -................................................................................ - - -2. DEVICE SUPPORT - - - 2.1 ISE - - The following device families are supported by the core for this release. - - - All 7 Series devices - Zynq-7000 devices - All Virtex-6 devices - All Spartan-6 devices - - - 2.2 Vivado - - All 7 Series devices - Zynq-7000 devices - -................................................................................ - - -3. NEW FEATURES HISTORY - - - 3.1 ISE - - - First release - - ISE 14.2 software support - - - 3.2 Vivado - - - First release - - 2012.2 software support - -................................................................................ - - -4. RESOLVED ISSUES - - - 4.1 ISE - - - N/A - - - 4.2 Vivado - - - N/A - - -................................................................................ - - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - N/A - - - 5.2 Vivado - - - N/A - - -The most recent information, including known issues, workarounds, and -resolutions for this version is provided in the IP Release Notes User Guide -located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -................................................................................ - - -6. TECHNICAL SUPPORT & FEEDBACK - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -................................................................................ - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support. -04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support. -================================================================================ - -................................................................................ - - -8. LEGAL DISCLAIMER - -(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html deleted file mode 100644 index 7ad3604b5..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html +++ /dev/null @@ -1,200 +0,0 @@ - - -axi_vfifo_ctrl_v1_1_vinfo - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf deleted file mode 100644 index 99f1cfca9..000000000 Binary files a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf and /dev/null differ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf deleted file mode 100755 index 4b89dc81c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf +++ /dev/null @@ -1,56 +0,0 @@ -################################################################################ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - - NET "ACLK" TNM_NET = "ACLK"; - TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ; - -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd deleted file mode 100755 index a67ac44d8..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd +++ /dev/null @@ -1,370 +0,0 @@ --------------------------------------------------------------------------------- --- --- AXI Virtual FIFO Controller Core - core top file for implementation --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: axi_vfifo_64_0x2000000_exdes.vhd --- --- Description: --- This is the VFIFO core wrapper with BUFG instances for clock connections. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library unisim; -use unisim.vcomponents.all; - --------------------------------------------------------------------------------- --- Entity Declaration --------------------------------------------------------------------------------- -entity axi_vfifo_64_0x2000000_exdes is - PORT ( - - -- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC) - S_AXIS_TVALID : IN STD_LOGIC := '0'; - S_AXIS_TREADY : OUT STD_LOGIC := '0'; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TLAST : IN STD_LOGIC := '0'; - S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - - -- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch - M_AXIS_TVALID : OUT STD_LOGIC := '0'; - M_AXIS_TREADY : IN STD_LOGIC := '0'; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1'); - M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TLAST : OUT STD_LOGIC := '0'; - M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Write Address Channel Signals - M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWVALID : OUT STD_LOGIC := '0'; - M_AXI_AWREADY : IN STD_LOGIC := '0'; - - -- Write Data Channel Signals - M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WLAST : OUT STD_LOGIC := '0'; - M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WVALID : OUT STD_LOGIC := '0'; - M_AXI_WREADY : IN STD_LOGIC := '0'; - - -- Write Response Channel Signals - M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BVALID : IN STD_LOGIC := '0'; - M_AXI_BREADY : OUT STD_LOGIC := '1'; - - -- Read Address Channel Signals - M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARVALID : OUT STD_LOGIC := '0'; - M_AXI_ARREADY : IN STD_LOGIC := '0'; - - -- Read Data Channel Signals - M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RLAST : IN STD_LOGIC := '0'; - M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RVALID : IN STD_LOGIC := '0'; - M_AXI_RREADY : OUT STD_LOGIC := '0'; - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Status Signal - VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0'; - - -- Global Signals - ACLK : IN STD_LOGIC := '0'; - ARESETN : IN STD_LOGIC := '0' - ); - -end axi_vfifo_64_0x2000000_exdes; - - - -architecture xilinx of axi_vfifo_64_0x2000000_exdes is - - signal s_aclk_i : std_logic; - - component axi_vfifo_64_0x2000000 is - PORT ( - - -- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC) - S_AXIS_TVALID : IN STD_LOGIC := '0'; - S_AXIS_TREADY : OUT STD_LOGIC := '0'; - S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TLAST : IN STD_LOGIC := '0'; - S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - - -- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch - M_AXIS_TVALID : OUT STD_LOGIC := '0'; - M_AXIS_TREADY : IN STD_LOGIC := '0'; - M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1'); - M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TLAST : OUT STD_LOGIC := '0'; - M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Write Address Channel Signals - M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_AWVALID : OUT STD_LOGIC := '0'; - M_AXI_AWREADY : IN STD_LOGIC := '0'; - - -- Write Data Channel Signals - M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WLAST : OUT STD_LOGIC := '0'; - M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_WVALID : OUT STD_LOGIC := '0'; - M_AXI_WREADY : IN STD_LOGIC := '0'; - - -- Write Response Channel Signals - M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_BVALID : IN STD_LOGIC := '0'; - M_AXI_BREADY : OUT STD_LOGIC := '1'; - - -- Read Address Channel Signals - M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0'); - M_AXI_ARVALID : OUT STD_LOGIC := '0'; - M_AXI_ARREADY : IN STD_LOGIC := '0'; - - -- Read Data Channel Signals - M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RLAST : IN STD_LOGIC := '0'; - M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0'); - M_AXI_RVALID : IN STD_LOGIC := '0'; - M_AXI_RREADY : OUT STD_LOGIC := '0'; - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0'); - VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Status Signal - VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1'); - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0'; - VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0'; - - -- Global Signals - ACLK : IN STD_LOGIC := '0'; - ARESETN : IN STD_LOGIC := '0' - ); - - end component; - - -begin - - s_aclk_buf: bufg - PORT map( - i => ACLK, - o => s_aclk_i - ); - - exdes_inst : axi_vfifo_64_0x2000000 - PORT MAP ( - - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TREADY => S_AXIS_TREADY, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TSTRB => S_AXIS_TSTRB, - S_AXIS_TKEEP => S_AXIS_TKEEP, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TID => S_AXIS_TID, - S_AXIS_TDEST => S_AXIS_TDEST, - - M_AXIS_TVALID => M_AXIS_TVALID, - M_AXIS_TREADY => M_AXIS_TREADY, - M_AXIS_TDATA => M_AXIS_TDATA, - M_AXIS_TSTRB => M_AXIS_TSTRB, - M_AXIS_TKEEP => M_AXIS_TKEEP, - M_AXIS_TLAST => M_AXIS_TLAST, - M_AXIS_TID => M_AXIS_TID, - M_AXIS_TDEST => M_AXIS_TDEST, - - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => M_AXI_AWLOCK, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWUSER => M_AXI_AWUSER, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WUSER => M_AXI_WUSER, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BUSER => M_AXI_BUSER, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => M_AXI_ARLOCK, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARUSER => M_AXI_ARUSER, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RUSER => M_AXI_RUSER, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - - -- External Interface Signals - VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL, - VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY, - VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL, - - -- Status Signal - VFIFO_IDLE => VFIFO_IDLE, - - -- Interrupt Signals - VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR, - VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR, - VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR, - - ACLK => s_aclk_i, - ARESETN => ARESETN - ); - -end xilinx; diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc deleted file mode 100755 index 94c78f7c9..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc +++ /dev/null @@ -1,55 +0,0 @@ -################################################################################ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - -create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ] - -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.bat deleted file mode 100755 index 8a147846e..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.bat +++ /dev/null @@ -1,88 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -copy axi_vfifo_64_0x2000000_exdes.ngc .\results\ - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\axi_vfifo_64_0x2000000.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\axi_vfifo_64_0x2000000_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes - -echo 'Running map' -map axi_vfifo_64_0x2000000_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.sh deleted file mode 100755 index d4114bc59..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -cp axi_vfifo_64_0x2000000_exdes.ngc ./results/ - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../axi_vfifo_64_0x2000000.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/axi_vfifo_64_0x2000000_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes - -echo 'Running map' -map axi_vfifo_64_0x2000000_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.bat deleted file mode 100755 index df8dbab1f..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.bat +++ /dev/null @@ -1,87 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\axi_vfifo_64_0x2000000.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\axi_vfifo_64_0x2000000_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes - -echo 'Running map' -map axi_vfifo_64_0x2000000_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.sh deleted file mode 100755 index 0d11660de..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.sh +++ /dev/null @@ -1,86 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../axi_vfifo_64_0x2000000.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/axi_vfifo_64_0x2000000_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes - -echo 'Running map' -map axi_vfifo_64_0x2000000_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.bat b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.bat deleted file mode 100755 index f6cc67a08..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.bat +++ /dev/null @@ -1,54 +0,0 @@ -rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -rem -rem This file contains confidential and proprietary information -rem of Xilinx, Inc. and is protected under U.S. and -rem international copyright and other intellectual property -rem laws. -rem -rem DISCLAIMER -rem This disclaimer is not a license and does not grant any -rem rights to the materials distributed herewith. Except as -rem otherwise provided in a valid license issued to you by -rem Xilinx, and to the maximum extent permitted by applicable -rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -rem (2) Xilinx shall not be liable (whether in contract or tort, -rem including negligence, or under any other theory of -rem liability) for any loss or damage of any kind or nature -rem related to, arising under or in connection with these -rem materials, including for any direct, or any indirect, -rem special, incidental, or consequential loss or damage -rem (including loss of data, profits, goodwill, or any type of -rem loss or damage suffered as a result of any action brought -rem by a third party) even if such damage or loss was -rem reasonably foreseeable or Xilinx had been advised of the -rem possibility of the same. -rem -rem CRITICAL APPLICATIONS -rem Xilinx products are not designed or intended to be fail- -rem safe, or for use in any application requiring fail-safe -rem performance, such as life-support or safety devices or -rem systems, Class III medical devices, nuclear facilities, -rem applications related to the deployment of airbags, or any -rem other applications that could lead to death, personal -rem injury, or severe property or environmental damage -rem (individually and collectively, "Critical -rem Applications"). Customer assumes the sole risk and -rem liability of any use of Xilinx products in Critical -rem Applications, subject only to applicable laws and -rem regulations governing limitations on product liability. -rem -rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -rem PART OF THIS FILE AT ALL TIMES. - -rem ----------------------------------------------------------------------------- -rem Script to synthesize and implement the Coregen FIFO Generator -rem ----------------------------------------------------------------------------- -rmdir /S /Q results -mkdir results -cd results -copy ..\..\..\axi_vfifo_64_0x2000000.ngc . -planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.sh b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.sh deleted file mode 100755 index 72397bfd2..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.sh +++ /dev/null @@ -1,55 +0,0 @@ -#!/bin/sh -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the Coregen FIFO Generator -#----------------------------------------------------------------------------- -rm -rf results -mkdir results -cd results -cp ../../../axi_vfifo_64_0x2000000.ngc . -planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl deleted file mode 100755 index 110df050c..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl +++ /dev/null @@ -1,67 +0,0 @@ -# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - - -set device xc7k410tffg900-2 -set projName axi_vfifo_64_0x2000000 -set design axi_vfifo_64_0x2000000 -set projDir [file dirname [info script]] -create_project $projName $projDir/results/$projName -part $device -force -set_property design_mode RTL [current_fileset -srcset] -set top_module axi_vfifo_64_0x2000000_exdes -add_files -norecurse {../../example_design/axi_vfifo_64_0x2000000_exdes.vhd} -add_files -norecurse {./axi_vfifo_64_0x2000000.ngc} -import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_0x2000000_exdes.xdc} -set_property top axi_vfifo_64_0x2000000_exdes [get_property srcset [current_run]] -synth_design -opt_design -place_design -route_design -write_sdf -rename_top_module axi_vfifo_64_0x2000000_exdes -file routed.sdf -write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_0x2000000_exdes routed.v -report_timing -nworst 30 -path_type full -file routed.twr -report_drc -file report.drc -write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.prj b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.prj deleted file mode 100755 index 1a6cfc905..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.prj +++ /dev/null @@ -1 +0,0 @@ -work ../example_design/axi_vfifo_64_0x2000000_exdes.vhd diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.scr b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.scr deleted file mode 100755 index 52b4317a0..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.scr +++ /dev/null @@ -1,13 +0,0 @@ -run --ifmt VHDL --ent axi_vfifo_64_0x2000000_exdes --p xc7k410t-ffg900-2 --ifn xst.prj --write_timing_constraints No --iobuf YES --max_fanout 100 --ofn axi_vfifo_64_0x2000000_exdes --ofmt NGC --bus_delimiter () --hierarchy_separator / --case Maintain diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000_flist.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000_flist.txt deleted file mode 100644 index b0af7b27b..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000_flist.txt +++ /dev/null @@ -1,25 +0,0 @@ -# Output products list for -axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt -axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html -axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf -axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf -axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd -axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc -axi_vfifo_64_0x2000000/implement/implement.bat -axi_vfifo_64_0x2000000/implement/implement.sh -axi_vfifo_64_0x2000000/implement/implement_synplify.bat -axi_vfifo_64_0x2000000/implement/implement_synplify.sh -axi_vfifo_64_0x2000000/implement/planAhead_ise.bat -axi_vfifo_64_0x2000000/implement/planAhead_ise.sh -axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl -axi_vfifo_64_0x2000000/implement/xst.prj -axi_vfifo_64_0x2000000/implement/xst.scr -axi_vfifo_64_0x2000000.gise -axi_vfifo_64_0x2000000.ngc -axi_vfifo_64_0x2000000.v -axi_vfifo_64_0x2000000.veo -axi_vfifo_64_0x2000000.xco -axi_vfifo_64_0x2000000.xise -axi_vfifo_64_0x2000000_flist.txt -axi_vfifo_64_0x2000000_xmdf.tcl -axi_vfifo_ctrl_v1_1_readme.txt diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000_xmdf.tcl b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000_xmdf.tcl deleted file mode 100644 index efadac3b4..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_0x2000000_xmdf.tcl +++ /dev/null @@ -1,127 +0,0 @@ -# The package naming convention is _xmdf -package provide axi_vfifo_64_0x2000000_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::axi_vfifo_64_0x2000000_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::axi_vfifo_64_0x2000000_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name axi_vfifo_64_0x2000000 -} -# ::axi_vfifo_64_0x2000000_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::axi_vfifo_64_0x2000000_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement_synplify.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement_synplify.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/planAhead_ise.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/planAhead_ise.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_ctrl_v1_1_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type text -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi_vfifo_64_0x2000000 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_flist.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_flist.txt deleted file mode 100644 index bc1393766..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_flist.txt +++ /dev/null @@ -1,26 +0,0 @@ -# Output products list for -axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt -axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html -axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf -axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf -axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd -axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc -axi_vfifo_64/implement/implement.bat -axi_vfifo_64/implement/implement.sh -axi_vfifo_64/implement/implement_synplify.bat -axi_vfifo_64/implement/implement_synplify.sh -axi_vfifo_64/implement/planAhead_ise.bat -axi_vfifo_64/implement/planAhead_ise.sh -axi_vfifo_64/implement/planAhead_ise.tcl -axi_vfifo_64/implement/xst.prj -axi_vfifo_64/implement/xst.scr -axi_vfifo_64.gise -axi_vfifo_64.ngc -axi_vfifo_64.v -axi_vfifo_64.veo -axi_vfifo_64.xco -axi_vfifo_64.xise -axi_vfifo_64_flist.txt -axi_vfifo_64_synth.v -axi_vfifo_64_xmdf.tcl -axi_vfifo_ctrl_v1_1_readme.txt diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_synth.v b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_synth.v deleted file mode 100644 index aa9df633b..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_synth.v +++ /dev/null @@ -1,190 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2012 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 * -* * -* The AXI Virtual FIFO Controller is a parameterizable number of multi * -* channel FIFO. * -*******************************************************************************/ -// Synthesized Netlist Wrapper -// This file is provided to wrap around the synthesized netlist (if appropriate) - -// Interfaces: -// AXI4Stream_MASTER_M_AXIS -// AXI4Stream_SLAVE_S_AXIS -// AXI4_MASTER_M_AXI - -module axi_vfifo_64 ( - aclk, - aresetn, - m_axi_awid, - m_axi_awaddr, - m_axi_awlen, - m_axi_awsize, - m_axi_awburst, - m_axi_awlock, - m_axi_awcache, - m_axi_awprot, - m_axi_awqos, - m_axi_awregion, - m_axi_awuser, - m_axi_awvalid, - m_axi_awready, - m_axi_wdata, - m_axi_wstrb, - m_axi_wlast, - m_axi_wuser, - m_axi_wvalid, - m_axi_wready, - m_axi_bid, - m_axi_bresp, - m_axi_buser, - m_axi_bvalid, - m_axi_bready, - m_axi_arid, - m_axi_araddr, - m_axi_arlen, - m_axi_arsize, - m_axi_arburst, - m_axi_arlock, - m_axi_arcache, - m_axi_arprot, - m_axi_arqos, - m_axi_arregion, - m_axi_aruser, - m_axi_arvalid, - m_axi_arready, - m_axi_rid, - m_axi_rdata, - m_axi_rresp, - m_axi_rlast, - m_axi_ruser, - m_axi_rvalid, - m_axi_rready, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - s_axis_tstrb, - s_axis_tkeep, - s_axis_tlast, - s_axis_tid, - s_axis_tdest, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata, - m_axis_tstrb, - m_axis_tkeep, - m_axis_tlast, - m_axis_tid, - m_axis_tdest, - vfifo_mm2s_channel_full, - vfifo_s2mm_channel_full, - vfifo_mm2s_channel_empty, - vfifo_mm2s_rresp_err_intr, - vfifo_s2mm_bresp_err_intr, - vfifo_s2mm_overrun_err_intr, - vfifo_idle -); - - input aclk; - input aresetn; - output [0 : 0] m_axi_awid; - output [31 : 0] m_axi_awaddr; - output [7 : 0] m_axi_awlen; - output [2 : 0] m_axi_awsize; - output [1 : 0] m_axi_awburst; - output [0 : 0] m_axi_awlock; - output [3 : 0] m_axi_awcache; - output [2 : 0] m_axi_awprot; - output [3 : 0] m_axi_awqos; - output [3 : 0] m_axi_awregion; - output [0 : 0] m_axi_awuser; - output m_axi_awvalid; - input m_axi_awready; - output [63 : 0] m_axi_wdata; - output [7 : 0] m_axi_wstrb; - output m_axi_wlast; - output [0 : 0] m_axi_wuser; - output m_axi_wvalid; - input m_axi_wready; - input [0 : 0] m_axi_bid; - input [1 : 0] m_axi_bresp; - input [0 : 0] m_axi_buser; - input m_axi_bvalid; - output m_axi_bready; - output [0 : 0] m_axi_arid; - output [31 : 0] m_axi_araddr; - output [7 : 0] m_axi_arlen; - output [2 : 0] m_axi_arsize; - output [1 : 0] m_axi_arburst; - output [0 : 0] m_axi_arlock; - output [3 : 0] m_axi_arcache; - output [2 : 0] m_axi_arprot; - output [3 : 0] m_axi_arqos; - output [3 : 0] m_axi_arregion; - output [0 : 0] m_axi_aruser; - output m_axi_arvalid; - input m_axi_arready; - input [0 : 0] m_axi_rid; - input [63 : 0] m_axi_rdata; - input [1 : 0] m_axi_rresp; - input m_axi_rlast; - input [0 : 0] m_axi_ruser; - input m_axi_rvalid; - output m_axi_rready; - input s_axis_tvalid; - output s_axis_tready; - input [63 : 0] s_axis_tdata; - input [7 : 0] s_axis_tstrb; - input [7 : 0] s_axis_tkeep; - input s_axis_tlast; - input [0 : 0] s_axis_tid; - input [0 : 0] s_axis_tdest; - output m_axis_tvalid; - input m_axis_tready; - output [63 : 0] m_axis_tdata; - output [7 : 0] m_axis_tstrb; - output [7 : 0] m_axis_tkeep; - output m_axis_tlast; - output [0 : 0] m_axis_tid; - output [0 : 0] m_axis_tdest; - input [1 : 0] vfifo_mm2s_channel_full; - output [1 : 0] vfifo_s2mm_channel_full; - output [1 : 0] vfifo_mm2s_channel_empty; - output vfifo_mm2s_rresp_err_intr; - output vfifo_s2mm_bresp_err_intr; - output vfifo_s2mm_overrun_err_intr; - output [1 : 0] vfifo_idle; - - // WARNING: This file provides a module declaration only, it does not support - // direct instantiation. Please use an instantiation template (VEO) to - // instantiate the IP within a design. - -endmodule - diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_xmdf.tcl b/fpga/usrp3/top/x300/coregen/axi_vfifo_64_xmdf.tcl deleted file mode 100644 index 3b1382e1e..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_64_xmdf.tcl +++ /dev/null @@ -1,131 +0,0 @@ -# The package naming convention is _xmdf -package provide axi_vfifo_64_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::axi_vfifo_64_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::axi_vfifo_64_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name axi_vfifo_64 -} -# ::axi_vfifo_64_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::axi_vfifo_64_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement_synplify.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement_synplify.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/planAhead_ise.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/planAhead_ise.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/planAhead_ise.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_synth.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_ctrl_v1_1_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type text -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi_vfifo_64 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen/axi_vfifo_ctrl_v1_1_readme.txt b/fpga/usrp3/top/x300/coregen/axi_vfifo_ctrl_v1_1_readme.txt deleted file mode 100644 index 2fbc94c40..000000000 --- a/fpga/usrp3/top/x300/coregen/axi_vfifo_ctrl_v1_1_readme.txt +++ /dev/null @@ -1,189 +0,0 @@ -CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 - - Core name: Xilinx LogiCORE AXI Virtual FIFO Controller - Version: 1.1 - Release: ISE 14.2 / Vivado 2012.2 - Release Date: July 25, 2012 - --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURES HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm - -................................................................................ - - -2. DEVICE SUPPORT - - - 2.1 ISE - - The following device families are supported by the core for this release. - - - All 7 Series devices - Zynq-7000 devices - All Virtex-6 devices - All Spartan-6 devices - - - 2.2 Vivado - - All 7 Series devices - Zynq-7000 devices - -................................................................................ - - -3. NEW FEATURES HISTORY - - - 3.1 ISE - - - First release - - ISE 14.2 software support - - - 3.2 Vivado - - - First release - - 2012.2 software support - -................................................................................ - - -4. RESOLVED ISSUES - - - 4.1 ISE - - - N/A - - - 4.2 Vivado - - - N/A - - -................................................................................ - - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - N/A - - - 5.2 Vivado - - - N/A - - -The most recent information, including known issues, workarounds, and -resolutions for this version is provided in the IP Release Notes User Guide -located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -................................................................................ - - -6. TECHNICAL SUPPORT & FEEDBACK - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -................................................................................ - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support. -04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support. -================================================================================ - -................................................................................ - - -8. LEGAL DISCLAIMER - -(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon.xise b/fpga/usrp3/top/x300/coregen/chipscope_icon.xise index 82f131ab5..4a084a6b9 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_icon.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_icon.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise index c1b1aa977..fc32f96d2 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila.xise b/fpga/usrp3/top/x300/coregen/chipscope_ila.xise index c77f79bd9..f73d28a38 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_ila.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_ila.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise index bc394c976..eb350b340 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen/coregen.cgp b/fpga/usrp3/top/x300/coregen/coregen.cgp index 287f67be4..3e343ea49 100644 --- a/fpga/usrp3/top/x300/coregen/coregen.cgp +++ b/fpga/usrp3/top/x300/coregen/coregen.cgp @@ -1,6 +1,6 @@ SET busformat = BusFormatAngleBracketNotRipped SET designentry = Verilog -SET device = xc7k410t +SET device = xc7k325t SET devicefamily = kintex7 SET flowvendor = Foundation_ISE SET package = ffg900 diff --git a/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise b/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise index d8694a9ea..76490a41b 100644 --- a/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise +++ b/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.asy b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.asy deleted file mode 100644 index 45b851986..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.asy +++ /dev/null @@ -1,41 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_xlnx_16x40_2clk -RECTANGLE Normal 32 32 800 4064 -LINE Normal 0 112 32 112 -PIN 0 112 LEFT 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Normal 0 208 32 208 -PIN 0 208 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Wide 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName din[39:0] -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 464 32 464 -PIN 0 464 LEFT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Normal 832 240 800 240 -PIN 832 240 RIGHT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Wide 832 272 800 272 -PIN 832 272 RIGHT 36 -PINATTR PinName dout[39:0] -PINATTR Polarity OUT -LINE Normal 832 304 800 304 -PIN 832 304 RIGHT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 832 496 800 496 -PIN 832 496 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise deleted file mode 100644 index 64c479aaf..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.ncf b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.ngc b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.ngc deleted file mode 100644 index 79ec7f828..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.v b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.v deleted file mode 100644 index 873e171e5..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.v +++ /dev/null @@ -1,487 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2013 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating -// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -`timescale 1ns/1ps - -module fifo_xlnx_16x40_2clk( - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - empty -); - -input rst; -input wr_clk; -input rd_clk; -input [39 : 0] din; -input wr_en; -input rd_en; -output [39 : 0] dout; -output full; -output empty; - -// synthesis translate_off - - FIFO_GENERATOR_V9_3 #( - .C_ADD_NGC_CONSTRAINT(0), - .C_APPLICATION_TYPE_AXIS(0), - .C_APPLICATION_TYPE_RACH(0), - .C_APPLICATION_TYPE_RDCH(0), - .C_APPLICATION_TYPE_WACH(0), - .C_APPLICATION_TYPE_WDCH(0), - .C_APPLICATION_TYPE_WRCH(0), - .C_AXI_ADDR_WIDTH(32), - .C_AXI_ARUSER_WIDTH(1), - .C_AXI_AWUSER_WIDTH(1), - .C_AXI_BUSER_WIDTH(1), - .C_AXI_DATA_WIDTH(64), - .C_AXI_ID_WIDTH(4), - .C_AXI_RUSER_WIDTH(1), - .C_AXI_TYPE(0), - .C_AXI_WUSER_WIDTH(1), - .C_AXIS_TDATA_WIDTH(64), - .C_AXIS_TDEST_WIDTH(4), - .C_AXIS_TID_WIDTH(8), - .C_AXIS_TKEEP_WIDTH(4), - .C_AXIS_TSTRB_WIDTH(4), - .C_AXIS_TUSER_WIDTH(4), - .C_AXIS_TYPE(0), - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(4), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(40), - .C_DIN_WIDTH_AXIS(1), - .C_DIN_WIDTH_RACH(32), - .C_DIN_WIDTH_RDCH(64), - .C_DIN_WIDTH_WACH(32), - .C_DIN_WIDTH_WDCH(64), - .C_DIN_WIDTH_WRCH(2), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(40), - .C_ENABLE_RLOCS(0), - .C_ENABLE_RST_SYNC(1), - .C_ERROR_INJECTION_TYPE(0), - .C_ERROR_INJECTION_TYPE_AXIS(0), - .C_ERROR_INJECTION_TYPE_RACH(0), - .C_ERROR_INJECTION_TYPE_RDCH(0), - .C_ERROR_INJECTION_TYPE_WACH(0), - .C_ERROR_INJECTION_TYPE_WDCH(0), - .C_ERROR_INJECTION_TYPE_WRCH(0), - .C_FAMILY("kintex7"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_AXI_ARUSER(0), - .C_HAS_AXI_AWUSER(0), - .C_HAS_AXI_BUSER(0), - .C_HAS_AXI_RD_CHANNEL(0), - .C_HAS_AXI_RUSER(0), - .C_HAS_AXI_WR_CHANNEL(0), - .C_HAS_AXI_WUSER(0), - .C_HAS_AXIS_TDATA(0), - .C_HAS_AXIS_TDEST(0), - .C_HAS_AXIS_TID(0), - .C_HAS_AXIS_TKEEP(0), - .C_HAS_AXIS_TLAST(0), - .C_HAS_AXIS_TREADY(1), - .C_HAS_AXIS_TSTRB(0), - .C_HAS_AXIS_TUSER(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_DATA_COUNTS_AXIS(0), - .C_HAS_DATA_COUNTS_RACH(0), - .C_HAS_DATA_COUNTS_RDCH(0), - .C_HAS_DATA_COUNTS_WACH(0), - .C_HAS_DATA_COUNTS_WDCH(0), - .C_HAS_DATA_COUNTS_WRCH(0), - .C_HAS_INT_CLK(0), - .C_HAS_MASTER_CE(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_PROG_FLAGS_AXIS(0), - .C_HAS_PROG_FLAGS_RACH(0), - .C_HAS_PROG_FLAGS_RDCH(0), - .C_HAS_PROG_FLAGS_WACH(0), - .C_HAS_PROG_FLAGS_WDCH(0), - .C_HAS_PROG_FLAGS_WRCH(0), - .C_HAS_RD_DATA_COUNT(0), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SLAVE_CE(0), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(0), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_IMPLEMENTATION_TYPE_AXIS(1), - .C_IMPLEMENTATION_TYPE_RACH(1), - .C_IMPLEMENTATION_TYPE_RDCH(1), - .C_IMPLEMENTATION_TYPE_WACH(1), - .C_IMPLEMENTATION_TYPE_WDCH(1), - .C_IMPLEMENTATION_TYPE_WRCH(1), - .C_INIT_WR_PNTR_VAL(0), - .C_INTERFACE_TYPE(0), - .C_MEMORY_TYPE(2), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x72"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_EMPTY_TYPE_AXIS(0), - .C_PROG_EMPTY_TYPE_RACH(0), - .C_PROG_EMPTY_TYPE_RDCH(0), - .C_PROG_EMPTY_TYPE_WACH(0), - .C_PROG_EMPTY_TYPE_WDCH(0), - .C_PROG_EMPTY_TYPE_WRCH(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(15), - .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), - .C_PROG_FULL_THRESH_NEGATE_VAL(14), - .C_PROG_FULL_TYPE(0), - .C_PROG_FULL_TYPE_AXIS(0), - .C_PROG_FULL_TYPE_RACH(0), - .C_PROG_FULL_TYPE_RDCH(0), - .C_PROG_FULL_TYPE_WACH(0), - .C_PROG_FULL_TYPE_WDCH(0), - .C_PROG_FULL_TYPE_WRCH(0), - .C_RACH_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(4), - .C_RD_DEPTH(16), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(4), - .C_RDCH_TYPE(0), - .C_REG_SLICE_MODE_AXIS(0), - .C_REG_SLICE_MODE_RACH(0), - .C_REG_SLICE_MODE_RDCH(0), - .C_REG_SLICE_MODE_WACH(0), - .C_REG_SLICE_MODE_WDCH(0), - .C_REG_SLICE_MODE_WRCH(0), - .C_SYNCHRONIZER_STAGE(2), - .C_UNDERFLOW_LOW(0), - .C_USE_COMMON_OVERFLOW(0), - .C_USE_COMMON_UNDERFLOW(0), - .C_USE_DEFAULT_SETTINGS(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_ECC_AXIS(0), - .C_USE_ECC_RACH(0), - .C_USE_ECC_RDCH(0), - .C_USE_ECC_WACH(0), - .C_USE_ECC_WDCH(0), - .C_USE_ECC_WRCH(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(0), - .C_VALID_LOW(0), - .C_WACH_TYPE(0), - .C_WDCH_TYPE(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(4), - .C_WR_DEPTH(16), - .C_WR_DEPTH_AXIS(1024), - .C_WR_DEPTH_RACH(16), - .C_WR_DEPTH_RDCH(1024), - .C_WR_DEPTH_WACH(16), - .C_WR_DEPTH_WDCH(1024), - .C_WR_DEPTH_WRCH(16), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(4), - .C_WR_PNTR_WIDTH_AXIS(10), - .C_WR_PNTR_WIDTH_RACH(4), - .C_WR_PNTR_WIDTH_RDCH(10), - .C_WR_PNTR_WIDTH_WACH(4), - .C_WR_PNTR_WIDTH_WDCH(10), - .C_WR_PNTR_WIDTH_WRCH(4), - .C_WR_RESPONSE_LATENCY(1), - .C_WRCH_TYPE(0) - ) - inst ( - .RST(rst), - .WR_CLK(wr_clk), - .RD_CLK(rd_clk), - .DIN(din), - .WR_EN(wr_en), - .RD_EN(rd_en), - .DOUT(dout), - .FULL(full), - .EMPTY(empty), - .BACKUP(), - .BACKUP_MARKER(), - .CLK(), - .SRST(), - .WR_RST(), - .RD_RST(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .INT_CLK(), - .INJECTDBITERR(), - .INJECTSBITERR(), - .ALMOST_FULL(), - .WR_ACK(), - .OVERFLOW(), - .ALMOST_EMPTY(), - .VALID(), - .UNDERFLOW(), - .DATA_COUNT(), - .RD_DATA_COUNT(), - .WR_DATA_COUNT(), - .PROG_FULL(), - .PROG_EMPTY(), - .SBITERR(), - .DBITERR(), - .M_ACLK(), - .S_ACLK(), - .S_ARESETN(), - .M_ACLK_EN(), - .S_ACLK_EN(), - .S_AXI_AWID(), - .S_AXI_AWADDR(), - .S_AXI_AWLEN(), - .S_AXI_AWSIZE(), - .S_AXI_AWBURST(), - .S_AXI_AWLOCK(), - .S_AXI_AWCACHE(), - .S_AXI_AWPROT(), - .S_AXI_AWQOS(), - .S_AXI_AWREGION(), - .S_AXI_AWUSER(), - .S_AXI_AWVALID(), - .S_AXI_AWREADY(), - .S_AXI_WID(), - .S_AXI_WDATA(), - .S_AXI_WSTRB(), - .S_AXI_WLAST(), - .S_AXI_WUSER(), - .S_AXI_WVALID(), - .S_AXI_WREADY(), - .S_AXI_BID(), - .S_AXI_BRESP(), - .S_AXI_BUSER(), - .S_AXI_BVALID(), - .S_AXI_BREADY(), - .M_AXI_AWID(), - .M_AXI_AWADDR(), - .M_AXI_AWLEN(), - .M_AXI_AWSIZE(), - .M_AXI_AWBURST(), - .M_AXI_AWLOCK(), - .M_AXI_AWCACHE(), - .M_AXI_AWPROT(), - .M_AXI_AWQOS(), - .M_AXI_AWREGION(), - .M_AXI_AWUSER(), - .M_AXI_AWVALID(), - .M_AXI_AWREADY(), - .M_AXI_WID(), - .M_AXI_WDATA(), - .M_AXI_WSTRB(), - .M_AXI_WLAST(), - .M_AXI_WUSER(), - .M_AXI_WVALID(), - .M_AXI_WREADY(), - .M_AXI_BID(), - .M_AXI_BRESP(), - .M_AXI_BUSER(), - .M_AXI_BVALID(), - .M_AXI_BREADY(), - .S_AXI_ARID(), - .S_AXI_ARADDR(), - .S_AXI_ARLEN(), - .S_AXI_ARSIZE(), - .S_AXI_ARBURST(), - .S_AXI_ARLOCK(), - .S_AXI_ARCACHE(), - .S_AXI_ARPROT(), - .S_AXI_ARQOS(), - .S_AXI_ARREGION(), - .S_AXI_ARUSER(), - .S_AXI_ARVALID(), - .S_AXI_ARREADY(), - .S_AXI_RID(), - .S_AXI_RDATA(), - .S_AXI_RRESP(), - .S_AXI_RLAST(), - .S_AXI_RUSER(), - .S_AXI_RVALID(), - .S_AXI_RREADY(), - .M_AXI_ARID(), - .M_AXI_ARADDR(), - .M_AXI_ARLEN(), - .M_AXI_ARSIZE(), - .M_AXI_ARBURST(), - .M_AXI_ARLOCK(), - .M_AXI_ARCACHE(), - .M_AXI_ARPROT(), - .M_AXI_ARQOS(), - .M_AXI_ARREGION(), - .M_AXI_ARUSER(), - .M_AXI_ARVALID(), - .M_AXI_ARREADY(), - .M_AXI_RID(), - .M_AXI_RDATA(), - .M_AXI_RRESP(), - .M_AXI_RLAST(), - .M_AXI_RUSER(), - .M_AXI_RVALID(), - .M_AXI_RREADY(), - .S_AXIS_TVALID(), - .S_AXIS_TREADY(), - .S_AXIS_TDATA(), - .S_AXIS_TSTRB(), - .S_AXIS_TKEEP(), - .S_AXIS_TLAST(), - .S_AXIS_TID(), - .S_AXIS_TDEST(), - .S_AXIS_TUSER(), - .M_AXIS_TVALID(), - .M_AXIS_TREADY(), - .M_AXIS_TDATA(), - .M_AXIS_TSTRB(), - .M_AXIS_TKEEP(), - .M_AXIS_TLAST(), - .M_AXIS_TID(), - .M_AXIS_TDEST(), - .M_AXIS_TUSER(), - .AXI_AW_INJECTSBITERR(), - .AXI_AW_INJECTDBITERR(), - .AXI_AW_PROG_FULL_THRESH(), - .AXI_AW_PROG_EMPTY_THRESH(), - .AXI_AW_DATA_COUNT(), - .AXI_AW_WR_DATA_COUNT(), - .AXI_AW_RD_DATA_COUNT(), - .AXI_AW_SBITERR(), - .AXI_AW_DBITERR(), - .AXI_AW_OVERFLOW(), - .AXI_AW_UNDERFLOW(), - .AXI_AW_PROG_FULL(), - .AXI_AW_PROG_EMPTY(), - .AXI_W_INJECTSBITERR(), - .AXI_W_INJECTDBITERR(), - .AXI_W_PROG_FULL_THRESH(), - .AXI_W_PROG_EMPTY_THRESH(), - .AXI_W_DATA_COUNT(), - .AXI_W_WR_DATA_COUNT(), - .AXI_W_RD_DATA_COUNT(), - .AXI_W_SBITERR(), - .AXI_W_DBITERR(), - .AXI_W_OVERFLOW(), - .AXI_W_UNDERFLOW(), - .AXI_B_INJECTSBITERR(), - .AXI_W_PROG_FULL(), - .AXI_W_PROG_EMPTY(), - .AXI_B_INJECTDBITERR(), - .AXI_B_PROG_FULL_THRESH(), - .AXI_B_PROG_EMPTY_THRESH(), - .AXI_B_DATA_COUNT(), - .AXI_B_WR_DATA_COUNT(), - .AXI_B_RD_DATA_COUNT(), - .AXI_B_SBITERR(), - .AXI_B_DBITERR(), - .AXI_B_OVERFLOW(), - .AXI_B_UNDERFLOW(), - .AXI_AR_INJECTSBITERR(), - .AXI_B_PROG_FULL(), - .AXI_B_PROG_EMPTY(), - .AXI_AR_INJECTDBITERR(), - .AXI_AR_PROG_FULL_THRESH(), - .AXI_AR_PROG_EMPTY_THRESH(), - .AXI_AR_DATA_COUNT(), - .AXI_AR_WR_DATA_COUNT(), - .AXI_AR_RD_DATA_COUNT(), - .AXI_AR_SBITERR(), - .AXI_AR_DBITERR(), - .AXI_AR_OVERFLOW(), - .AXI_AR_UNDERFLOW(), - .AXI_AR_PROG_FULL(), - .AXI_AR_PROG_EMPTY(), - .AXI_R_INJECTSBITERR(), - .AXI_R_INJECTDBITERR(), - .AXI_R_PROG_FULL_THRESH(), - .AXI_R_PROG_EMPTY_THRESH(), - .AXI_R_DATA_COUNT(), - .AXI_R_WR_DATA_COUNT(), - .AXI_R_RD_DATA_COUNT(), - .AXI_R_SBITERR(), - .AXI_R_DBITERR(), - .AXI_R_OVERFLOW(), - .AXI_R_UNDERFLOW(), - .AXIS_INJECTSBITERR(), - .AXI_R_PROG_FULL(), - .AXI_R_PROG_EMPTY(), - .AXIS_INJECTDBITERR(), - .AXIS_PROG_FULL_THRESH(), - .AXIS_PROG_EMPTY_THRESH(), - .AXIS_DATA_COUNT(), - .AXIS_WR_DATA_COUNT(), - .AXIS_RD_DATA_COUNT(), - .AXIS_SBITERR(), - .AXIS_DBITERR(), - .AXIS_OVERFLOW(), - .AXIS_UNDERFLOW(), - .AXIS_PROG_FULL(), - .AXIS_PROG_EMPTY() - ); - -// synthesis translate_on - -endmodule diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.veo b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.veo deleted file mode 100644 index 4f0455d7e..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.veo +++ /dev/null @@ -1,77 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2013 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * -* * -* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * -* memory queue generator. Use it to generate resource and performance * -* optimized FIFOs with common or independent read/write clock domains, * -* and optional fixed or programmable full and empty flags and * -* handshaking signals. Choose from a selection of memory resource * -* types for implementation. Optional Hamming code based error * -* detection and correction as well as error injection capability for * -* system test help to insure data integrity. FIFO width and depth are * -* parameterizable, and for native interface FIFOs, asymmetric read and * -* write port widths are also supported. * -*******************************************************************************/ - -// Interfaces: -// AXI4Stream_MASTER_M_AXIS -// AXI4Stream_SLAVE_S_AXIS -// AXI4_MASTER_M_AXI -// AXI4_SLAVE_S_AXI -// AXI4Lite_MASTER_M_AXI -// AXI4Lite_SLAVE_S_AXI -// master_aclk -// slave_aclk -// slave_aresetn - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_16x40_2clk your_instance_name ( - .rst(rst), // input rst - .wr_clk(wr_clk), // input wr_clk - .rd_clk(rd_clk), // input rd_clk - .din(din), // input [39 : 0] din - .wr_en(wr_en), // input wr_en - .rd_en(rd_en), // input rd_en - .dout(dout), // output [39 : 0] dout - .full(full), // output full - .empty(empty) // output empty -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating -// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xco b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xco deleted file mode 100644 index f5524f637..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xco +++ /dev/null @@ -1,213 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Fri May 3 23:15:24 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:fifo_generator:9.3 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 -# END Select -# BEGIN Parameters -CSET add_ngc_constraint_axi=false -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET aruser_width=1 -CSET awuser_width=1 -CSET axi_address_width=32 -CSET axi_data_width=64 -CSET axi_type=AXI4_Stream -CSET axis_type=FIFO -CSET buser_width=1 -CSET clock_enable_type=Slave_Interface_Clock_Enable -CSET clock_type_axi=Common_Clock -CSET component_name=fifo_xlnx_16x40_2clk -CSET data_count=false -CSET data_count_width=4 -CSET disable_timing_violations=false -CSET disable_timing_violations_axi=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_assert_value_axis=1022 -CSET empty_threshold_assert_value_rach=1022 -CSET empty_threshold_assert_value_rdch=1022 -CSET empty_threshold_assert_value_wach=1022 -CSET empty_threshold_assert_value_wdch=1022 -CSET empty_threshold_assert_value_wrch=1022 -CSET empty_threshold_negate_value=5 -CSET enable_aruser=false -CSET enable_awuser=false -CSET enable_buser=false -CSET enable_common_overflow=false -CSET enable_common_underflow=false -CSET enable_data_counts_axis=false -CSET enable_data_counts_rach=false -CSET enable_data_counts_rdch=false -CSET enable_data_counts_wach=false -CSET enable_data_counts_wdch=false -CSET enable_data_counts_wrch=false -CSET enable_ecc=false -CSET enable_ecc_axis=false -CSET enable_ecc_rach=false -CSET enable_ecc_rdch=false -CSET enable_ecc_wach=false -CSET enable_ecc_wdch=false -CSET enable_ecc_wrch=false -CSET enable_read_channel=false -CSET enable_read_pointer_increment_by2=false -CSET enable_reset_synchronization=true -CSET enable_ruser=false -CSET enable_tdata=false -CSET enable_tdest=false -CSET enable_tid=false -CSET enable_tkeep=false -CSET enable_tlast=false -CSET enable_tready=true -CSET enable_tstrobe=false -CSET enable_tuser=false -CSET enable_write_channel=false -CSET enable_wuser=false -CSET fifo_application_type_axis=Data_FIFO -CSET fifo_application_type_rach=Data_FIFO -CSET fifo_application_type_rdch=Data_FIFO -CSET fifo_application_type_wach=Data_FIFO -CSET fifo_application_type_wdch=Data_FIFO -CSET fifo_application_type_wrch=Data_FIFO -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET fifo_implementation_axis=Common_Clock_Block_RAM -CSET fifo_implementation_rach=Common_Clock_Block_RAM -CSET fifo_implementation_rdch=Common_Clock_Block_RAM -CSET fifo_implementation_wach=Common_Clock_Block_RAM -CSET fifo_implementation_wdch=Common_Clock_Block_RAM -CSET fifo_implementation_wrch=Common_Clock_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=15 -CSET full_threshold_assert_value_axis=1023 -CSET full_threshold_assert_value_rach=1023 -CSET full_threshold_assert_value_rdch=1023 -CSET full_threshold_assert_value_wach=1023 -CSET full_threshold_assert_value_wdch=1023 -CSET full_threshold_assert_value_wrch=1023 -CSET full_threshold_negate_value=14 -CSET id_width=4 -CSET inject_dbit_error=false -CSET inject_dbit_error_axis=false -CSET inject_dbit_error_rach=false -CSET inject_dbit_error_rdch=false -CSET inject_dbit_error_wach=false -CSET inject_dbit_error_wdch=false -CSET inject_dbit_error_wrch=false -CSET inject_sbit_error=false -CSET inject_sbit_error_axis=false -CSET inject_sbit_error_rach=false -CSET inject_sbit_error_rdch=false -CSET inject_sbit_error_wach=false -CSET inject_sbit_error_wdch=false -CSET inject_sbit_error_wrch=false -CSET input_data_width=40 -CSET input_depth=16 -CSET input_depth_axis=1024 -CSET input_depth_rach=16 -CSET input_depth_rdch=1024 -CSET input_depth_wach=16 -CSET input_depth_wdch=1024 -CSET input_depth_wrch=16 -CSET interface_type=Native -CSET output_data_width=40 -CSET output_depth=16 -CSET overflow_flag=false -CSET overflow_flag_axi=false -CSET overflow_sense=Active_High -CSET overflow_sense_axi=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET programmable_full_type_axis=No_Programmable_Full_Threshold -CSET programmable_full_type_rach=No_Programmable_Full_Threshold -CSET programmable_full_type_rdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wach=No_Programmable_Full_Threshold -CSET programmable_full_type_wdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wrch=No_Programmable_Full_Threshold -CSET rach_type=FIFO -CSET rdch_type=FIFO -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=4 -CSET register_slice_mode_axis=Fully_Registered -CSET register_slice_mode_rach=Fully_Registered -CSET register_slice_mode_rdch=Fully_Registered -CSET register_slice_mode_wach=Fully_Registered -CSET register_slice_mode_wdch=Fully_Registered -CSET register_slice_mode_wrch=Fully_Registered -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET ruser_width=1 -CSET synchronization_stages=2 -CSET synchronization_stages_axi=2 -CSET tdata_width=64 -CSET tdest_width=4 -CSET tid_width=8 -CSET tkeep_width=4 -CSET tstrb_width=4 -CSET tuser_width=4 -CSET underflow_flag=false -CSET underflow_flag_axi=false -CSET underflow_sense=Active_High -CSET underflow_sense_axi=Active_High -CSET use_clock_enable=false -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET wach_type=FIFO -CSET wdch_type=FIFO -CSET wrch_type=FIFO -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=4 -CSET wuser_width=1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T12:39:56Z -# END Extra information -GENERATE -# CRC: 64a8999c diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise deleted file mode 100644 index 9d088377d..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_readme.txt deleted file mode 100644 index 7853ebde8..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_readme.txt +++ /dev/null @@ -1,236 +0,0 @@ -CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 - - Release Date: December 18, 2012 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm - -................................................................................ - - -2. DEVICE SUPPORT - - - 2.1 ISE - - The following device families are supported by the core for this release. - - - All 7 Series devices - Zynq-7000 devices - All Virtex-6 devices - All Spartan-6 devices - All Virtex-5 devices - All Spartan-3 devices - All Virtex-4 devices - - - 2.2 Vivado - - All 7 Series devices - Zynq-7000 devices - -................................................................................ - - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - ISE 14.4 software support - - - 3.2 Vivado - - - 2012.4 software support - - IP level constraint for Built-in FIFO reset synchronizer - -................................................................................ - - -4. RESOLVED ISSUES - - - 4.1 ISE - - - N/A - - - 4.2 Vivado - - - N/A - - -................................................................................ - - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - The following are known issues for v9.3 Rev 1 of this core at time of release: - - 1. Importing an XCO file alters the XCO configurations - - Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) - into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, - page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. - - CR 467240 - AR 31379 - - 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed - - Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, - correct behavior of the FIFO status flags cannot be guaranteed after the first write. - - Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. - For more information and additional workaround see Answer Record 41099. - - 5.2 Vivado - - The following are known issues for v9.3 Rev 1 of this core at time of release: - - 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen - ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. - - CR 665836 - -The most recent information, including known issues, workarounds, and -resolutions for this version is provided in the IP Release Notes User Guide -located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -................................................................................ - - -6. TECHNICAL SUPPORT & FEEDBACK - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -................................................................................ - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer -10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO -07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO -04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support - AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO -01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support -10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support -06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support -03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support -10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support -09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support -07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support -06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support -04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support -12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support -09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support -06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support -04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support -09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes -03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes -10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs -08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO -04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support -09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support -07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support -01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 -08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 -04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 -11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 -05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support -04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release -================================================================================ - -................................................................................ - - -8. LEGAL DISCLAIMER - -(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_vinfo.html deleted file mode 100644 index fefce62a3..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_vinfo.html +++ /dev/null @@ -1,247 +0,0 @@ - - -fifo_generator_v9_3_vinfo - - - -

-CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
-
-                    Release Date: December 18, 2012
---------------------------------------------------------------------------------
-
-Table of Contents
-
-1. INTRODUCTION 
-2. DEVICE SUPPORT    
-3. NEW FEATURE HISTORY   
-4. RESOLVED ISSUES 
-5. KNOWN ISSUES & LIMITATIONS 
-6. TECHNICAL SUPPORT & FEEDBACK
-7. CORE RELEASE HISTORY 
-8. LEGAL DISCLAIMER 
-
---------------------------------------------------------------------------------  
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
-solution. For the latest core updates, see the product page at:
- 
-   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
-
-................................................................................
-
-
-2. DEVICE SUPPORT
-
-
-  2.1 ISE 
-   
-    The following device families are supported by the core for this release.
-    
-    
-    All 7 Series devices
-    Zynq-7000 devices
-    All Virtex-6 devices
-    All Spartan-6 devices
-    All Virtex-5 devices
-    All Spartan-3 devices
-    All Virtex-4 devices
-  
-  
-  2.2 Vivado 
-  
-    All 7 Series devices
-    Zynq-7000 devices
-
-................................................................................
-
-
-3. NEW FEATURE HISTORY
-
-
-  3.1 ISE 
-  
-    - ISE 14.4 software support
-
-  
-  3.2 Vivado
-  
-    - 2012.4 software support
-    - IP level constraint for Built-in FIFO reset synchronizer
-
-................................................................................
-
-
-4. RESOLVED ISSUES 
-
-
-  4.1 ISE 
-
-    - N/A
-
-
-  4.2 Vivado 
-
-    - N/A
-
-
-................................................................................
-
-
-5. KNOWN ISSUES & LIMITATIONS 
-
-
-  5.1 ISE 
-  
-    The following are known issues for v9.3 Rev 1 of this core at time of release:
-  
-    1. Importing an XCO file alters the XCO configurations
-  
-       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
-       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
-       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
-    
-       CR 467240
-       AR 31379
-  
-    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
-  
-       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
-       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
-    
-       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
-       For more information and additional workaround see Answer Record 41099.
-  
-  5.2 Vivado 
-
-    The following are known issues for v9.3 Rev 1 of this core at time of release:
-     
-    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
-       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
-      
-       CR 665836
-
-The most recent information, including known issues, workarounds, and
-resolutions for this version is provided in the IP Release Notes User Guide
-located at 
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
-
-................................................................................
-
-
-6. TECHNICAL SUPPORT & FEEDBACK
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.  
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-................................................................................
-
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
-10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
-07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
-04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
-                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
-01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
-10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
-06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
-03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
-10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
-09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
-07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
-06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
-04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
-12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
-09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
-06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
-04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
-09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
-03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
-10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
-08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
-04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
-09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
-07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
-01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
-08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
-04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
-11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
-05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
-04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
-================================================================================
-
-................................................................................
-
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
-
-  This file contains confidential and proprietary information
-  of Xilinx, Inc. and is protected under U.S. and
-  international copyright and other intellectual property
-  laws.
-
-  DISCLAIMER
-  This disclaimer is not a license and does not grant any
-  rights to the materials distributed herewith. Except as
-  otherwise provided in a valid license issued to you by
-  Xilinx, and to the maximum extent permitted by applicable
-  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-  (2) Xilinx shall not be liable (whether in contract or tort,
-  including negligence, or under any other theory of
-  liability) for any loss or damage of any kind or nature
-  related to, arising under or in connection with these
-  materials, including for any direct, or any indirect,
-  special, incidental, or consequential loss or damage
-  (including loss of data, profits, goodwill, or any type of
-  loss or damage suffered as a result of any action brought
-  by a third party) even if such damage or loss was
-  reasonably foreseeable or Xilinx had been advised of the
-  possibility of the same. 
-
-  CRITICAL APPLICATIONS
-  Xilinx products are not designed or intended to be fail-
-  safe, or for use in any application requiring fail-safe
-  performance, such as life-support or safety devices or
-  systems, Class III medical devices, nuclear facilities,
-  applications related to the deployment of airbags, or any
-  other applications that could lead to death, personal
-  injury, or severe property or environmental damage
-  (individually and collectively, "Critical 
-  Applications"). Customer assumes the sole risk and 
-  liability of any use of Xilinx products in Critical 
-  Applications, subject only to applicable laws and 
-  regulations governing limitations on product liability. 
- 
-  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-  PART OF THIS FILE AT ALL TIMES.
-
-
- - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/pg057-fifo-generator.pdf deleted file mode 100644 index 5ec45fbcb..000000000 Binary files a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/doc/pg057-fifo-generator.pdf and /dev/null differ diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.ucf b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.ucf deleted file mode 100755 index 62e5058ab..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.ucf +++ /dev/null @@ -1,56 +0,0 @@ -################################################################################ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -################################################################################ - -# Core Period Constraint. This constraint can be modified, and is -# valid as long as it is met after place and route. - NET "RD_CLK" TNM_NET = "RD_CLK"; - NET "WR_CLK" TNM_NET = "WR_CLK"; - TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; - TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; -################################################################################ diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.vhd deleted file mode 100755 index 3c1bc60be..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.vhd +++ /dev/null @@ -1,139 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core - core top file for implementation --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_exdes.vhd --- --- Description: --- This is the FIFO core wrapper with BUFG instances for clock connections. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library unisim; -use unisim.vcomponents.all; - --------------------------------------------------------------------------------- --- Entity Declaration --------------------------------------------------------------------------------- -entity fifo_xlnx_16x40_2clk_exdes is - PORT ( - WR_CLK : IN std_logic; - RD_CLK : IN std_logic; - RST : IN std_logic; - WR_EN : IN std_logic; - RD_EN : IN std_logic; - DIN : IN std_logic_vector(40-1 DOWNTO 0); - DOUT : OUT std_logic_vector(40-1 DOWNTO 0); - FULL : OUT std_logic; - EMPTY : OUT std_logic); - -end fifo_xlnx_16x40_2clk_exdes; - - - -architecture xilinx of fifo_xlnx_16x40_2clk_exdes is - - signal wr_clk_i : std_logic; - signal rd_clk_i : std_logic; - - - - component fifo_xlnx_16x40_2clk is - PORT ( - WR_CLK : IN std_logic; - RD_CLK : IN std_logic; - RST : IN std_logic; - WR_EN : IN std_logic; - RD_EN : IN std_logic; - DIN : IN std_logic_vector(40-1 DOWNTO 0); - DOUT : OUT std_logic_vector(40-1 DOWNTO 0); - FULL : OUT std_logic; - EMPTY : OUT std_logic); - - end component; - - -begin - - wr_clk_buf: bufg - PORT map( - i => WR_CLK, - o => wr_clk_i - ); - - rd_clk_buf: bufg - PORT map( - i => RD_CLK, - o => rd_clk_i - ); - - - exdes_inst : fifo_xlnx_16x40_2clk - PORT MAP ( - WR_CLK => wr_clk_i, - RD_CLK => rd_clk_i, - RST => rst, - WR_EN => wr_en, - RD_EN => rd_en, - DIN => din, - DOUT => dout, - FULL => full, - EMPTY => empty); - -end xilinx; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/fifo_generator_v9_3_readme.txt deleted file mode 100644 index 7853ebde8..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/fifo_generator_v9_3_readme.txt +++ /dev/null @@ -1,236 +0,0 @@ -CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 - - Release Date: December 18, 2012 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm - -................................................................................ - - -2. DEVICE SUPPORT - - - 2.1 ISE - - The following device families are supported by the core for this release. - - - All 7 Series devices - Zynq-7000 devices - All Virtex-6 devices - All Spartan-6 devices - All Virtex-5 devices - All Spartan-3 devices - All Virtex-4 devices - - - 2.2 Vivado - - All 7 Series devices - Zynq-7000 devices - -................................................................................ - - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - ISE 14.4 software support - - - 3.2 Vivado - - - 2012.4 software support - - IP level constraint for Built-in FIFO reset synchronizer - -................................................................................ - - -4. RESOLVED ISSUES - - - 4.1 ISE - - - N/A - - - 4.2 Vivado - - - N/A - - -................................................................................ - - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - The following are known issues for v9.3 Rev 1 of this core at time of release: - - 1. Importing an XCO file alters the XCO configurations - - Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) - into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, - page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. - - CR 467240 - AR 31379 - - 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed - - Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, - correct behavior of the FIFO status flags cannot be guaranteed after the first write. - - Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. - For more information and additional workaround see Answer Record 41099. - - 5.2 Vivado - - The following are known issues for v9.3 Rev 1 of this core at time of release: - - 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen - ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. - - CR 665836 - -The most recent information, including known issues, workarounds, and -resolutions for this version is provided in the IP Release Notes User Guide -located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -................................................................................ - - -6. TECHNICAL SUPPORT & FEEDBACK - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - -................................................................................ - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer -10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO -07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO -04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support - AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO -01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support -10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support -06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support -03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support -10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support -09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support -07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support -06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support -04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support -12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support -09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support -06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support -04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support -09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes -03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes -10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs -08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO -04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support -09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support -07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support -01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 -08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 -04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 -11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 -05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support -04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release -================================================================================ - -................................................................................ - - -8. LEGAL DISCLAIMER - -(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement.bat deleted file mode 100755 index c177929f4..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement.bat +++ /dev/null @@ -1,88 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -copy fifo_xlnx_16x40_2clk_exdes.ngc .\results\ - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\fifo_xlnx_16x40_2clk.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\fifo_xlnx_16x40_2clk_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ fifo_xlnx_16x40_2clk_exdes - -echo 'Running map' -map fifo_xlnx_16x40_2clk_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm fifo_xlnx_16x40_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement.sh deleted file mode 100755 index 5bf9e8207..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with XST'; -xst -ifn xst.scr -cp fifo_xlnx_16x40_2clk_exdes.ngc ./results/ - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../fifo_xlnx_16x40_2clk.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/fifo_xlnx_16x40_2clk_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ fifo_xlnx_16x40_2clk_exdes - -echo 'Running map' -map fifo_xlnx_16x40_2clk_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm fifo_xlnx_16x40_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement_synplify.bat deleted file mode 100755 index eb1fea980..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement_synplify.bat +++ /dev/null @@ -1,87 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -rem Clean up the results directory -rmdir /S /Q results -mkdir results - -rem Synthesize the VHDL Wrapper Files - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -rem Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -copy ..\..\fifo_xlnx_16x40_2clk.ngc results\ - - -rem Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -copy ..\example_design\fifo_xlnx_16x40_2clk_exdes.ucf results\ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ fifo_xlnx_16x40_2clk_exdes - -echo 'Running map' -map fifo_xlnx_16x40_2clk_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm fifo_xlnx_16x40_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement_synplify.sh deleted file mode 100755 index 2ea5c086b..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/implement_synplify.sh +++ /dev/null @@ -1,86 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -# Clean up the results directory -rm -rf results -mkdir results - -#Synthesize the Wrapper Files - -echo 'Synthesizing example design with Synplify' -synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx - - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../fifo_xlnx_16x40_2clk.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/fifo_xlnx_16x40_2clk_exdes.ucf results/ - -cd results - -echo 'Running ngdbuild' - -ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ fifo_xlnx_16x40_2clk_exdes - -echo 'Running map' -map fifo_xlnx_16x40_2clk_exdes -o mapped.ncd - -echo 'Running par' -par mapped.ncd routed.ncd - -echo 'Running trce' -trce -e 10 routed.ncd mapped.pcf -o routed - -echo 'Running design through bitgen' -bitgen -w routed -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -sim -tm fifo_xlnx_16x40_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.bat deleted file mode 100755 index c3929caff..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.bat +++ /dev/null @@ -1,54 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -rem ----------------------------------------------------------------------------- -rem Script to synthesize and implement the Coregen FIFO Generator -rem ----------------------------------------------------------------------------- -rmdir /S /Q results -mkdir results -cd results -copy ..\..\..\fifo_xlnx_16x40_2clk.ngc . -planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.sh deleted file mode 100755 index ffc39b34a..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.sh +++ /dev/null @@ -1,55 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - -#----------------------------------------------------------------------------- -# Script to synthesize and implement the Coregen FIFO Generator -#----------------------------------------------------------------------------- -rm -rf results -mkdir results -cd results -cp ../../../fifo_xlnx_16x40_2clk.ngc . -planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.tcl deleted file mode 100755 index 298595cfd..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/planAhead_ise.tcl +++ /dev/null @@ -1,67 +0,0 @@ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - - -set device xc7k410tffg900-2 -set projName fifo_xlnx_16x40_2clk -set design fifo_xlnx_16x40_2clk -set projDir [file dirname [info script]] -create_project $projName $projDir/results/$projName -part $device -force -set_property design_mode RTL [current_fileset -srcset] -set top_module fifo_xlnx_16x40_2clk_exdes -add_files -norecurse {../../example_design/fifo_xlnx_16x40_2clk_exdes.vhd} -add_files -norecurse {./fifo_xlnx_16x40_2clk.ngc} -import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_xlnx_16x40_2clk_exdes.xdc} -set_property top fifo_xlnx_16x40_2clk_exdes [get_property srcset [current_run]] -synth_design -opt_design -place_design -route_design -write_sdf -rename_top_module fifo_xlnx_16x40_2clk_exdes -file routed.sdf -write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_xlnx_16x40_2clk_exdes routed.v -report_timing -nworst 30 -path_type full -file routed.twr -report_drc -file report.drc -write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/xst.prj b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/xst.prj deleted file mode 100755 index ff8591659..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/xst.prj +++ /dev/null @@ -1 +0,0 @@ -work ../example_design/fifo_xlnx_16x40_2clk_exdes.vhd diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/xst.scr b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/xst.scr deleted file mode 100755 index 2687f3926..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/implement/xst.scr +++ /dev/null @@ -1,13 +0,0 @@ -run --ifmt VHDL --ent fifo_xlnx_16x40_2clk_exdes --p xc7k410t-ffg900-2 --ifn xst.prj --write_timing_constraints No --iobuf YES --max_fanout 100 --ofn fifo_xlnx_16x40_2clk_exdes --ofmt NGC --bus_delimiter () --hierarchy_separator / --case Maintain diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dgen.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dgen.vhd deleted file mode 100755 index 7621dbfbe..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dgen.vhd +++ /dev/null @@ -1,123 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_dgen.vhd --- --- Description: --- Used for write interface stimulus generation --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE IEEE.std_logic_arith.all; -USE IEEE.std_logic_misc.all; - -LIBRARY work; -USE work.fifo_xlnx_16x40_2clk_pkg.ALL; - -ENTITY fifo_xlnx_16x40_2clk_dgen IS - GENERIC ( - C_DIN_WIDTH : INTEGER := 32; - C_DOUT_WIDTH : INTEGER := 32; - C_CH_TYPE : INTEGER := 0; - TB_SEED : INTEGER := 2 - ); - PORT ( - RESET : IN STD_LOGIC; - WR_CLK : IN STD_LOGIC; - PRC_WR_EN : IN STD_LOGIC; - FULL : IN STD_LOGIC; - WR_EN : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) - ); -END ENTITY; - - -ARCHITECTURE fg_dg_arch OF fifo_xlnx_16x40_2clk_dgen IS - - CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); - CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); - - SIGNAL pr_w_en : STD_LOGIC := '0'; - SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); - SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); - BEGIN - - WR_EN <= PRC_WR_EN ; - WR_DATA <= wr_data_i AFTER 100 ns; - - ---------------------------------------------- - -- Generation of DATA - ---------------------------------------------- - gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE - rd_gen_inst1:fifo_xlnx_16x40_2clk_rng - GENERIC MAP( - WIDTH => 8, - SEED => TB_SEED+N - ) - PORT MAP( - CLK => WR_CLK, - RESET => RESET, - RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), - ENABLE => pr_w_en - ); - END GENERATE; - - pr_w_en <= PRC_WR_EN AND NOT FULL; - wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); - - -END ARCHITECTURE; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dverif.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dverif.vhd deleted file mode 100755 index 8f69c683a..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dverif.vhd +++ /dev/null @@ -1,150 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_dverif.vhd --- --- Description: --- Used for FIFO read interface stimulus generation and data checking --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE IEEE.std_logic_arith.all; -USE IEEE.std_logic_misc.all; - -LIBRARY work; -USE work.fifo_xlnx_16x40_2clk_pkg.ALL; - -ENTITY fifo_xlnx_16x40_2clk_dverif IS - GENERIC( - C_DIN_WIDTH : INTEGER := 0; - C_DOUT_WIDTH : INTEGER := 0; - C_USE_EMBEDDED_REG : INTEGER := 0; - C_CH_TYPE : INTEGER := 0; - TB_SEED : INTEGER := 2 - ); - PORT( - RESET : IN STD_LOGIC; - RD_CLK : IN STD_LOGIC; - PRC_RD_EN : IN STD_LOGIC; - EMPTY : IN STD_LOGIC; - DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); - RD_EN : OUT STD_LOGIC; - DOUT_CHK : OUT STD_LOGIC - ); -END ENTITY; - - -ARCHITECTURE fg_dv_arch OF fifo_xlnx_16x40_2clk_dverif IS - - CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); - CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); - CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); - - SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_chk : STD_LOGIC := '1'; - SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); - SIGNAL rd_en_i : STD_LOGIC := '0'; - SIGNAL pr_r_en : STD_LOGIC := '0'; - SIGNAL rd_en_d1 : STD_LOGIC := '1'; -BEGIN - - - DOUT_CHK <= data_chk; - RD_EN <= rd_en_i; - rd_en_i <= PRC_RD_EN; - rd_en_d1 <= '1'; - - - data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE - ------------------------------------------------------- - -- Expected data generation and checking for data_fifo - ------------------------------------------------------- - - pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; - expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); - - gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE - rd_gen_inst2:fifo_xlnx_16x40_2clk_rng - GENERIC MAP( - WIDTH => 8, - SEED => TB_SEED+N - ) - PORT MAP( - CLK => RD_CLK, - RESET => RESET, - RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), - ENABLE => pr_r_en - ); - END GENERATE; - - PROCESS (RD_CLK,RESET) - BEGIN - IF(RESET = '1') THEN - data_chk <= '0'; - ELSIF (RD_CLK'event AND RD_CLK='1') THEN - IF(EMPTY = '0') THEN - IF(DATA_OUT = expected_dout) THEN - data_chk <= '0'; - ELSE - data_chk <= '1'; - END IF; - END IF; - END IF; - END PROCESS; - END GENERATE data_fifo_chk; - -END ARCHITECTURE; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pctrl.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pctrl.vhd deleted file mode 100755 index f48c1a1f0..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pctrl.vhd +++ /dev/null @@ -1,541 +0,0 @@ - --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_pctrl.vhd --- --- Description: --- Used for protocol control on write and read interface stimulus and status generation --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE IEEE.std_logic_arith.all; -USE IEEE.std_logic_misc.all; - -LIBRARY work; -USE work.fifo_xlnx_16x40_2clk_pkg.ALL; - -ENTITY fifo_xlnx_16x40_2clk_pctrl IS - GENERIC( - AXI_CHANNEL : STRING :="NONE"; - C_APPLICATION_TYPE : INTEGER := 0; - C_DIN_WIDTH : INTEGER := 0; - C_DOUT_WIDTH : INTEGER := 0; - C_WR_PNTR_WIDTH : INTEGER := 0; - C_RD_PNTR_WIDTH : INTEGER := 0; - C_CH_TYPE : INTEGER := 0; - FREEZEON_ERROR : INTEGER := 0; - TB_STOP_CNT : INTEGER := 2; - TB_SEED : INTEGER := 2 - ); - PORT( - RESET_WR : IN STD_LOGIC; - RESET_RD : IN STD_LOGIC; - WR_CLK : IN STD_LOGIC; - RD_CLK : IN STD_LOGIC; - FULL : IN STD_LOGIC; - EMPTY : IN STD_LOGIC; - ALMOST_FULL : IN STD_LOGIC; - ALMOST_EMPTY : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); - DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); - DOUT_CHK : IN STD_LOGIC; - PRC_WR_EN : OUT STD_LOGIC; - PRC_RD_EN : OUT STD_LOGIC; - RESET_EN : OUT STD_LOGIC; - SIM_DONE : OUT STD_LOGIC; - STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END ENTITY; - - -ARCHITECTURE fg_pc_arch OF fifo_xlnx_16x40_2clk_pctrl IS - - CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); - CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); - CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); - - SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); - SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); - SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); - SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); - SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); - SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); - SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); - SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); - SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); - SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); - SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); - SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); - SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); - SIGNAL wr_en_i : STD_LOGIC := '0'; - SIGNAL rd_en_i : STD_LOGIC := '0'; - SIGNAL state : STD_LOGIC := '0'; - SIGNAL wr_control : STD_LOGIC := '0'; - SIGNAL rd_control : STD_LOGIC := '0'; - SIGNAL stop_on_err : STD_LOGIC := '0'; - SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); - SIGNAL sim_done_i : STD_LOGIC := '0'; - SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); - SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); - SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); - SIGNAL prc_we_i : STD_LOGIC := '0'; - SIGNAL prc_re_i : STD_LOGIC := '0'; - SIGNAL reset_en_i : STD_LOGIC := '0'; - SIGNAL sim_done_d1 : STD_LOGIC := '0'; - SIGNAL sim_done_wr1 : STD_LOGIC := '0'; - SIGNAL sim_done_wr2 : STD_LOGIC := '0'; - SIGNAL empty_d1 : STD_LOGIC := '0'; - SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; - SIGNAL state_d1 : STD_LOGIC := '0'; - SIGNAL state_rd_dom1 : STD_LOGIC := '0'; - SIGNAL rd_en_d1 : STD_LOGIC := '0'; - SIGNAL rd_en_wr1 : STD_LOGIC := '0'; - SIGNAL wr_en_d1 : STD_LOGIC := '0'; - SIGNAL wr_en_rd1 : STD_LOGIC := '0'; - SIGNAL full_chk_d1 : STD_LOGIC := '0'; - SIGNAL full_chk_rd1 : STD_LOGIC := '0'; - SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; - - SIGNAL state_rd_dom2 : STD_LOGIC := '0'; - SIGNAL state_rd_dom3 : STD_LOGIC := '0'; - SIGNAL rd_en_wr2 : STD_LOGIC := '0'; - SIGNAL wr_en_rd2 : STD_LOGIC := '0'; - SIGNAL full_chk_rd2 : STD_LOGIC := '0'; - SIGNAL reset_en_d1 : STD_LOGIC := '0'; - SIGNAL reset_en_rd1 : STD_LOGIC := '0'; - SIGNAL reset_en_rd2 : STD_LOGIC := '0'; - - SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; - SIGNAL data_chk_rd1 : STD_LOGIC := '0'; - SIGNAL data_chk_rd2 : STD_LOGIC := '0'; - SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); - SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); -BEGIN - status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; - STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); - - prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; - prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; - - SIM_DONE <= sim_done_i; - rdw_gt_wrw <= (OTHERS => '1'); - wrw_gt_rdw <= (OTHERS => '1'); - - PROCESS(RD_CLK) - BEGIN - IF (RD_CLK'event AND RD_CLK='1') THEN - IF(prc_re_i = '1') THEN - rd_activ_cont <= rd_activ_cont + "1"; - END IF; - END IF; - END PROCESS; - - - PROCESS(sim_done_i) - BEGIN - assert sim_done_i = '0' - report "Simulation Complete for:" & AXI_CHANNEL - severity note; - END PROCESS; - ------------------------------------------------------ --- SIM_DONE SIGNAL GENERATION ------------------------------------------------------ -PROCESS (RD_CLK,RESET_RD) -BEGIN - IF(RESET_RD = '1') THEN - --sim_done_i <= '0'; - ELSIF(RD_CLK'event AND RD_CLK='1') THEN - IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN - sim_done_i <= '1'; - END IF; - END IF; -END PROCESS; - - -- TB Timeout/Stop - fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE - PROCESS (RD_CLK) - BEGIN - IF (RD_CLK'event AND RD_CLK='1') THEN - IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN - sim_stop_cntr <= sim_stop_cntr - "1"; - END IF; - END IF; - END PROCESS; - END GENERATE fifo_tb_stop_run; - - - -- Stop when error found - PROCESS (RD_CLK) - BEGIN - IF (RD_CLK'event AND RD_CLK='1') THEN - IF(sim_done_i = '0') THEN - status_d1_i <= status_i OR status_d1_i; - END IF; - IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN - stop_on_err <= '1'; - END IF; - END IF; - END PROCESS; - ----------------------------------------------------- - - ----------------------------------------------------- - -- CHECKS FOR FIFO - ----------------------------------------------------- - - - PROCESS(RD_CLK,RESET_RD) - BEGIN - IF(RESET_RD = '1') THEN - post_rst_dly_rd <= (OTHERS => '1'); - ELSIF (RD_CLK'event AND RD_CLK='1') THEN - post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); - END IF; - END PROCESS; - - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - post_rst_dly_wr <= (OTHERS => '1'); - ELSIF (WR_CLK'event AND WR_CLK='1') THEN - post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); - END IF; - END PROCESS; - - - -- FULL de-assert Counter - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - full_ds_timeout <= (OTHERS => '0'); - ELSIF(WR_CLK'event AND WR_CLK='1') THEN - IF(state = '1') THEN - IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN - full_ds_timeout <= full_ds_timeout + '1'; - END IF; - ELSE - full_ds_timeout <= (OTHERS => '0'); - END IF; - END IF; - END PROCESS; - - - -- EMPTY deassert counter - PROCESS(RD_CLK,RESET_RD) - BEGIN - IF(RESET_RD = '1') THEN - empty_ds_timeout <= (OTHERS => '0'); - ELSIF(RD_CLK'event AND RD_CLK='1') THEN - IF(state = '0') THEN - IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN - empty_ds_timeout <= empty_ds_timeout + '1'; - END IF; - ELSE - empty_ds_timeout <= (OTHERS => '0'); - END IF; - END IF; - END PROCESS; - - -- Full check signal generation - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - full_chk_i <= '0'; - ELSIF(WR_CLK'event AND WR_CLK='1') THEN - IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN - full_chk_i <= '0'; - ELSE - full_chk_i <= AND_REDUCE(full_as_timeout) OR - AND_REDUCE(full_ds_timeout); - END IF; - END IF; - END PROCESS; - - -- Empty checks - PROCESS(RD_CLK,RESET_RD) - BEGIN - IF(RESET_RD = '1') THEN - empty_chk_i <= '0'; - ELSIF(RD_CLK'event AND RD_CLK='1') THEN - IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN - empty_chk_i <= '0'; - ELSE - empty_chk_i <= AND_REDUCE(empty_as_timeout) OR - AND_REDUCE(empty_ds_timeout); - END IF; - END IF; - END PROCESS; - - fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE - PRC_WR_EN <= prc_we_i AFTER 100 ns; - PRC_RD_EN <= prc_re_i AFTER 50 ns; - data_chk_i <= dout_chk; - END GENERATE fifo_d_chk; - ----------------------------------------------------- - - - ----------------------------------------------------- - -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS - ----------------------------------------------------- - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - empty_wr_dom1 <= '1'; - empty_wr_dom2 <= '1'; - state_d1 <= '0'; - wr_en_d1 <= '0'; - rd_en_wr1 <= '0'; - rd_en_wr2 <= '0'; - full_chk_d1 <= '0'; - reset_en_d1 <= '0'; - sim_done_wr1 <= '0'; - sim_done_wr2 <= '0'; - ELSIF (WR_CLK'event AND WR_CLK='1') THEN - sim_done_wr1 <= sim_done_d1; - sim_done_wr2 <= sim_done_wr1; - reset_en_d1 <= reset_en_i; - state_d1 <= state; - empty_wr_dom1 <= empty_d1; - empty_wr_dom2 <= empty_wr_dom1; - wr_en_d1 <= wr_en_i; - rd_en_wr1 <= rd_en_d1; - rd_en_wr2 <= rd_en_wr1; - full_chk_d1 <= full_chk_i; - END IF; - END PROCESS; - - PROCESS(RD_CLK,RESET_RD) - BEGIN - IF(RESET_RD = '1') THEN - empty_d1 <= '1'; - state_rd_dom1 <= '0'; - state_rd_dom2 <= '0'; - state_rd_dom3 <= '0'; - wr_en_rd1 <= '0'; - wr_en_rd2 <= '0'; - rd_en_d1 <= '0'; - full_chk_rd1 <= '0'; - full_chk_rd2 <= '0'; - reset_en_rd1 <= '0'; - reset_en_rd2 <= '0'; - sim_done_d1 <= '0'; - ELSIF (RD_CLK'event AND RD_CLK='1') THEN - sim_done_d1 <= sim_done_i; - reset_en_rd1 <= reset_en_d1; - reset_en_rd2 <= reset_en_rd1; - empty_d1 <= EMPTY; - rd_en_d1 <= rd_en_i; - state_rd_dom1 <= state_d1; - state_rd_dom2 <= state_rd_dom1; - state_rd_dom3 <= state_rd_dom2; - wr_en_rd1 <= wr_en_d1; - wr_en_rd2 <= wr_en_rd1; - full_chk_rd1 <= full_chk_d1; - full_chk_rd2 <= full_chk_rd1; - END IF; - END PROCESS; - - RESET_EN <= reset_en_rd2; - - - data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE - ----------------------------------------------------- - -- WR_EN GENERATION - ----------------------------------------------------- - gen_rand_wr_en:fifo_xlnx_16x40_2clk_rng - GENERIC MAP( - WIDTH => 8, - SEED => TB_SEED+1 - ) - PORT MAP( - CLK => WR_CLK, - RESET => RESET_WR, - RANDOM_NUM => wr_en_gen, - ENABLE => '1' - ); - - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - wr_en_i <= '0'; - ELSIF(WR_CLK'event AND WR_CLK='1') THEN - IF(state = '1') THEN - wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; - ELSE - wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------- - -- WR_EN CONTROL - ----------------------------------------------------- - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - wr_cntr <= (OTHERS => '0'); - wr_control <= '1'; - full_as_timeout <= (OTHERS => '0'); - ELSIF(WR_CLK'event AND WR_CLK='1') THEN - IF(state = '1') THEN - IF(wr_en_i = '1') THEN - wr_cntr <= wr_cntr + "1"; - END IF; - full_as_timeout <= (OTHERS => '0'); - ELSE - wr_cntr <= (OTHERS => '0'); - IF(rd_en_wr2 = '0') THEN - IF(wr_en_i = '1') THEN - full_as_timeout <= full_as_timeout + "1"; - END IF; - ELSE - full_as_timeout <= (OTHERS => '0'); - END IF; - END IF; - - wr_control <= NOT wr_cntr(wr_cntr'high); - - END IF; - END PROCESS; - - ----------------------------------------------------- - -- RD_EN GENERATION - ----------------------------------------------------- - gen_rand_rd_en:fifo_xlnx_16x40_2clk_rng - GENERIC MAP( - WIDTH => 8, - SEED => TB_SEED - ) - PORT MAP( - CLK => RD_CLK, - RESET => RESET_RD, - RANDOM_NUM => rd_en_gen, - ENABLE => '1' - ); - - PROCESS(RD_CLK,RESET_RD) - BEGIN - IF(RESET_RD = '1') THEN - rd_en_i <= '0'; - ELSIF(RD_CLK'event AND RD_CLK='1') THEN - IF(state_rd_dom2 = '0') THEN - rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); - ELSE - rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------- - -- RD_EN CONTROL - ----------------------------------------------------- - PROCESS(RD_CLK,RESET_RD) - BEGIN - IF(RESET_RD = '1') THEN - rd_cntr <= (OTHERS => '0'); - rd_control <= '1'; - empty_as_timeout <= (OTHERS => '0'); - ELSIF(RD_CLK'event AND RD_CLK='1') THEN - IF(state_rd_dom2 = '0') THEN - IF(rd_en_i = '1') THEN - rd_cntr <= rd_cntr + "1"; - END IF; - empty_as_timeout <= (OTHERS => '0'); - ELSE - rd_cntr <= (OTHERS => '0'); - IF(wr_en_rd2 = '0') THEN - IF(rd_en_i = '1') THEN - empty_as_timeout <= empty_as_timeout + "1"; - END IF; - ELSE - empty_as_timeout <= (OTHERS => '0'); - END IF; - END IF; - - rd_control <= NOT rd_cntr(rd_cntr'high); - - END IF; - END PROCESS; - - ----------------------------------------------------- - -- STIMULUS CONTROL - ----------------------------------------------------- - PROCESS(WR_CLK,RESET_WR) - BEGIN - IF(RESET_WR = '1') THEN - state <= '0'; - reset_en_i <= '0'; - ELSIF(WR_CLK'event AND WR_CLK='1') THEN - CASE state IS - WHEN '0' => - IF(FULL = '1' AND empty_wr_dom2 = '0') THEN - state <= '1'; - reset_en_i <= '0'; - END IF; - WHEN '1' => - IF(empty_wr_dom2 = '1' AND FULL = '0') THEN - state <= '0'; - reset_en_i <= '1'; - END IF; - WHEN OTHERS => state <= state; - END CASE; - END IF; - END PROCESS; - END GENERATE data_fifo_en; - -END ARCHITECTURE; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pkg.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pkg.vhd deleted file mode 100755 index 105a0879c..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pkg.vhd +++ /dev/null @@ -1,348 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_pkg.vhd --- --- Description: --- This is the demo testbench package file for FIFO Generator core. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE ieee.std_logic_arith.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -PACKAGE fifo_xlnx_16x40_2clk_pkg IS - - FUNCTION divroundup ( - data_value : INTEGER; - divisor : INTEGER) - RETURN INTEGER; - ------------------------ - FUNCTION if_then_else ( - condition : BOOLEAN; - true_case : INTEGER; - false_case : INTEGER) - RETURN INTEGER; - ------------------------ - FUNCTION if_then_else ( - condition : BOOLEAN; - true_case : STD_LOGIC; - false_case : STD_LOGIC) - RETURN STD_LOGIC; - ------------------------ - FUNCTION if_then_else ( - condition : BOOLEAN; - true_case : TIME; - false_case : TIME) - RETURN TIME; - ------------------------ - FUNCTION log2roundup ( - data_value : INTEGER) - RETURN INTEGER; - ------------------------ - FUNCTION hexstr_to_std_logic_vec( - arg1 : string; - size : integer ) - RETURN std_logic_vector; - ------------------------ - COMPONENT fifo_xlnx_16x40_2clk_rng IS - GENERIC (WIDTH : integer := 8; - SEED : integer := 3); - PORT ( - CLK : IN STD_LOGIC; - RESET : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) - ); - END COMPONENT; - ------------------------ - - COMPONENT fifo_xlnx_16x40_2clk_dgen IS - GENERIC ( - C_DIN_WIDTH : INTEGER := 32; - C_DOUT_WIDTH : INTEGER := 32; - C_CH_TYPE : INTEGER := 0; - TB_SEED : INTEGER := 2 - ); - PORT ( - RESET : IN STD_LOGIC; - WR_CLK : IN STD_LOGIC; - PRC_WR_EN : IN STD_LOGIC; - FULL : IN STD_LOGIC; - WR_EN : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) - ); - END COMPONENT; - ------------------------ - - COMPONENT fifo_xlnx_16x40_2clk_dverif IS - GENERIC( - C_DIN_WIDTH : INTEGER := 0; - C_DOUT_WIDTH : INTEGER := 0; - C_USE_EMBEDDED_REG : INTEGER := 0; - C_CH_TYPE : INTEGER := 0; - TB_SEED : INTEGER := 2 - ); - PORT( - RESET : IN STD_LOGIC; - RD_CLK : IN STD_LOGIC; - PRC_RD_EN : IN STD_LOGIC; - EMPTY : IN STD_LOGIC; - DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); - RD_EN : OUT STD_LOGIC; - DOUT_CHK : OUT STD_LOGIC - ); - END COMPONENT; - ------------------------ - - COMPONENT fifo_xlnx_16x40_2clk_pctrl IS - GENERIC( - AXI_CHANNEL : STRING := "NONE"; - C_APPLICATION_TYPE : INTEGER := 0; - C_DIN_WIDTH : INTEGER := 0; - C_DOUT_WIDTH : INTEGER := 0; - C_WR_PNTR_WIDTH : INTEGER := 0; - C_RD_PNTR_WIDTH : INTEGER := 0; - C_CH_TYPE : INTEGER := 0; - FREEZEON_ERROR : INTEGER := 0; - TB_STOP_CNT : INTEGER := 2; - TB_SEED : INTEGER := 2 - ); - PORT( - RESET_WR : IN STD_LOGIC; - RESET_RD : IN STD_LOGIC; - WR_CLK : IN STD_LOGIC; - RD_CLK : IN STD_LOGIC; - FULL : IN STD_LOGIC; - EMPTY : IN STD_LOGIC; - ALMOST_FULL : IN STD_LOGIC; - ALMOST_EMPTY : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); - DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); - DOUT_CHK : IN STD_LOGIC; - PRC_WR_EN : OUT STD_LOGIC; - PRC_RD_EN : OUT STD_LOGIC; - RESET_EN : OUT STD_LOGIC; - SIM_DONE : OUT STD_LOGIC; - STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); - END COMPONENT; - ------------------------ - COMPONENT fifo_xlnx_16x40_2clk_synth IS - GENERIC( - FREEZEON_ERROR : INTEGER := 0; - TB_STOP_CNT : INTEGER := 0; - TB_SEED : INTEGER := 1 - ); - PORT( - WR_CLK : IN STD_LOGIC; - RD_CLK : IN STD_LOGIC; - RESET : IN STD_LOGIC; - SIM_DONE : OUT STD_LOGIC; - STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); - END COMPONENT; - ------------------------ - COMPONENT fifo_xlnx_16x40_2clk_exdes IS - PORT ( - WR_CLK : IN std_logic; - RD_CLK : IN std_logic; - RST : IN std_logic; - WR_EN : IN std_logic; - RD_EN : IN std_logic; - DIN : IN std_logic_vector(40-1 DOWNTO 0); - DOUT : OUT std_logic_vector(40-1 DOWNTO 0); - FULL : OUT std_logic; - EMPTY : OUT std_logic); - - END COMPONENT; - ------------------------ - - -END fifo_xlnx_16x40_2clk_pkg; - - - -PACKAGE BODY fifo_xlnx_16x40_2clk_pkg IS - - FUNCTION divroundup ( - data_value : INTEGER; - divisor : INTEGER) - RETURN INTEGER IS - VARIABLE div : INTEGER; - BEGIN - div := data_value/divisor; - IF ( (data_value MOD divisor) /= 0) THEN - div := div+1; - END IF; - RETURN div; - END divroundup; - --------------------------------- - FUNCTION if_then_else ( - condition : BOOLEAN; - true_case : INTEGER; - false_case : INTEGER) - RETURN INTEGER IS - VARIABLE retval : INTEGER := 0; - BEGIN - IF condition=false THEN - retval:=false_case; - ELSE - retval:=true_case; - END IF; - RETURN retval; - END if_then_else; - --------------------------------- - FUNCTION if_then_else ( - condition : BOOLEAN; - true_case : STD_LOGIC; - false_case : STD_LOGIC) - RETURN STD_LOGIC IS - VARIABLE retval : STD_LOGIC := '0'; - BEGIN - IF condition=false THEN - retval:=false_case; - ELSE - retval:=true_case; - END IF; - RETURN retval; - END if_then_else; - --------------------------------- - FUNCTION if_then_else ( - condition : BOOLEAN; - true_case : TIME; - false_case : TIME) - RETURN TIME IS - VARIABLE retval : TIME := 0 ps; - BEGIN - IF condition=false THEN - retval:=false_case; - ELSE - retval:=true_case; - END IF; - RETURN retval; - END if_then_else; - ------------------------------- - FUNCTION log2roundup ( - data_value : INTEGER) - RETURN INTEGER IS - - VARIABLE width : INTEGER := 0; - VARIABLE cnt : INTEGER := 1; - BEGIN - IF (data_value <= 1) THEN - width := 1; - ELSE - WHILE (cnt < data_value) LOOP - width := width + 1; - cnt := cnt *2; - END LOOP; - END IF; - - RETURN width; - END log2roundup; - ------------------------------------------------------------------------------ - -- hexstr_to_std_logic_vec - -- This function converts a hex string to a std_logic_vector - ------------------------------------------------------------------------------ - FUNCTION hexstr_to_std_logic_vec( - arg1 : string; - size : integer ) - RETURN std_logic_vector IS - VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); - VARIABLE bin : std_logic_vector(3 DOWNTO 0); - VARIABLE index : integer := 0; - BEGIN - FOR i IN arg1'reverse_range LOOP - CASE arg1(i) IS - WHEN '0' => bin := (OTHERS => '0'); - WHEN '1' => bin := (0 => '1', OTHERS => '0'); - WHEN '2' => bin := (1 => '1', OTHERS => '0'); - WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); - WHEN '4' => bin := (2 => '1', OTHERS => '0'); - WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); - WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); - WHEN '7' => bin := (3 => '0', OTHERS => '1'); - WHEN '8' => bin := (3 => '1', OTHERS => '0'); - WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); - WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); - WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); - WHEN 'B' => bin := (2 => '0', OTHERS => '1'); - WHEN 'b' => bin := (2 => '0', OTHERS => '1'); - WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); - WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); - WHEN 'D' => bin := (1 => '0', OTHERS => '1'); - WHEN 'd' => bin := (1 => '0', OTHERS => '1'); - WHEN 'E' => bin := (0 => '0', OTHERS => '1'); - WHEN 'e' => bin := (0 => '0', OTHERS => '1'); - WHEN 'F' => bin := (OTHERS => '1'); - WHEN 'f' => bin := (OTHERS => '1'); - WHEN OTHERS => - FOR j IN 0 TO 3 LOOP - bin(j) := 'X'; - END LOOP; - END CASE; - FOR j IN 0 TO 3 LOOP - IF (index*4)+j < size THEN - result((index*4)+j) := bin(j); - END IF; - END LOOP; - index := index + 1; - END LOOP; - RETURN result; - END hexstr_to_std_logic_vec; - -END fifo_xlnx_16x40_2clk_pkg; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_rng.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_rng.vhd deleted file mode 100755 index 1a89db016..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_rng.vhd +++ /dev/null @@ -1,100 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_rng.vhd --- --- Description: --- Used for generation of pseudo random numbers --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE IEEE.std_logic_arith.all; -USE IEEE.std_logic_misc.all; - -ENTITY fifo_xlnx_16x40_2clk_rng IS - GENERIC ( - WIDTH : integer := 8; - SEED : integer := 3); - PORT ( - CLK : IN STD_LOGIC; - RESET : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); -END ENTITY; - -ARCHITECTURE rg_arch OF fifo_xlnx_16x40_2clk_rng IS -BEGIN -PROCESS (CLK,RESET) - VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); - VARIABLE temp : STD_LOGIC := '0'; -BEGIN - IF(RESET = '1') THEN - rand_temp := conv_std_logic_vector(SEED,width); - temp := '0'; - ELSIF (CLK'event AND CLK = '1') THEN - IF (ENABLE = '1') THEN - temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); - rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); - rand_temp(0) := temp; - END IF; - END IF; - - RANDOM_NUM <= rand_temp; - -END PROCESS; - -END ARCHITECTURE; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_synth.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_synth.vhd deleted file mode 100755 index b39c15125..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_synth.vhd +++ /dev/null @@ -1,296 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_synth.vhd --- --- Description: --- This is the demo testbench for fifo_generator core. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.STD_LOGIC_1164.ALL; -USE ieee.STD_LOGIC_unsigned.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE ieee.numeric_std.ALL; -USE ieee.STD_LOGIC_misc.ALL; - -LIBRARY std; -USE std.textio.ALL; - -LIBRARY work; -USE work.fifo_xlnx_16x40_2clk_pkg.ALL; - --------------------------------------------------------------------------------- --- Entity Declaration --------------------------------------------------------------------------------- -ENTITY fifo_xlnx_16x40_2clk_synth IS - GENERIC( - FREEZEON_ERROR : INTEGER := 0; - TB_STOP_CNT : INTEGER := 0; - TB_SEED : INTEGER := 1 - ); - PORT( - WR_CLK : IN STD_LOGIC; - RD_CLK : IN STD_LOGIC; - RESET : IN STD_LOGIC; - SIM_DONE : OUT STD_LOGIC; - STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END ENTITY; - -ARCHITECTURE simulation_arch OF fifo_xlnx_16x40_2clk_synth IS - - -- FIFO interface signal declarations - SIGNAL wr_clk_i : STD_LOGIC; - SIGNAL rd_clk_i : STD_LOGIC; - SIGNAL rst : STD_LOGIC; - SIGNAL wr_en : STD_LOGIC; - SIGNAL rd_en : STD_LOGIC; - SIGNAL din : STD_LOGIC_VECTOR(40-1 DOWNTO 0); - SIGNAL dout : STD_LOGIC_VECTOR(40-1 DOWNTO 0); - SIGNAL full : STD_LOGIC; - SIGNAL empty : STD_LOGIC; - -- TB Signals - SIGNAL wr_data : STD_LOGIC_VECTOR(40-1 DOWNTO 0); - SIGNAL dout_i : STD_LOGIC_VECTOR(40-1 DOWNTO 0); - SIGNAL wr_en_i : STD_LOGIC := '0'; - SIGNAL rd_en_i : STD_LOGIC := '0'; - SIGNAL full_i : STD_LOGIC := '0'; - SIGNAL empty_i : STD_LOGIC := '0'; - SIGNAL almost_full_i : STD_LOGIC := '0'; - SIGNAL almost_empty_i : STD_LOGIC := '0'; - SIGNAL prc_we_i : STD_LOGIC := '0'; - SIGNAL prc_re_i : STD_LOGIC := '0'; - SIGNAL dout_chk_i : STD_LOGIC := '0'; - SIGNAL rst_int_rd : STD_LOGIC := '0'; - SIGNAL rst_int_wr : STD_LOGIC := '0'; - SIGNAL rst_s_wr1 : STD_LOGIC := '0'; - SIGNAL rst_s_wr2 : STD_LOGIC := '0'; - SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL rst_s_wr3 : STD_LOGIC := '0'; - SIGNAL rst_s_rd : STD_LOGIC := '0'; - SIGNAL reset_en : STD_LOGIC := '0'; - SIGNAL rst_async_wr1 : STD_LOGIC := '0'; - SIGNAL rst_async_wr2 : STD_LOGIC := '0'; - SIGNAL rst_async_wr3 : STD_LOGIC := '0'; - SIGNAL rst_async_rd1 : STD_LOGIC := '0'; - SIGNAL rst_async_rd2 : STD_LOGIC := '0'; - SIGNAL rst_async_rd3 : STD_LOGIC := '0'; - - - BEGIN - - ---- Reset generation logic ----- - rst_int_wr <= rst_async_wr3 OR rst_s_wr3; - rst_int_rd <= rst_async_rd3 OR rst_s_rd; - - --Testbench reset synchronization - PROCESS(rd_clk_i,RESET) - BEGIN - IF(RESET = '1') THEN - rst_async_rd1 <= '1'; - rst_async_rd2 <= '1'; - rst_async_rd3 <= '1'; - ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN - rst_async_rd1 <= RESET; - rst_async_rd2 <= rst_async_rd1; - rst_async_rd3 <= rst_async_rd2; - END IF; - END PROCESS; - - PROCESS(wr_clk_i,RESET) - BEGIN - IF(RESET = '1') THEN - rst_async_wr1 <= '1'; - rst_async_wr2 <= '1'; - rst_async_wr3 <= '1'; - ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN - rst_async_wr1 <= RESET; - rst_async_wr2 <= rst_async_wr1; - rst_async_wr3 <= rst_async_wr2; - END IF; - END PROCESS; - - --Soft reset for core and testbench - PROCESS(rd_clk_i) - BEGIN - IF(rd_clk_i'event AND rd_clk_i='1') THEN - rst_gen_rd <= rst_gen_rd + "1"; - IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN - rst_s_rd <= '1'; - assert false - report "Reset applied..Memory Collision checks are not valid" - severity note; - ELSE - IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN - rst_s_rd <= '0'; - END IF; - END IF; - END IF; - END PROCESS; - - PROCESS(wr_clk_i) - BEGIN - IF(wr_clk_i'event AND wr_clk_i='1') THEN - rst_s_wr1 <= rst_s_rd; - rst_s_wr2 <= rst_s_wr1; - rst_s_wr3 <= rst_s_wr2; - IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN - assert false - report "Reset removed..Memory Collision checks are valid" - severity note; - END IF; - END IF; - END PROCESS; - ------------------ - - ---- Clock buffers for testbench ---- - wr_clk_i <= WR_CLK; - rd_clk_i <= RD_CLK; - ------------------ - - rst <= RESET OR rst_s_rd AFTER 12 ns; - din <= wr_data; - dout_i <= dout; - wr_en <= wr_en_i; - rd_en <= rd_en_i; - full_i <= full; - empty_i <= empty; - - fg_dg_nv: fifo_xlnx_16x40_2clk_dgen - GENERIC MAP ( - C_DIN_WIDTH => 40, - C_DOUT_WIDTH => 40, - TB_SEED => TB_SEED, - C_CH_TYPE => 0 - ) - PORT MAP ( -- Write Port - RESET => rst_int_wr, - WR_CLK => wr_clk_i, - PRC_WR_EN => prc_we_i, - FULL => full_i, - WR_EN => wr_en_i, - WR_DATA => wr_data - ); - - fg_dv_nv: fifo_xlnx_16x40_2clk_dverif - GENERIC MAP ( - C_DOUT_WIDTH => 40, - C_DIN_WIDTH => 40, - C_USE_EMBEDDED_REG => 0, - TB_SEED => TB_SEED, - C_CH_TYPE => 0 - ) - PORT MAP( - RESET => rst_int_rd, - RD_CLK => rd_clk_i, - PRC_RD_EN => prc_re_i, - RD_EN => rd_en_i, - EMPTY => empty_i, - DATA_OUT => dout_i, - DOUT_CHK => dout_chk_i - ); - - fg_pc_nv: fifo_xlnx_16x40_2clk_pctrl - GENERIC MAP ( - AXI_CHANNEL => "Native", - C_APPLICATION_TYPE => 0, - C_DOUT_WIDTH => 40, - C_DIN_WIDTH => 40, - C_WR_PNTR_WIDTH => 4, - C_RD_PNTR_WIDTH => 4, - C_CH_TYPE => 0, - FREEZEON_ERROR => FREEZEON_ERROR, - TB_SEED => TB_SEED, - TB_STOP_CNT => TB_STOP_CNT - ) - PORT MAP( - RESET_WR => rst_int_wr, - RESET_RD => rst_int_rd, - RESET_EN => reset_en, - WR_CLK => wr_clk_i, - RD_CLK => rd_clk_i, - PRC_WR_EN => prc_we_i, - PRC_RD_EN => prc_re_i, - FULL => full_i, - ALMOST_FULL => almost_full_i, - ALMOST_EMPTY => almost_empty_i, - DOUT_CHK => dout_chk_i, - EMPTY => empty_i, - DATA_IN => wr_data, - DATA_OUT => dout, - SIM_DONE => SIM_DONE, - STATUS => STATUS - ); - - - - - - fifo_xlnx_16x40_2clk_inst : fifo_xlnx_16x40_2clk_exdes - PORT MAP ( - WR_CLK => wr_clk_i, - RD_CLK => rd_clk_i, - RST => rst, - WR_EN => wr_en, - RD_EN => rd_en, - DIN => din, - DOUT => dout, - FULL => full, - EMPTY => empty); - -END ARCHITECTURE; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_tb.vhd b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_tb.vhd deleted file mode 100755 index ab6b21849..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_tb.vhd +++ /dev/null @@ -1,208 +0,0 @@ --------------------------------------------------------------------------------- --- --- FIFO Generator Core Demo Testbench --- --------------------------------------------------------------------------------- --- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- --- Filename: fifo_xlnx_16x40_2clk_tb.vhd --- --- Description: --- This is the demo testbench top file for fifo_generator core. --- --------------------------------------------------------------------------------- --- Library Declarations --------------------------------------------------------------------------------- -LIBRARY ieee; -LIBRARY std; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.ALL; -USE IEEE.std_logic_arith.ALL; -USE IEEE.std_logic_misc.ALL; -USE ieee.numeric_std.ALL; -USE ieee.std_logic_textio.ALL; -USE std.textio.ALL; - -LIBRARY work; -USE work.fifo_xlnx_16x40_2clk_pkg.ALL; - -ENTITY fifo_xlnx_16x40_2clk_tb IS -END ENTITY; - - -ARCHITECTURE fifo_xlnx_16x40_2clk_arch OF fifo_xlnx_16x40_2clk_tb IS - SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; - SIGNAL wr_clk : STD_LOGIC; - SIGNAL rd_clk : STD_LOGIC; - SIGNAL reset : STD_LOGIC; - SIGNAL sim_done : STD_LOGIC := '0'; - SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); - -- Write and Read clock periods - CONSTANT wr_clk_period_by_2 : TIME := 200 ns; - CONSTANT rd_clk_period_by_2 : TIME := 100 ns; - -- Procedures to display strings - PROCEDURE disp_str(CONSTANT str:IN STRING) IS - variable dp_l : line := null; - BEGIN - write(dp_l,str); - writeline(output,dp_l); - END PROCEDURE; - - PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS - variable dp_lx : line := null; - BEGIN - hwrite(dp_lx,hex); - writeline(output,dp_lx); - END PROCEDURE; - -BEGIN - - -- Generation of clock - - PROCESS BEGIN - WAIT FOR 400 ns; -- Wait for global reset - WHILE 1 = 1 LOOP - wr_clk <= '0'; - WAIT FOR wr_clk_period_by_2; - wr_clk <= '1'; - WAIT FOR wr_clk_period_by_2; - END LOOP; - END PROCESS; - - PROCESS BEGIN - WAIT FOR 200 ns;-- Wait for global reset - WHILE 1 = 1 LOOP - rd_clk <= '0'; - WAIT FOR rd_clk_period_by_2; - rd_clk <= '1'; - WAIT FOR rd_clk_period_by_2; - END LOOP; - END PROCESS; - - -- Generation of Reset - - PROCESS BEGIN - reset <= '1'; - WAIT FOR 4200 ns; - reset <= '0'; - WAIT; - END PROCESS; - - - -- Error message printing based on STATUS signal from fifo_xlnx_16x40_2clk_synth - - PROCESS(status) - BEGIN - IF(status /= "0" AND status /= "1") THEN - disp_str("STATUS:"); - disp_hex(status); - END IF; - - IF(status(7) = '1') THEN - assert false - report "Data mismatch found" - severity error; - END IF; - - IF(status(1) = '1') THEN - END IF; - - IF(status(5) = '1') THEN - assert false - report "Empty flag Mismatch/timeout" - severity error; - END IF; - - IF(status(6) = '1') THEN - assert false - report "Full Flag Mismatch/timeout" - severity error; - END IF; - END PROCESS; - - - PROCESS - BEGIN - wait until sim_done = '1'; - IF(status /= "0" AND status /= "1") THEN - assert false - report "Simulation failed" - severity failure; - ELSE - assert false - report "Test Completed Successfully" - severity failure; - END IF; - END PROCESS; - - PROCESS - BEGIN - wait for 400 ms; - assert false - report "Test bench timed out" - severity failure; - END PROCESS; - - -- Instance of fifo_xlnx_16x40_2clk_synth - - fifo_xlnx_16x40_2clk_synth_inst:fifo_xlnx_16x40_2clk_synth - GENERIC MAP( - FREEZEON_ERROR => 0, - TB_STOP_CNT => 2, - TB_SEED => 60 - ) - PORT MAP( - WR_CLK => wr_clk, - RD_CLK => rd_clk, - RESET => reset, - SIM_DONE => sim_done, - STATUS => status - ); - -END ARCHITECTURE; diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.bat deleted file mode 100755 index b8b9afdef..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.bat +++ /dev/null @@ -1,63 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogcomp -work work ..\\..\\..\\fifo_xlnx_16x40_2clk.v -vhpcomp -work work ..\\..\\example_design\\fifo_xlnx_16x40_2clk_exdes.vhd - -echo "Compiling Test Bench Files" -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_pkg.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_rng.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_dgen.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_dverif.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_pctrl.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_synth.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_tb.vhd - -vlogcomp -work work $XILINX\\verilog\\src\\glbl.v -fuse work.fifo_xlnx_16x40_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_xlnx_16x40_2clk_tb.exe - -.\\fifo_xlnx_16x40_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.sh deleted file mode 100755 index 8497d2bb8..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.sh +++ /dev/null @@ -1,65 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogcomp -work work ../../../fifo_xlnx_16x40_2clk.v -vhpcomp -work work ../../example_design/fifo_xlnx_16x40_2clk_exdes.vhd - -echo "Compiling Test Bench Files" -vhpcomp -work work ../fifo_xlnx_16x40_2clk_pkg.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_rng.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_dgen.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_dverif.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_pctrl.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_synth.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_tb.vhd - -vlogcomp -work work $XILINX/verilog/src/glbl.v -fuse work.fifo_xlnx_16x40_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_xlnx_16x40_2clk_tb.exe - -./fifo_xlnx_16x40_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.bat deleted file mode 100755 index 35375ce20..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.bat +++ /dev/null @@ -1,47 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.do deleted file mode 100755 index ceb06da3f..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,74 +0,0 @@ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -vlib work -vmap work work - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlog -work work ../../../fifo_xlnx_16x40_2clk.v -vcom -work work ../../example_design/fifo_xlnx_16x40_2clk_exdes.vhd - -echo "Compiling Test Bench Files" -vcom -work work ../fifo_xlnx_16x40_2clk_pkg.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_rng.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_dgen.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_dverif.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_pctrl.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_synth.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_tb.vhd - -vlog -work work $env(XILINX)/verilog/src/glbl.v -vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_xlnx_16x40_2clk_tb - -add log -r /* -do wave_mti.do -#Ignore integer warnings at time 0 -set StdArithNoWarnings 1 -run 0 -set StdArithNoWarnings 0 - -run -all diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.sh deleted file mode 100755 index edb1b0dd9..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.sh +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_ncsim.sh deleted file mode 100755 index 205637a9e..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -mkdir work - -echo "Compiling Core Verilog UNISIM/Behavioral model" -ncvlog -work work ../../../fifo_xlnx_16x40_2clk.v -ncvhdl -v93 -work work ../../example_design/fifo_xlnx_16x40_2clk_exdes.vhd - -echo "Compiling Test Bench Files" -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_pkg.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_rng.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_dgen.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_dverif.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_pctrl.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_synth.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_tb.vhd - -echo "Elaborating Design" -ncvlog -work work $XILINX/verilog/src/glbl.v -ncelab -access +rwc glbl work.fifo_xlnx_16x40_2clk_tb - -echo "Simulating Design" -ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_xlnx_16x40_2clk_tb - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_vcs.sh deleted file mode 100755 index 29e77ee91..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -rm -rf simv* csrc DVEfiles AN.DB - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogan +v2k ../../../fifo_xlnx_16x40_2clk.v -vhdlan ../../example_design/fifo_xlnx_16x40_2clk_exdes.vhd - -echo "Compiling Test Bench Files" -vhdlan ../fifo_xlnx_16x40_2clk_pkg.vhd -vhdlan ../fifo_xlnx_16x40_2clk_rng.vhd -vhdlan ../fifo_xlnx_16x40_2clk_dgen.vhd -vhdlan ../fifo_xlnx_16x40_2clk_dverif.vhd -vhdlan ../fifo_xlnx_16x40_2clk_pctrl.vhd -vhdlan ../fifo_xlnx_16x40_2clk_synth.vhd -vhdlan ../fifo_xlnx_16x40_2clk_tb.vhd - -echo "Elaborating Design" -vlogan +v2k $XILINX/verilog/src/glbl.v -vcs -time_res 1ps +vcs+lic+wait -debug fifo_xlnx_16x40_2clk_tb glbl - -echo "Simulating Design" -./simv -ucli -i ucli_commands.key -dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/ucli_commands.key deleted file mode 100755 index f468f1ade..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,4 +0,0 @@ -dump -file fifo_xlnx_16x40_2clk.vpd -type VPD -dump -add fifo_xlnx_16x40_2clk_tb -run -quit diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/vcs_session.tcl deleted file mode 100755 index 320dac215..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,77 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: vcs_session.tcl -# -# Description: -# This is the VCS wave form file. -# -#-------------------------------------------------------------------------------- -if { ![gui_is_db_opened -db {fifo_xlnx_16x40_2clk.vpd}] } { - gui_open_db -design V1 -file fifo_xlnx_16x40_2clk.vpd -nosource -} -gui_set_precision 1ps -gui_set_time_units 1ps - - -gui_open_window Wave -gui_sg_create fifo_xlnx_16x40_2clk_Group -gui_list_add_group -id Wave.1 {fifo_xlnx_16x40_2clk_Group} - -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group WRITE -divider -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group READ -divider -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_isim.tcl deleted file mode 100755 index 38fa5e088..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_isim.tcl +++ /dev/null @@ -1,68 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: wave_isim.tcl -# -# Description: -# This is the ISIM wave form file. -# -#-------------------------------------------------------------------------------- -wcfg new -isim set radix hex -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -run all -quit - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_mti.do deleted file mode 100755 index d553aecac..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_mti.do +++ /dev/null @@ -1,88 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. -# Filename: wave_mti.do -# -# Description: -# This is the modelsim wave form file. -# -#-------------------------------------------------------------------------------- - -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -add wave -noupdate -divider WRITE -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -add wave -noupdate -radix hexadecimal /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/DIN -add wave -noupdate -divider READ -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -add wave -noupdate -radix hexadecimal /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/DOUT - -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} -configure wave -namecolwidth 197 -configure wave -valuecolwidth 106 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_ncsim.sv deleted file mode 100755 index 827dc9825..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/functional/wave_ncsim.sv +++ /dev/null @@ -1,70 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: wave_ncsim.sv -# -# Description: -# This is the IUS wave form file. -# -#-------------------------------------------------------------------------------- - -window new WaveWindow -name "Waves for FIFO Generator Example Design" -waveform using "Waves for FIFO Generator Example Design" - -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -waveform add -label WRITE -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -waveform add -label READ -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.bat deleted file mode 100755 index 9a26bffb1..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.bat +++ /dev/null @@ -1,61 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogcomp -work work ..\\..\\implement\\results\\routed.v - -echo "Compiling Test Bench Files" -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_pkg.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_rng.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_dgen.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_dverif.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_pctrl.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_synth.vhd -vhpcomp -work work ..\\fifo_xlnx_16x40_2clk_tb.vhd - -fuse work.fifo_xlnx_16x40_2clk_tb work.glbl -L simprims_ver -o fifo_xlnx_16x40_2clk_tb.exe - -.\\fifo_xlnx_16x40_2clk_tb.exe -sdfmax /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.sh deleted file mode 100755 index b17c37433..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogcomp -work work ../../implement/results/routed.v - -echo "Compiling Test Bench Files" -vhpcomp -work work ../fifo_xlnx_16x40_2clk_pkg.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_rng.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_dgen.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_dverif.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_pctrl.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_synth.vhd -vhpcomp -work work ../fifo_xlnx_16x40_2clk_tb.vhd - -fuse work.fifo_xlnx_16x40_2clk_tb work.glbl -L simprims_ver -o fifo_xlnx_16x40_2clk_tb.exe - -./fifo_xlnx_16x40_2clk_tb.exe -sdfmax /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.bat deleted file mode 100755 index 35375ce20..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.bat +++ /dev/null @@ -1,47 +0,0 @@ -:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. - -vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.do deleted file mode 100755 index 5b83909ee..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.do +++ /dev/null @@ -1,72 +0,0 @@ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -vlib work -vmap work work - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlog -work work ../../implement/results/routed.v - -echo "Compiling Test Bench Files" -vcom -work work ../fifo_xlnx_16x40_2clk_pkg.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_rng.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_dgen.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_dverif.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_pctrl.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_synth.vhd -vcom -work work ../fifo_xlnx_16x40_2clk_tb.vhd - -vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst=../../implement/results/routed.sdf work.fifo_xlnx_16x40_2clk_tb - -add log -r /* -do wave_mti.do -#Ignore integer warnings at time 0 -set StdArithNoWarnings 1 -run 0 -set StdArithNoWarnings 0 - -run -all diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.sh deleted file mode 100755 index edb1b0dd9..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.sh +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_ncsim.sh deleted file mode 100755 index 57db29304..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_ncsim.sh +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -mkdir work -echo "Compiling Core Verilog UNISIM/Behavioral model" -ncvlog -work work ../../implement/results/routed.v - -echo "Compiling Test Bench Files" -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_pkg.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_rng.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_dgen.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_dverif.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_pctrl.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_synth.vhd -ncvhdl -v93 -work work ../fifo_xlnx_16x40_2clk_tb.vhd - -echo "Compiling SDF file" -ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X - -echo "Generating SDF command file" -echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd -echo 'SCOPE = :fifo_xlnx_16x40_2clk_synth_inst:fifo_xlnx_16x40_2clk_inst,' >> sdf.cmd -echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd - -echo "Elaborating Design" -ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_xlnx_16x40_2clk_tb - -echo "Simulating Design" -ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_xlnx_16x40_2clk_tb diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_vcs.sh deleted file mode 100755 index d2fe8dfbc..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/simulate_vcs.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -rm -rf simv* csrc DVEfiles AN.DB - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogan +v2k ../../implement/results/routed.v - -echo "Compiling Test Bench Files" -vhdlan ../fifo_xlnx_16x40_2clk_pkg.vhd -vhdlan ../fifo_xlnx_16x40_2clk_rng.vhd -vhdlan ../fifo_xlnx_16x40_2clk_dgen.vhd -vhdlan ../fifo_xlnx_16x40_2clk_dverif.vhd -vhdlan ../fifo_xlnx_16x40_2clk_pctrl.vhd -vhdlan ../fifo_xlnx_16x40_2clk_synth.vhd -vhdlan ../fifo_xlnx_16x40_2clk_tb.vhd - -echo "Elaborating Design" -vcs -time_res 1ps +neg_tchk -sdf max:/fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_xlnx_16x40_2clk_tb glbl - -echo "Simulating Design" -./simv -ucli -i ucli_commands.key -dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/ucli_commands.key deleted file mode 100755 index f468f1ade..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/ucli_commands.key +++ /dev/null @@ -1,4 +0,0 @@ -dump -file fifo_xlnx_16x40_2clk.vpd -type VPD -dump -add fifo_xlnx_16x40_2clk_tb -run -quit diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/vcs_session.tcl deleted file mode 100755 index 50de69ec0..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/vcs_session.tcl +++ /dev/null @@ -1,76 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: vcs_session.tcl -# -# Description: -# This is the VCS wave form file. -# -#-------------------------------------------------------------------------------- -if { ![gui_is_db_opened -db {fifo_xlnx_16x40_2clk.vpd}] } { - gui_open_db -design V1 -file fifo_xlnx_16x40_2clk.vpd -nosource -} -gui_set_precision 1ps -gui_set_time_units 1ps - -gui_open_window Wave -gui_sg_create fifo_xlnx_16x40_2clk_Group -gui_list_add_group -id Wave.1 {fifo_xlnx_16x40_2clk_Group} - -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group WRITE -divider -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group READ -divider -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -gui_sg_addsignal -group fifo_xlnx_16x40_2clk_Group /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_isim.tcl deleted file mode 100755 index 38fa5e088..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_isim.tcl +++ /dev/null @@ -1,68 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: wave_isim.tcl -# -# Description: -# This is the ISIM wave form file. -# -#-------------------------------------------------------------------------------- -wcfg new -isim set radix hex -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -wave add /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -run all -quit - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_mti.do deleted file mode 100755 index d553aecac..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_mti.do +++ /dev/null @@ -1,88 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- --- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. -# Filename: wave_mti.do -# -# Description: -# This is the modelsim wave form file. -# -#-------------------------------------------------------------------------------- - -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -add wave -noupdate -divider WRITE -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -add wave -noupdate -radix hexadecimal /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/DIN -add wave -noupdate -divider READ -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -add wave -noupdate /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -add wave -noupdate -radix hexadecimal /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/DOUT - -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} -configure wave -namecolwidth 197 -configure wave -valuecolwidth 106 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_ncsim.sv deleted file mode 100755 index 827dc9825..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk/simulation/timing/wave_ncsim.sv +++ /dev/null @@ -1,70 +0,0 @@ -#-------------------------------------------------------------------------------- -#-- -#-- FIFO Generator Core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: wave_ncsim.sv -# -# Description: -# This is the IUS wave form file. -# -#-------------------------------------------------------------------------------- - -window new WaveWindow -name "Waves for FIFO Generator Example Design" -waveform using "Waves for FIFO Generator Example Design" - -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RST -waveform add -label WRITE -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_CLK -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/WR_EN -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/FULL -waveform add -label READ -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_CLK -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/RD_EN -waveform add -signals /fifo_xlnx_16x40_2clk_tb/fifo_xlnx_16x40_2clk_synth_inst/fifo_xlnx_16x40_2clk_inst/EMPTY -console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 544bda31d..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,98 +0,0 @@ - - - - - - -
- - - - - - - - - - - - - -
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- - - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_flist.txt b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_flist.txt deleted file mode 100644 index b4a758388..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_flist.txt +++ /dev/null @@ -1,56 +0,0 @@ -# Output products list for -fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_readme.txt -fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_vinfo.html -fifo_xlnx_16x40_2clk/doc/pg057-fifo-generator.pdf -fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.ucf -fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.vhd -fifo_xlnx_16x40_2clk/fifo_generator_v9_3_readme.txt -fifo_xlnx_16x40_2clk/implement/implement.bat -fifo_xlnx_16x40_2clk/implement/implement.sh -fifo_xlnx_16x40_2clk/implement/implement_synplify.bat -fifo_xlnx_16x40_2clk/implement/implement_synplify.sh -fifo_xlnx_16x40_2clk/implement/planAhead_ise.bat -fifo_xlnx_16x40_2clk/implement/planAhead_ise.sh -fifo_xlnx_16x40_2clk/implement/planAhead_ise.tcl -fifo_xlnx_16x40_2clk/implement/xst.prj -fifo_xlnx_16x40_2clk/implement/xst.scr -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dgen.vhd -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dverif.vhd -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pctrl.vhd -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pkg.vhd -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_rng.vhd -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_synth.vhd -fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_tb.vhd -fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.bat -fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.sh -fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.bat -fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.do -fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.sh -fifo_xlnx_16x40_2clk/simulation/functional/simulate_ncsim.sh -fifo_xlnx_16x40_2clk/simulation/functional/simulate_vcs.sh -fifo_xlnx_16x40_2clk/simulation/functional/ucli_commands.key -fifo_xlnx_16x40_2clk/simulation/functional/vcs_session.tcl -fifo_xlnx_16x40_2clk/simulation/functional/wave_isim.tcl -fifo_xlnx_16x40_2clk/simulation/functional/wave_mti.do -fifo_xlnx_16x40_2clk/simulation/functional/wave_ncsim.sv -fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.bat -fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.sh -fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.bat -fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.do -fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.sh -fifo_xlnx_16x40_2clk/simulation/timing/simulate_ncsim.sh -fifo_xlnx_16x40_2clk/simulation/timing/simulate_vcs.sh -fifo_xlnx_16x40_2clk/simulation/timing/ucli_commands.key -fifo_xlnx_16x40_2clk/simulation/timing/vcs_session.tcl -fifo_xlnx_16x40_2clk/simulation/timing/wave_isim.tcl -fifo_xlnx_16x40_2clk/simulation/timing/wave_mti.do -fifo_xlnx_16x40_2clk/simulation/timing/wave_ncsim.sv -fifo_xlnx_16x40_2clk.asy -fifo_xlnx_16x40_2clk.gise -fifo_xlnx_16x40_2clk.ngc -fifo_xlnx_16x40_2clk.v -fifo_xlnx_16x40_2clk.veo -fifo_xlnx_16x40_2clk.xco -fifo_xlnx_16x40_2clk.xise -fifo_xlnx_16x40_2clk_flist.txt -fifo_xlnx_16x40_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_readme.txt b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_readme.txt deleted file mode 100644 index bbcd4af79..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_16x40_2clk' in directory -/home/matt/sourcerepo/fpga/usrp2/coregen/: - -fifo_xlnx_16x40_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_16x40_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_16x40_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_16x40_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_16x40_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_16x40_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_16x40_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl deleted file mode 100644 index ceaff5355..000000000 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl +++ /dev/null @@ -1,251 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_16x40_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_16x40_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x40_2clk -} -# ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/doc/fifo_generator_v9_3_vinfo.html -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/doc/pg057-fifo-generator.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/example_design/fifo_xlnx_16x40_2clk_exdes.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/fifo_generator_v9_3_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/implement_synplify.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/implement_synplify.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/planAhead_ise.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/planAhead_ise.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/planAhead_ise.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dgen.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_dverif.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pctrl.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_pkg.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_rng.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_synth.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/fifo_xlnx_16x40_2clk_tb.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_isim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_mti.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_ncsim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/simulate_vcs.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/ucli_commands.key -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/vcs_session.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/wave_isim.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/wave_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/functional/wave_ncsim.sv -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_isim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_mti.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_ncsim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/simulate_vcs.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/ucli_commands.key -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/vcs_session.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/wave_isim.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/wave_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk/simulation/timing/wave_ncsim.sv -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x40_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp.asy b/fpga/usrp3/top/x300/coregen/gige_sfp.asy deleted file mode 100644 index db81f2fc2..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp.asy +++ /dev/null @@ -1,129 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 gige_sfp -RECTANGLE Normal 32 32 544 1152 -LINE Normal 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName reset -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName userclk -PINATTR Polarity IN -LINE Normal 0 208 32 208 -PIN 0 208 LEFT 36 -PINATTR PinName userclk2 -PINATTR Polarity IN -LINE Wide 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName gmii_txd[7:0] -PINATTR Polarity IN -LINE Normal 0 304 32 304 -PIN 0 304 LEFT 36 -PINATTR PinName gmii_tx_en -PINATTR Polarity IN -LINE Normal 0 336 32 336 -PIN 0 336 LEFT 36 -PINATTR PinName gmii_tx_er -PINATTR Polarity IN -LINE Wide 0 368 32 368 -PIN 0 368 LEFT 36 -PINATTR PinName gmii_rxd[7:0] -PINATTR Polarity OUT -LINE Normal 0 400 32 400 -PIN 0 400 LEFT 36 -PINATTR PinName gmii_rx_dv -PINATTR Polarity OUT -LINE Normal 0 432 32 432 -PIN 0 432 LEFT 36 -PINATTR PinName gmii_rx_er -PINATTR Polarity OUT -LINE Normal 0 464 32 464 -PIN 0 464 LEFT 36 -PINATTR PinName gmii_isolate -PINATTR Polarity OUT -LINE Wide 0 720 32 720 -PIN 0 720 LEFT 36 -PINATTR PinName configuration_vector[4:0] -PINATTR Polarity IN -LINE Wide 0 784 32 784 -PIN 0 784 LEFT 36 -PINATTR PinName status_vector[15:0] -PINATTR Polarity OUT -LINE Normal 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName mgt_rx_reset -PINATTR Polarity OUT -LINE Normal 576 112 544 112 -PIN 576 112 RIGHT 36 -PINATTR PinName mgt_tx_reset -PINATTR Polarity OUT -LINE Normal 576 144 544 144 -PIN 576 144 RIGHT 36 -PINATTR PinName dcm_locked -PINATTR Polarity IN -LINE Wide 576 176 544 176 -PIN 576 176 RIGHT 36 -PINATTR PinName rxbufstatus[1:0] -PINATTR Polarity IN -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName rxchariscomma -PINATTR Polarity IN -LINE Normal 576 240 544 240 -PIN 576 240 RIGHT 36 -PINATTR PinName rxcharisk -PINATTR Polarity IN -LINE Wide 576 272 544 272 -PIN 576 272 RIGHT 36 -PINATTR PinName rxclkcorcnt[2:0] -PINATTR Polarity IN -LINE Wide 576 304 544 304 -PIN 576 304 RIGHT 36 -PINATTR PinName rxdata[7:0] -PINATTR Polarity IN -LINE Normal 576 336 544 336 -PIN 576 336 RIGHT 36 -PINATTR PinName rxdisperr -PINATTR Polarity IN -LINE Normal 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName rxnotintable -PINATTR Polarity IN -LINE Normal 576 400 544 400 -PIN 576 400 RIGHT 36 -PINATTR PinName rxrundisp -PINATTR Polarity IN -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName txbuferr -PINATTR Polarity IN -LINE Normal 576 464 544 464 -PIN 576 464 RIGHT 36 -PINATTR PinName powerdown -PINATTR Polarity OUT -LINE Normal 576 496 544 496 -PIN 576 496 RIGHT 36 -PINATTR PinName txchardispmode -PINATTR Polarity OUT -LINE Normal 576 528 544 528 -PIN 576 528 RIGHT 36 -PINATTR PinName txchardispval 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp.v b/fpga/usrp3/top/x300/coregen/gige_sfp.v deleted file mode 100644 index 3b5fa0711..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp.v +++ /dev/null @@ -1,3400 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -//////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version: P.40xd -// \ \ Application: netgen -// / / Filename: gige_sfp.v -// /___/ /\ Timestamp: Fri Dec 21 13:53:12 2012 -// \ \ / \ -// \___\/\___\ -// -// Command : -w -sim -ofmt verilog /home/matt/sourcerepo/fpga/usrp3/top/x300/coregen/tmp/_cg/gige_sfp.ngc /home/matt/sourcerepo/fpga/usrp3/top/x300/coregen/tmp/_cg/gige_sfp.v -// Device : 7k410tffg900-2 -// Input file : /home/matt/sourcerepo/fpga/usrp3/top/x300/coregen/tmp/_cg/gige_sfp.ngc -// Output file : /home/matt/sourcerepo/fpga/usrp3/top/x300/coregen/tmp/_cg/gige_sfp.v -// # of Modules : 1 -// Design Name : gige_sfp -// Xilinx : /opt/Xilinx/14.3/ISE_DS/ISE/ -// -// Purpose: -// This verilog netlist is a verification model and uses simulation -// primitives which may not represent the true implementation of the -// device, however the netlist is functionally correct and should not -// be modified. This file cannot be synthesized and should only be used -// with supported simulation tools. -// -// Reference: -// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 -// -//////////////////////////////////////////////////////////////////////////////// - -`timescale 1 ns/1 ps - -module gige_sfp ( - reset, signal_detect, userclk, userclk2, dcm_locked, rxchariscomma, rxcharisk, rxdisperr, rxnotintable, rxrundisp, txbuferr, gmii_tx_en, gmii_tx_er -, mgt_rx_reset, mgt_tx_reset, powerdown, txchardispmode, txchardispval, txcharisk, enablealign, gmii_rx_dv, gmii_rx_er, gmii_isolate, rxbufstatus, -rxclkcorcnt, rxdata, gmii_txd, configuration_vector, txdata, gmii_rxd, status_vector -)/* synthesis syn_black_box syn_noprune=1 */; - input reset; - input signal_detect; - input userclk; - input userclk2; - input dcm_locked; - input rxchariscomma; - input rxcharisk; - input rxdisperr; - input rxnotintable; - input rxrundisp; - input txbuferr; - input gmii_tx_en; - input gmii_tx_er; - output mgt_rx_reset; - output mgt_tx_reset; - output powerdown; - output txchardispmode; - output txchardispval; - output txcharisk; - output enablealign; - output gmii_rx_dv; - output gmii_rx_er; - output gmii_isolate; - input [1 : 0] rxbufstatus; - input [2 : 0] rxclkcorcnt; - input [7 : 0] rxdata; - input [7 : 0] gmii_txd; - input [4 : 0] configuration_vector; - output [7 : 0] txdata; - output [7 : 0] gmii_rxd; - output [15 : 0] status_vector; - - // synthesis translate_off - - wire \U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_in ; - wire \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_REG_51 ; - wire \U0/xst_options.gpcs_pma_inst/RXDISPERR_REG_52 ; - wire \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_I_54 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_C_55 ; - wire \NlwRenamedSignal_U0/xst_options.gpcs_pma_inst/STATUS_VECTOR_0 ; - wire \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ; - wire \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ; - wire \U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE_60 ; - wire \U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL_61 ; - wire \U0/xst_options.gpcs_pma_inst/TXCHARISK_62 ; - wire \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN ; - wire \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_ER_65 ; - wire N0; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1-In ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2-In ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3-In ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1-In ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2-In ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3-In ; - wire \U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_sync1 ; - wire \U0/xst_options.gpcs_pma_inst/SRESET_PIPE_PWR_14_o_MUX_1_o ; - wire \U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o ; - wire \U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o ; - wire \U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL_INT_GND_14_o_MUX_194_o ; - wire \U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE_INT_TXEVEN_MUX_193_o ; - wire \U0/xst_options.gpcs_pma_inst/TXCHARISK_INT_TXEVEN_MUX_192_o ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<2> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<3> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<4> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<5> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<6> ; - wire \U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<7> ; - wire \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_GND_14_o_MUX_182_o ; - wire \U0/xst_options.gpcs_pma_inst/RXDISPERR_GND_14_o_MUX_183_o ; - wire \U0/xst_options.gpcs_pma_inst/RXCHARISK_TXCHARISK_INT_MUX_185_o ; - wire \U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_TXCHARISK_INT_MUX_186_o ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM[3]_GND_14_o_Mux_17_o ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM[3]_GND_14_o_Mux_13_o ; - wire \U0/xst_options.gpcs_pma_inst/TXBUFERR_INT_103 ; - wire \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ; - wire \U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ; - wire \U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ; - wire \U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT_119 ; - wire \U0/xst_options.gpcs_pma_inst/SRESET_121 ; - wire \U0/xst_options.gpcs_pma_inst/SRESET_PIPE_122 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ; - wire \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_SRL ; - wire \U0/xst_options.gpcs_pma_inst/RXDISPERR_SRL ; - wire \U0/xst_options.gpcs_pma_inst/RESET_INT_PIPE_127 ; - wire \U0/xst_options.gpcs_pma_inst/RESET_INT_128 ; - wire \U0/xst_options.gpcs_pma_inst/SIGNAL_DETECT_REG ; - wire \U0/xst_options.gpcs_pma_inst/DCM_LOCKED_SOFT_RESET_OR_2_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_131 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPMODE_132 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARISK_133 ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<2> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<3> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<4> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<5> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<6> ; - wire \U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<7> ; - wire \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<2> ; - wire \U0/xst_options.gpcs_pma_inst/RXBUFSTATUS[1]_GND_14_o_mux_21_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT511 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mram_CODE_GRP_CNT[1]_GND_21_o_Mux_5_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT[1]_TX_CONFIG[15]_wide_mux_4_OUT<7> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISP5 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_TRIGGER_T_OR_14_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_EVEN_AND_8_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_CODE_GRP_CNT[1]_MUX_73_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_GND_21_o_MUX_79_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<2> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<3> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<4> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<5> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<6> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<7> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_EVEN_AND_42_o ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<2> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<3> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<4> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<5> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<6> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<7> ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_188 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_190 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_192 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_S_194 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1_208 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_0 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In2_223 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1-In2 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2-In2 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3-In3 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/_n0103_inv ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_PWR_19_o_equal_19_o ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_GND_23_o_mux_30_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_GND_23_o_mux_30_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SIGNAL_DETECT_REG_234 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o1_235 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG2_236 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_D21p5_AND_116_o_norst ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG[1]_IDLE_REG[2]_OR_114_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG[0]_RX_CONFIG_VALID_REG[3]_OR_113_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_C_REG3_OR_59_o_240 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_242 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_ISOLATE_AND_182_o_244 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_EXT_ILLEGAL_K_REG2_OR_83_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_EXTEND_OR_65_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<0> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<1> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<2> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<3> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<4> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<5> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<6> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<7> ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_K28p5_REG1_AND_167_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/S_WAIT_FOR_K_AND_144_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_C_REG1_AND_125_o_257 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EVEN_RXCHARISK_AND_115_o_258 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_EVEN_AND_127_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA[7]_RXNOTINTABLE_AND_211_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K23p7 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K29p7 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXFIFO_ERR_RXDISPERR_OR_36_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_267 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_269 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_270 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_278 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_K_279 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_280 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG2_281 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG1_282 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_283 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_ERR_284 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG2_285 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG1_286 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_287 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_288 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_REG1_289 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_290 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_291 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FROM_RX_CX_292 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_REG_295 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_INT_296 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG3_297 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_298 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_308 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG2_311 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG2 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_313 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG2 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_315 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG3_316 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/R_REG1_319 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_320 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG1_321 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_REG_322 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_324 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/I_325 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/T_326 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/S_327 ; - wire N2; - wire N6; - wire N8; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o1_331 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o2_332 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT2 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT1 ; - wire N14; - wire N18; - wire N20; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o1_339 ; - wire N22; - wire N24; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o1 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o12_343 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o13_344 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o14_345 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o1_346 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o1_347 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o2_348 ; - wire N26; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_glue_set_350 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_glue_set_351 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_glue_set_352 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_glue_rst_353 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_glue_set_354 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_glue_set_355 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID_glue_set_356 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV_glue_set_357 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_glue_set_358 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_glue_set_359 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_glue_set_360 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_rstpot_361 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_rstpot_362 ; - wire \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_rstpot_363 ; - wire \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_rstpot_364 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_rstpot_365 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_rstpot_366 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_rstpot_367 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_rstpot_368 ; - wire \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_0_rstpot_369 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_rstpot_370 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/C_rstpot_371 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_rstpot_372 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_rstpot_373 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_rstpot_374 ; - wire N28; - wire N34; - wire N38; - wire N39; - wire N43; - wire N45; - wire N57; - wire N59; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN_rstpot_383 ; - wire \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_rstpot_384 ; - wire N71; - wire N73; - wire N75; - wire N77; - wire N79; - wire N81; - wire N83; - wire N84; - wire N85; - wire N86; - wire N87; - wire N88; - wire N89; - wire N90; - wire N91; - wire N92; - wire N93; - wire N94; - wire N95; - wire N96; - wire \U0/xst_options.gpcs_pma_inst/Mshreg_STATUS_VECTOR_0_405 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_7_406 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_6_407 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_5_408 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_2_409 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_4_410 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_3_411 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_EXTEND_REG3_412 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_1_413 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_0_414 ; - wire \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_SOP_REG2_415 ; - wire \NLW_U0/xst_options.gpcs_pma_inst/Mshreg_STATUS_VECTOR_0_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_7_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_6_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_5_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_2_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_4_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_3_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_EXTEND_REG3_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_1_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_0_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_CGBAD_REG2_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_SOP_REG2_Q15_UNCONNECTED ; - wire \NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_FALSE_CARRIER_REG2_Q15_UNCONNECTED ; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/TXDATA ; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD ; - wire [3 : 2] \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG ; - wire [2 : 0] \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT ; - wire [1 : 1] \U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT ; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/RXDATA_INT ; - wire [1 : 1] \U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG ; - wire [1 : 0] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT ; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA ; - wire [1 : 0] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Result ; - wire [1 : 1] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/_n0234 ; - wire [3 : 0] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA ; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP ; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 ; - wire [1 : 0] \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS ; - wire [2 : 0] \U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG ; - wire [3 : 0] \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG ; - wire [7 : 7] NlwRenamedSig_OI_status_vector; - wire [7 : 0] \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 ; - assign - \U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_in = signal_detect, - txdata[7] = \U0/xst_options.gpcs_pma_inst/TXDATA [7], - txdata[6] = \U0/xst_options.gpcs_pma_inst/TXDATA [6], - txdata[5] = \U0/xst_options.gpcs_pma_inst/TXDATA [5], - txdata[4] = \U0/xst_options.gpcs_pma_inst/TXDATA [4], - txdata[3] = \U0/xst_options.gpcs_pma_inst/TXDATA [3], - txdata[2] = \U0/xst_options.gpcs_pma_inst/TXDATA [2], - txdata[1] = \U0/xst_options.gpcs_pma_inst/TXDATA [1], - txdata[0] = \U0/xst_options.gpcs_pma_inst/TXDATA [0], - gmii_rxd[7] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [7], - gmii_rxd[6] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [6], - gmii_rxd[5] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [5], - gmii_rxd[4] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [4], - gmii_rxd[3] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [3], - gmii_rxd[2] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [2], - gmii_rxd[1] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [1], - gmii_rxd[0] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [0], - status_vector[15] = NlwRenamedSig_OI_status_vector[7], - status_vector[14] = NlwRenamedSig_OI_status_vector[7], - status_vector[13] = NlwRenamedSig_OI_status_vector[7], - status_vector[12] = NlwRenamedSig_OI_status_vector[7], - status_vector[11] = NlwRenamedSig_OI_status_vector[7], - status_vector[10] = NlwRenamedSig_OI_status_vector[7], - status_vector[9] = NlwRenamedSig_OI_status_vector[7], - status_vector[8] = NlwRenamedSig_OI_status_vector[7], - status_vector[7] = NlwRenamedSig_OI_status_vector[7], - status_vector[6] = \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_REG_51 , - status_vector[5] = \U0/xst_options.gpcs_pma_inst/RXDISPERR_REG_52 , - status_vector[4] = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID , - status_vector[3] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_I_54 , - status_vector[2] = \U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_C_55 , - status_vector[1] = \NlwRenamedSignal_U0/xst_options.gpcs_pma_inst/STATUS_VECTOR_0 , - status_vector[0] = \NlwRenamedSignal_U0/xst_options.gpcs_pma_inst/STATUS_VECTOR_0 , - mgt_rx_reset = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT , - mgt_tx_reset = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT , - powerdown = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [2], - txchardispmode = \U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE_60 , - txchardispval = \U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL_61 , - txcharisk = \U0/xst_options.gpcs_pma_inst/TXCHARISK_62 , - enablealign = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN , - gmii_rx_dv = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV , - gmii_rx_er = \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_ER_65 , - gmii_isolate = \NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]; - VCC XST_VCC ( - .P(N0) - ); - GND XST_GND ( - .G(NlwRenamedSig_OI_status_vector[7]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/DELAY_RXNOTINTABLE ( - .A0(NlwRenamedSig_OI_status_vector[7]), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(N0), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ), - .Q(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_SRL ) - ); - SRL16 #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/DELAY_RXDISPERR ( - .A0(NlwRenamedSig_OI_status_vector[7]), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(N0), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDISPERR_SRL ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2-In ), - .R(\U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3-In ), - .R(\U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1-In ), - .R(\U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1-In ), - .R(\U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o ), - .Q(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2-In ), - .R(\U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o ), - .Q(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3-In ), - .R(\U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o ), - .Q(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_sync ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_in ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_sync1 ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_sync_reg ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNC_SIGNAL_DETECT/data_sync1 ), - .Q(\U0/xst_options.gpcs_pma_inst/SIGNAL_DETECT_REG ) - ); - FD \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_SRL ), - .Q(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_REG_51 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RXDISPERR_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDISPERR_SRL ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDISPERR_REG_52 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL_INT_GND_14_o_MUX_194_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL_61 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXCHARISK ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXCHARISK_INT_TXEVEN_MUX_192_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXCHARISK_62 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_7 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<7> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [7]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_6 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<6> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [6]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_5 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<5> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [5]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<4> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [4]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<3> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<2> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXDATA_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<0> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXDATA [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE_INT_TXEVEN_MUX_193_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE_60 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXCHARISK_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXCHARISK_TXCHARISK_INT_MUX_185_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_TXCHARISK_INT_MUX_186_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT_119 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_7 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<7> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_6 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<6> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_5 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<5> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<4> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<3> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<2> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDATA_INT_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<0> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS[1]_GND_14_o_mux_21_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<2> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<0> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_GND_14_o_MUX_182_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RXDISPERR_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDISPERR_GND_14_o_MUX_183_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG_3 ( - .C(userclk2), - .D(configuration_vector[3]), - .R(\U0/xst_options.gpcs_pma_inst/SRESET_121 ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG_2 ( - .C(userclk2), - .D(configuration_vector[2]), - .R(\U0/xst_options.gpcs_pma_inst/SRESET_121 ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG_1 ( - .C(userclk2), - .D(configuration_vector[1]), - .R(\U0/xst_options.gpcs_pma_inst/SRESET_121 ), - .Q(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]) - ); - FD \U0/xst_options.gpcs_pma_inst/SRESET ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SRESET_PIPE_PWR_14_o_MUX_1_o ), - .Q(\U0/xst_options.gpcs_pma_inst/SRESET_121 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TXBUFERR_INT ( - .C(userclk2), - .D(txbuferr), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TXBUFERR_INT_103 ) - ); - FD \U0/xst_options.gpcs_pma_inst/SRESET_PIPE ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ), - .Q(\U0/xst_options.gpcs_pma_inst/SRESET_PIPE_122 ) - ); - FDS \U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RX_RST_SM[3]_GND_14_o_Mux_17_o ), - .S(\U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ) - ); - FDS \U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TX_RST_SM[3]_GND_14_o_Mux_13_o ), - .S(\U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ) - ); - FDP \U0/xst_options.gpcs_pma_inst/RESET_INT ( - .C(userclk), - .D(\U0/xst_options.gpcs_pma_inst/RESET_INT_PIPE_127 ), - .PRE(\U0/xst_options.gpcs_pma_inst/DCM_LOCKED_SOFT_RESET_OR_2_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ) - ); - FDP \U0/xst_options.gpcs_pma_inst/RESET_INT_PIPE ( - .C(userclk), - .D(NlwRenamedSig_OI_status_vector[7]), - .PRE(\U0/xst_options.gpcs_pma_inst/DCM_LOCKED_SOFT_RESET_OR_2_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RESET_INT_PIPE_127 ) - ); - FDS \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Result [1]), - .S(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]) - ); - FDS \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Result [0]), - .S(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_7 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<7> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [7]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_6 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<6> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [6]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_5 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<5> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [5]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<4> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [4]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<3> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<2> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<0> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARISK ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_GND_21_o_MUX_79_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARISK_133 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_7 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<7> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [7]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_6 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<6> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [6]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_5 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<5> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [5]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<4> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [4]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<3> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [3]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<2> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [2]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<1> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [1]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<0> ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [0]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_CODE_GRP_CNT[1]_MUX_73_o ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ) - ); - FDS \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPMODE ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_EVEN_AND_42_o ), - .S(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPMODE_132 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_S ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_EVEN_AND_8_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_S_194 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/T ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_TRIGGER_T_OR_14_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mram_CODE_GRP_CNT[1]_GND_21_o_Mux_5_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT[1]_TX_CONFIG[15]_wide_mux_4_OUT<7> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/_n0234 [1]), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [1]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1 ( - .C(userclk2), - .D(gmii_tx_er), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1_208 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1 ( - .C(userclk2), - .D(gmii_tx_en), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_7 ( - .C(userclk2), - .D(gmii_txd[7]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [7]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_6 ( - .C(userclk2), - .D(gmii_txd[6]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [6]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_5 ( - .C(userclk2), - .D(gmii_txd[5]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [5]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_4 ( - .C(userclk2), - .D(gmii_txd[4]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [4]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_3 ( - .C(userclk2), - .D(gmii_txd[3]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [3]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_2 ( - .C(userclk2), - .D(gmii_txd[2]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [2]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_1 ( - .C(userclk2), - .D(gmii_txd[1]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [1]) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1_0 ( - .C(userclk2), - .D(gmii_txd[0]), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [0]) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1-In2 ), - .R(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_0 ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2-In2 ), - .R(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_0 ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In2_223 ), - .R(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_0 ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ) - ); - FDR #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3-In3 ), - .R(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_0 ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ) - ); - FDRE \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS_1 ( - .C(userclk2), - .CE(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/_n0103_inv ), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_GND_23_o_mux_30_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [1]) - ); - FDRE \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS_0 ( - .C(userclk2), - .CE(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/_n0103_inv ), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_GND_23_o_mux_30_OUT<0> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [0]) - ); - FD \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SIGNAL_DETECT_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SIGNAL_DETECT_REG ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SIGNAL_DETECT_REG_234 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_7 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<7> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [7]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_6 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<6> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [6]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_5 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<5> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [5]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<4> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [4]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<3> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<2> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<1> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RXD_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<0> ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXD [0]) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG2_236 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG3_316 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG2 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG2 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG3_297 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG2_311 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG2_236 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [1]), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [0]), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG1_282 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG2_281 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG1_286 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG2_285 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_324 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG1_321 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_320 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG_3 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [2]), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [3]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG_2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [1]), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [2]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG_1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [0]), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [1]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_INT_296 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [0]) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_283 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG1_282 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_287 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG1_286 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_267 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_325 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/R_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_REG1_319 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_326 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG1_321 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_I ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG[1]_IDLE_REG[2]_OR_114_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_I_54 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_C ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG[0]_RX_CONFIG_VALID_REG[3]_OR_113_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RUDI_C_55 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_K ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA[7]_RXNOTINTABLE_AND_211_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_K_279 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_280 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_ER ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_ISOLATE_AND_182_o_244 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_ER_65 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_ERR ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_EXT_ILLEGAL_K_REG2_OR_83_o ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_ERR_284 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_K28p5_REG1_AND_167_o ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_287 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/EOP ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_290 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/SOP ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_WAIT_FOR_K_AND_144_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_291 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_EXTEND_OR_65_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_REG1_289 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/FROM_RX_CX ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_C_REG3_OR_59_o_240 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FROM_RX_CX_292 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_REG_295 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_C_REG1_AND_125_o_257 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_INT_296 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/R ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/K23p7 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXFIFO_ERR_RXDISPERR_OR_36_o ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_298 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_315 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_242 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_REG_322 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/I ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EVEN_RXCHARISK_AND_115_o_258 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_325 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/S ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_327 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/T ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/K29p7 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_326 ) - ); - LUT4 #( - .INIT ( 16'hEA6A )) - \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2-In1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ), - .I1(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ), - .I2(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ), - .I3(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ), - .O(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2-In ) - ); - LUT4 #( - .INIT ( 16'hEA6A )) - \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2-In1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ), - .I1(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ), - .I2(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ), - .I3(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ), - .O(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2-In ) - ); - LUT4 #( - .INIT ( 16'hE666 )) - \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3-In1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ), - .I1(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ), - .I2(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ), - .I3(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ), - .O(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3-In ) - ); - LUT4 #( - .INIT ( 16'hE666 )) - \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3-In1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ), - .I1(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ), - .I2(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ), - .I3(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ), - .O(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3-In ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXCHARDISPVAL_INT_GND_14_o_MUX_194_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_131 ), - .O(\U0/xst_options.gpcs_pma_inst/TXCHARDISPVAL_INT_GND_14_o_MUX_194_o ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXCHARDISPMODE_INT_TXEVEN_MUX_193_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPMODE_132 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXCHARDISPMODE_INT_TXEVEN_MUX_193_o ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXCHARISK_INT_TXEVEN_MUX_192_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARISK_133 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXCHARISK_INT_TXEVEN_MUX_192_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<0> ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [1]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<1> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT31 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [2]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<2> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT41 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [3]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<3> ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT51 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [4]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<4> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT61 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [5]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<5> ) - ); - LUT3 #( - .INIT ( 8'h4E )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT71 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [6]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<6> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_TXDATA_INT[7]_GND_14_o_mux_30_OUT81 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [7]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TXDATA_INT[7]_GND_14_o_mux_30_OUT<7> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXCHARISK_TXCHARISK_INT_MUX_185_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxcharisk), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARISK_133 ), - .O(\U0/xst_options.gpcs_pma_inst/RXCHARISK_TXCHARISK_INT_MUX_185_o ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXCHARISCOMMA_TXCHARISK_INT_MUX_186_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxchariscomma), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARISK_133 ), - .O(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_TXCHARISK_INT_MUX_186_o ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[0]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [0]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<0> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[1]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [1]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<1> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT31 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[2]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [2]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<2> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT41 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[3]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [3]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<3> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT51 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[4]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [4]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<4> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT61 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[5]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [5]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<5> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT71 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[6]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [6]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<6> ) - ); - LUT3 #( - .INIT ( 8'hE4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDATA[7]_TXDATA_INT[7]_mux_20_OUT81 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdata[7]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXDATA [7]), - .O(\U0/xst_options.gpcs_pma_inst/RXDATA[7]_TXDATA_INT[7]_mux_20_OUT<7> ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/Mmux_SRESET_PIPE_PWR_14_o_MUX_1_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ), - .I1(\U0/xst_options.gpcs_pma_inst/SRESET_PIPE_122 ), - .O(\U0/xst_options.gpcs_pma_inst/SRESET_PIPE_PWR_14_o_MUX_1_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXDISPERR_GND_14_o_MUX_183_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxdisperr), - .O(\U0/xst_options.gpcs_pma_inst/RXDISPERR_GND_14_o_MUX_183_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXNOTINTABLE_GND_14_o_MUX_182_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxnotintable), - .O(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_GND_14_o_MUX_182_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXCLKCORCNT[2]_GND_14_o_mux_22_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxclkcorcnt[0]), - .O(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<0> ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXCLKCORCNT[2]_GND_14_o_mux_22_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxclkcorcnt[1]), - .O(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<1> ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXCLKCORCNT[2]_GND_14_o_mux_22_OUT31 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxclkcorcnt[2]), - .O(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT[2]_GND_14_o_mux_22_OUT<2> ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/Mmux_RXBUFSTATUS[1]_GND_14_o_mux_21_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I1(rxbufstatus[1]), - .O(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS[1]_GND_14_o_mux_21_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'hFF80 )) - \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1-In1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ), - .I1(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ), - .I2(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ), - .I3(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ), - .O(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'hDFFF )) - \U0/xst_options.gpcs_pma_inst/RX_RST_SM_RX_RST_SM[3]_GND_14_o_Mux_17_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ), - .I1(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ), - .I2(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ), - .I3(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ), - .O(\U0/xst_options.gpcs_pma_inst/RX_RST_SM[3]_GND_14_o_Mux_17_o ) - ); - LUT4 #( - .INIT ( 16'hFF80 )) - \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1-In1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ), - .I1(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ), - .I2(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ), - .I3(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ), - .O(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1-In ) - ); - LUT4 #( - .INIT ( 16'hDFFF )) - \U0/xst_options.gpcs_pma_inst/TX_RST_SM_TX_RST_SM[3]_GND_14_o_Mux_13_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ), - .I1(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ), - .I2(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ), - .I3(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ), - .O(\U0/xst_options.gpcs_pma_inst/TX_RST_SM[3]_GND_14_o_Mux_13_o ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ), - .I1(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT [1]), - .O(\U0/xst_options.gpcs_pma_inst/RESET_INT_RXBUFSTATUS_INT[1]_OR_116_o ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ), - .I1(\U0/xst_options.gpcs_pma_inst/TXBUFERR_INT_103 ), - .O(\U0/xst_options.gpcs_pma_inst/RESET_INT_TXBUFERR_INT_OR_115_o ) - ); - LUT2 #( - .INIT ( 4'hB )) - \U0/xst_options.gpcs_pma_inst/DCM_LOCKED_SOFT_RESET_OR_2_o1 ( - .I0(reset), - .I1(dcm_locked), - .O(\U0/xst_options.gpcs_pma_inst/DCM_LOCKED_SOFT_RESET_OR_2_o ) - ); - LUT4 #( - .INIT ( 16'hCFCA )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT51 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [4]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [2]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT511 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<4> ) - ); - LUT4 #( - .INIT ( 16'hCFCA )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT61 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [5]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [2]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT511 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<5> ) - ); - LUT4 #( - .INIT ( 16'hCFCA )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT81 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [7]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [2]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT511 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<7> ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFFFEFF )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT5111 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I5(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT511 ) - ); - LUT5 #( - .INIT ( 32'hE881811F )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISP51 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [3]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [4]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [1]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [2]), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISP5 ) - ); - LUT3 #( - .INIT ( 8'h15 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT[1]_TX_CONFIG[15]_wide_mux_4_OUT<7>1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_188 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT[1]_TX_CONFIG[15]_wide_mux_4_OUT<7> ) - ); - LUT6 #( - .INIT ( 64'hFFFF444044404440 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_TRIGGER_T_OR_14_o1 ( - .I0(gmii_tx_en), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_192 ), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_TRIGGER_T_OR_14_o ) - ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mcount_CODE_GRP_CNT_xor<1>11 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Result [1]) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mram_CODE_GRP_CNT[1]_GND_21_o_Mux_5_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mram_CODE_GRP_CNT[1]_GND_21_o_Mux_5_o ) - ); - LUT4 #( - .INIT ( 16'h0040 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_EVEN_AND_8_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1_208 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I2(gmii_tx_en), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_EVEN_AND_8_o ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_EVEN_AND_42_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_EVEN_AND_42_o ) - ); - LUT6 #( - .INIT ( 64'h0000577757770000 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/Mmux_GOOD_CGS[1]_GND_23_o_mux_30_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [0]), - .I5(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [1]), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_GND_23_o_mux_30_OUT<1> ) - ); - LUT5 #( - .INIT ( 32'hA888FFFF )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/_n0103_inv1 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/_n0103_inv ) - ); - LUT5 #( - .INIT ( 32'h01115555 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/Mmux_GOOD_CGS[1]_GND_23_o_mux_30_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [0]), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_GND_23_o_mux_30_OUT<0> ) - ); - LUT6 #( - .INIT ( 64'hD8B0D8B0E8E0F8F0 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1-In21 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_PWR_19_o_equal_19_o ), - .I5(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1-In2 ) - ); - LUT3 #( - .INIT ( 8'hF1 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_01 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SIGNAL_DETECT_REG_234 ), - .I1(\U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [1]), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In1_0 ) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_PWR_19_o_equal_19_o<1>1 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [0]), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [1]), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_PWR_19_o_equal_19_o ) - ); - LUT5 #( - .INIT ( 32'hFFFEFEFE )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ), - .I2(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT_119 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ) - ); - LUT4 #( - .INIT ( 16'h5554 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [1]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'h5554 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT41 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [3]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<3> ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT31 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [2]), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<2> ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT61 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [5]), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<5> ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT81 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [7]), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<7> ) - ); - LUT4 #( - .INIT ( 16'h0800 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K29p71 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o1_235 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K29p7 ) - ); - LUT6 #( - .INIT ( 64'h8000000000000000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I5(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o1_235 ) - ); - LUT4 #( - .INIT ( 16'hFF54 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [0]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<0> ) - ); - LUT5 #( - .INIT ( 32'hFFFF4540 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT51 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_ERR_284 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [4]), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<4> ) - ); - LUT5 #( - .INIT ( 32'h08080800 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/S_WAIT_FOR_K_AND_144_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_327 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_270 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_267 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_WAIT_FOR_K_AND_144_o ) - ); - LUT4 #( - .INIT ( 16'h2000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K23p71 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o1_235 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K23p7 ) - ); - LUT5 #( - .INIT ( 32'h00200000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXFIFO_ERR_RXDISPERR_OR_36_o ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o1_235 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K27p7_RXFIFO_ERR_AND_111_o ) - ); - LUT4 #( - .INIT ( 16'hFF10 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mmux_RXDATA_REG5[7]_GND_24_o_mux_9_OUT71 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [6]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5[7]_GND_24_o_mux_9_OUT<6> ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG[1]_IDLE_REG[2]_OR_114_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [1]), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG [2]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/IDLE_REG[1]_IDLE_REG[2]_OR_114_o ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG[0]_RX_CONFIG_VALID_REG[3]_OR_113_o<0>1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [0]), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [1]), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [2]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG [3]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID_REG[0]_RX_CONFIG_VALID_REG[3]_OR_113_o ) - ); - LUT3 #( - .INIT ( 8'hEA )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_EXT_ILLEGAL_K_REG2_OR_83_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_REG2_281 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_308 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG3_297 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_EXT_ILLEGAL_K_REG2_OR_83_o ) - ); - LUT3 #( - .INIT ( 8'hEA )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_EXTEND_OR_65_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_290 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_267 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_EXTEND_OR_65_o ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_K28p5_REG1_AND_167_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_315 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_326 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_K28p5_REG1_AND_167_o ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_EVEN_AND_127_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_EVEN_AND_127_o ) - ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RXFIFO_ERR_RXDISPERR_OR_36_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ), - .I2(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXFIFO_ERR_RXDISPERR_OR_36_o ) - ); - LUT2 #( - .INIT ( 4'hD )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I1(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT3_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [2]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .O(N2) - ); - LUT6 #( - .INIT ( 64'hFFFFBBAB55551101 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT3 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I3(N2), - .I4(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [2]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<2> ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT4_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .O(N6) - ); - LUT6 #( - .INIT ( 64'hFFFFBBAB55551101 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT4 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [3]), - .I4(N6), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [3]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<3> ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT7_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .O(N8) - ); - LUT6 #( - .INIT ( 64'hDDDDDCCC11111000 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT7 ( - .I0(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [6]), - .I4(N8), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [1]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<6> ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFDFFFFFFFF )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o1 ( - .I0(gmii_txd[3]), - .I1(gmii_txd[7]), - .I2(gmii_txd[4]), - .I3(gmii_txd[5]), - .I4(gmii_txd[6]), - .I5(gmii_txd[2]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o1_331 ) - ); - LUT6 #( - .INIT ( 64'hA8AAAAAA20222222 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o2 ( - .I0(gmii_tx_er), - .I1(gmii_tx_en), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o1_331 ), - .I3(gmii_txd[0]), - .I4(gmii_txd[1]), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o2_332 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFFFFF5540 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [1]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT2 ) - ); - LUT4 #( - .INIT ( 16'h8B88 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT22 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT2 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<1> ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF55555540 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXD_REG1 [0]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT1 ) - ); - LUT4 #( - .INIT ( 16'h8B88 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT12 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [0]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_PWR_17_o_CONFIG_DATA[7]_mux_21_OUT1 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/PWR_17_o_CONFIG_DATA[7]_mux_21_OUT<0> ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_ISOLATE_AND_182_o_SW0 ( - .I0(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I1(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [2]), - .O(N14) - ); - LUT6 #( - .INIT ( 64'h5555555144444440 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_ISOLATE_AND_182_o ( - .I0(N14), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_288 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG3_294 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_ISOLATE_AND_182_o_244 ) - ); - LUT4 #( - .INIT ( 16'hAAA8 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EVEN_RXCHARISK_AND_115_o_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_278 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_K_279 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_280 ), - .O(N18) - ); - LUT6 #( - .INIT ( 64'h00000000A0A88088 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EVEN_RXCHARISK_AND_115_o ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I4(N18), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_D21p5_AND_116_o_norst ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/EVEN_RXCHARISK_AND_115_o_258 ) - ); - LUT2 #( - .INIT ( 4'hB )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p51_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I1(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .O(N20) - ); - LUT6 #( - .INIT ( 64'h4000000000000000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I5(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o ) - ); - LUT6 #( - .INIT ( 64'h0000000400000000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o2 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I5(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o1_339 ) - ); - LUT6 #( - .INIT ( 64'h0013001100030000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o3 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o1_339 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_D21p5_AND_116_o_norst ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I2(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .O(N22) - ); - LUT6 #( - .INIT ( 64'h0000000000000001 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I5(N22), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_242 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_C_REG3_OR_59_o_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG2_236 ), - .O(N24) - ); - LUT6 #( - .INIT ( 64'hFFFF8AAACEEE8AAA )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_C_REG3_OR_59_o ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG3_316 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_298 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I4(N24), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_315 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_C_REG3_OR_59_o_240 ) - ); - LUT6 #( - .INIT ( 64'hE8FFFFFFFFFFFFFF )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I5(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o1 ) - ); - LUT5 #( - .INIT ( 32'hFFFFFFFE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o13 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I2(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o13_344 ) - ); - LUT4 #( - .INIT ( 16'hFF17 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o14 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o13_344 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o14_345 ) - ); - LUT5 #( - .INIT ( 32'h88888000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_320 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_REG1_319 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o1_346 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFF80FF80FF80 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o2 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/D0p0_REG_322 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o1_346 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_T_REG2_OR_64_o ) - ); - LUT4 #( - .INIT ( 16'hFFFE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/ILLEGAL_K_REG2_285 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG3_297 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o1_347 ) - ); - LUT5 #( - .INIT ( 32'h54545554 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o2 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_REG1_319 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_320 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG1_321 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o2_348 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_C_REG1_AND_125_o_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXCHARISK_REG1_315 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_298 ), - .O(N26) - ); - LUT6 #( - .INIT ( 64'h0010001000100000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_C_REG1_AND_125_o ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXFIFO_ERR_RXDISPERR_OR_36_o ), - .I1(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I3(N26), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG1_317 ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_313 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_C_REG1_AND_125_o_257 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/V ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_glue_set_350 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_glue_set_351 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/R ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_glue_set_352 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ) - ); - FDS \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_glue_rst_353 ), - .S(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_glue_set_354 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_glue_set_355 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID_glue_set_356 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV_glue_set_357 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_glue_set_358 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_267 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_glue_set_359 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_269 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_glue_set_360 ), - .R(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_270 ) - ); - FDR \U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_rstpot_361 ), - .R(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_188 ) - ); - FDS \U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_rstpot_362 ), - .S(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_rstpot_363 ), - .Q(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_rstpot_364 ), - .Q(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_rstpot_365 ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_190 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_rstpot_366 ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_131 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_rstpot_367 ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_192 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/S ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_rstpot_368 ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ) - ); - FD \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_0 ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_0_rstpot_369 ), - .Q(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA [0]) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_rstpot_370 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_313 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/C ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_rstpot_371 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_324 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_rstpot_372 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_283 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_rstpot_373 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_288 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFA9999995 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o12 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDISPERR_INT_109 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I5(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o12_343 ) - ); - FD \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_rstpot_374 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_278 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o15_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I1(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .O(N28) - ); - LUT6 #( - .INIT ( 64'h0400000004440044 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o12_343 ), - .I1(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o1 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I4(N28), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_POS_FALSE_NIT_NEG_OR_108_o14_345 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_rstpot_374 ) - ); - LUT2 #( - .INIT ( 4'hB )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_rstpot_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_320 ), - .O(N34) - ); - LUT6 #( - .INIT ( 64'h00000000AAAAAA02 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ), - .I1(N34), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_EVEN_AND_127_o ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o1_347 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/T_REG2_R_REG1_OR_79_o2_348 ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/RESET_SYNC_STATUS_OR_51_o ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DATA_ERROR_rstpot_373 ) - ); - LUT5 #( - .INIT ( 32'hE8FFFFFF )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o4_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .O(N38) - ); - LUT5 #( - .INIT ( 32'hFCBDFFFF )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o4_SW1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .O(N39) - ); - LUT4 #( - .INIT ( 16'hDFFF )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p51_SW1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .O(N43) - ); - LUT6 #( - .INIT ( 64'h0010000000000010 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA[7]_RXNOTINTABLE_AND_211_o1 ( - .I0(N20), - .I1(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I3(N43), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I5(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA[7]_RXNOTINTABLE_AND_211_o ) - ); - LUT3 #( - .INIT ( 8'hBF )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p51_SW2 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .O(N45) - ); - LUT6 #( - .INIT ( 64'h0000000004000000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/K28p52 ( - .I0(N20), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I3(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I4(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .I5(N45), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5 ) - ); - LUT2 #( - .INIT ( 4'hE )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o4_SW2 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I1(\U0/xst_options.gpcs_pma_inst/RXNOTINTABLE_INT_108 ), - .O(N57) - ); - LUT6 #( - .INIT ( 64'h0000000400200024 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o5 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .I3(N57), - .I4(N38), - .I5(N39), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_POS_RXNOTINTABLE_AND_203_o ) - ); - LUT2 #( - .INIT ( 4'hB )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o3_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .O(N59) - ); - LUT6 #( - .INIT ( 64'h0013000300110000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/C_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .I1(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .I2(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .I3(N59), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o1_339 ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/D21p5_D2p2_OR_38_o ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_rstpot_371 ) - ); - FD \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN_rstpot_383 ), - .Q(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN ) - ); - FD #( - .INIT ( 1'b0 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS ( - .C(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_rstpot_384 ), - .Q(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ) - ); - LUT4 #( - .INIT ( 16'h6A2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_188 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_rstpot_361 ) - ); - LUT3 #( - .INIT ( 8'h2F )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT_119 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_glue_set_354 ) - ); - LUT6 #( - .INIT ( 64'h0001010101010101 )) - \U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ), - .I1(\U0/xst_options.gpcs_pma_inst/RXBUFSTATUS_INT [1]), - .I2(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_71 ), - .I3(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd2_69 ), - .I4(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd3_70 ), - .I5(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd1_68 ), - .O(\U0/xst_options.gpcs_pma_inst/RX_RST_SM_FSM_FFd4_rstpot_363 ) - ); - LUT6 #( - .INIT ( 64'h0001010101010101 )) - \U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/RESET_INT_128 ), - .I1(\U0/xst_options.gpcs_pma_inst/TXBUFERR_INT_103 ), - .I2(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_78 ), - .I3(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd2_76 ), - .I4(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd3_77 ), - .I5(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd1_75 ), - .O(\U0/xst_options.gpcs_pma_inst/TX_RST_SM_FSM_FFd4_rstpot_364 ) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_0_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I1(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_188 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CONFIG_DATA_0_rstpot_369 ) - ); - LUT5 #( - .INIT ( 32'h2AFF2A2A )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_270 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/SYNC_STATUS_REG_295 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/WAIT_FOR_K_glue_set_360 ) - ); - LUT3 #( - .INIT ( 8'hBA )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_glue_set_351 ) - ); - LUT3 #( - .INIT ( 8'hBA )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG2_311 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_290 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_glue_set_355 ) - ); - LUT3 #( - .INIT ( 8'hBA )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/FROM_RX_CX_292 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_INVALID_glue_set_356 ) - ); - LUT3 #( - .INIT ( 8'h02 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ), - .I1(gmii_tx_en), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_T_rstpot_367 ) - ); - LUT4 #( - .INIT ( 16'h0040 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_REG2_236 ), - .I2(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/RXCLKCORCNT_INT [2]), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/C_HDR_REMOVED_REG_rstpot_370 ) - ); - LUT5 #( - .INIT ( 32'hFFFF4440 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1_208 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_glue_set_352 ) - ); - LUT2 #( - .INIT ( 4'hB )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV_glue_set_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/EOP_REG1_289 ), - .I1(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV ), - .O(N71) - ); - LUT6 #( - .INIT ( 64'h0200FFFF0200AAAA )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I1(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [2]), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG3_310 ), - .I4(N71), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/RX_DV_glue_set_357 ) - ); - LUT4 #( - .INIT ( 16'hFFDF )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_glue_set_SW1 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/I_REG_318 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_327 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_NIT_278 ), - .O(N73) - ); - LUT6 #( - .INIT ( 64'h44444445CCCCCCCD )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_269 ), - .I2(N73), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_DATA_280 ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_K_279 ), - .I5(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_glue_set_359 ) - ); - LUT3 #( - .INIT ( 8'h08 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_glue_rst_SW1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .O(N75) - ); - LUT6 #( - .INIT ( 64'h00000000857A7A85 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_glue_rst ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [5]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [7]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [6]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISP5 ), - .I5(N75), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_glue_rst_353 ) - ); - LUT2 #( - .INIT ( 4'h8 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_glue_set_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/RECEIVE_268 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_REG1_319 ), - .O(N77) - ); - LUT6 #( - .INIT ( 64'hFFFF022202220222 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_267 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_327 ), - .I2(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_323 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/EVEN_124 ), - .I4(N77), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_glue_set_358 ) - ); - LUT2 #( - .INIT ( 4'hB )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_glue_set_SW1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1_208 ), - .O(N79) - ); - LUT6 #( - .INIT ( 64'hFFFF445444544454 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_glue_set ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_XMIT_DATA_INT_AND_20_o2_332 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ), - .I3(N79), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_glue_set_350 ) - ); - LUT4 #( - .INIT ( 16'hFFFB )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_rstpot_SW0 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .O(N81) - ); - LUT6 #( - .INIT ( 64'h5F5F0F0F5F5C0F0C )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I3(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I5(N81), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_rstpot_365 ) - ); - LUT3 #( - .INIT ( 8'hA8 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_rstpot_362 ) - ); - LUT3 #( - .INIT ( 8'h2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRPISK_GND_21_o_MUX_79_o11 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_190 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRPISK_GND_21_o_MUX_79_o ) - ); - LUT4 #( - .INIT ( 16'hEA2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT11 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [0]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<0> ) - ); - LUT3 #( - .INIT ( 8'h2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT21 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<1> ) - ); - LUT4 #( - .INIT ( 16'hEA2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT31 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [2]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<2> ) - ); - LUT3 #( - .INIT ( 8'h2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT41 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [3]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<3> ) - ); - LUT4 #( - .INIT ( 16'h2AEA )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT51 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [4]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<4> ) - ); - LUT3 #( - .INIT ( 8'h2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT61 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [5]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<5> ) - ); - LUT3 #( - .INIT ( 8'hEA )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT71 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [6]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<6> ) - ); - LUT4 #( - .INIT ( 16'hEA2A )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_CODE_GRP[7]_GND_21_o_mux_24_OUT81 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP [7]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP[7]_GND_21_o_mux_24_OUT<7> ) - ); - LUT3 #( - .INIT ( 8'h20 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/_n0234<1>1 ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/C1_OR_C2_188 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/_n0234 [1]) - ); - LUT4 #( - .INIT ( 16'h0040 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/DISPARITY_183 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/SYNC_DISPARITY_191 ), - .I3(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TXCHARDISPVAL_rstpot_366 ) - ); - LUT6 #( - .INIT ( 64'h0000000000000008 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_rstpot ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I1(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .I2(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_RX_RESET_INT ), - .I3(\U0/xst_options.gpcs_pma_inst/RECEIVER/K28p5_REG1_EVEN_AND_127_o ), - .I4(\U0/xst_options.gpcs_pma_inst/RECEIVER/R_299 ), - .I5(\U0/xst_options.gpcs_pma_inst/RECEIVER/S_327 ), - .O(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXT_ILLEGAL_K_rstpot_372 ) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In2 ( - .I0(N83), - .I1(N84), - .S(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In2_223 ) - ); - LUT6 #( - .INIT ( 64'hF0F4540400040404 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In2_F ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I1(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT_119 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I5(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_PWR_19_o_equal_19_o ), - .O(N83) - ); - LUT5 #( - .INIT ( 32'hDBDB8988 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4-In2_G ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXCHARISCOMMA_INT_119 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .O(N84) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN_rstpot ( - .I0(N85), - .I1(N86), - .S(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN_rstpot_383 ) - ); - LUT6 #( - .INIT ( 64'hAAAAAA2AAAAAAB2B )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN_rstpot_F ( - .I0(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I3(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I5(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .O(N85) - ); - LUT5 #( - .INIT ( 32'hFFFFA889 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN_rstpot_G ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I4(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/ENCOMMAALIGN ), - .O(N86) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_rstpot ( - .I0(N87), - .I1(N88), - .S(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_rstpot_384 ) - ); - LUT6 #( - .INIT ( 64'hAAAAAAA8AEAAAEA8 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_rstpot_F ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I5(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .O(N87) - ); - LUT5 #( - .INIT ( 32'h222A22A8 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_rstpot_G ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .O(N88) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2-In22 ( - .I0(N89), - .I1(N90), - .S(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2-In2 ) - ); - LUT6 #( - .INIT ( 64'hF212E2A2F69AE6AA )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2-In22_F ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS[1]_PWR_19_o_equal_19_o ), - .I5(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .O(N89) - ); - LUT3 #( - .INIT ( 8'h20 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2-In22_G ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .O(N90) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_TX_PACKET_CODE_GRP_CNT[1]_MUX_73_o11 ( - .I0(N91), - .I1(N92), - .S(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_CODE_GRP_CNT[1]_MUX_73_o ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF00000001 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_TX_PACKET_CODE_GRP_CNT[1]_MUX_73_o11_F ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_195 ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/V_184 ), - .I2(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/T_193 ), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/R_185 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_PACKET_186 ), - .I5(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/CONFIGURATION_VECTOR_REG [3]), - .O(N91) - ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mmux_TX_PACKET_CODE_GRP_CNT[1]_MUX_73_o11_G ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [1]), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(N92) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_rstpot ( - .I0(N93), - .I1(N94), - .S(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TRIGGER_S_194 ), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_rstpot_368 ) - ); - LUT6 #( - .INIT ( 64'h0010000000100010 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_rstpot_F ( - .I0(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_EN_REG1_209 ), - .I1(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .I2(gmii_tx_en), - .I3(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .I4(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/TX_ER_REG1_208 ), - .I5(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(N93) - ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/xst_options.gpcs_pma_inst/TRANSMITTER/S_rstpot_G ( - .I0(\NlwRenamedSig_OI_U0/xst_options.gpcs_pma_inst/MGT_TX_RESET_INT ), - .I1(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/XMIT_CONFIG_INT_187 ), - .O(N94) - ); - MUXF7 \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3-In32 ( - .I0(N95), - .I1(N96), - .S(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd4_222 ), - .O(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3-In3 ) - ); - LUT6 #( - .INIT ( 64'hAA8AAB8AAA8AAA8A )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3-In32_F ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd2_220 ), - .I2(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .I4(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [0]), - .I5(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/GOOD_CGS [1]), - .O(N95) - ); - LUT4 #( - .INIT ( 16'h5501 )) - \U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3-In32_G ( - .I0(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd3_221 ), - .I1(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/CGBAD ), - .I2(\U0/xst_options.gpcs_pma_inst/RXCHARISK_INT_118 ), - .I3(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/STATE_FSM_FFd1_219 ), - .O(N96) - ); - INV \U0/xst_options.gpcs_pma_inst/TRANSMITTER/Mcount_CODE_GRP_CNT_xor<0>11_INV_0 ( - .I(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/CODE_GRP_CNT [0]), - .O(\U0/xst_options.gpcs_pma_inst/TRANSMITTER/Result [0]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/Mshreg_STATUS_VECTOR_0 ( - .A0(NlwRenamedSig_OI_status_vector[7]), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_123 ), - .Q(\U0/xst_options.gpcs_pma_inst/Mshreg_STATUS_VECTOR_0_405 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/Mshreg_STATUS_VECTOR_0_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/STATUS_VECTOR_0 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/Mshreg_STATUS_VECTOR_0_405 ), - .Q(\NlwRenamedSignal_U0/xst_options.gpcs_pma_inst/STATUS_VECTOR_0 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_7 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [7]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_7_406 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_7_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_7 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_7_406 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [7]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_6 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [6]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_6_407 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_6_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_6 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_6_407 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [6]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_5 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [5]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_5_408 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_5_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_5 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_5_408 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [5]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_2 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [2]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_2_409 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_2_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_2 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_2_409 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [2]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_4 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [4]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_4_410 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_4_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_4 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_4_410 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [4]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_3 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [3]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_3_411 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_3_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_3 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_3_411 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [3]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_EXTEND_REG3 ( - .A0(NlwRenamedSig_OI_status_vector[7]), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG1_309 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_EXTEND_REG3_412 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_EXTEND_REG3_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_EXTEND_REG3_412 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/EXTEND_REG3_308 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_1 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [1]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_1_413 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_1_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_1 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_1_413 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [1]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_0 ( - .A0(N0), - .A1(N0), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RXDATA_INT [0]), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_0_414 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_0_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5_0 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_RXDATA_REG5_0_414 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/RXDATA_REG5 [0]) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_CGBAD_REG2 ( - .A0(N0), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_298 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/CGBAD_REG2 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_CGBAD_REG2_Q15_UNCONNECTED ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_SOP_REG2 ( - .A0(NlwRenamedSig_OI_status_vector[7]), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_291 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_SOP_REG2_415 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_SOP_REG2_Q15_UNCONNECTED ) - ); - FDE \U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG2 ( - .C(userclk2), - .CE(N0), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_SOP_REG2_415 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/SOP_REG2_311 ) - ); - SRLC16E #( - .INIT ( 16'h0000 )) - \U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_FALSE_CARRIER_REG2 ( - .A0(N0), - .A1(NlwRenamedSig_OI_status_vector[7]), - .A2(NlwRenamedSig_OI_status_vector[7]), - .A3(NlwRenamedSig_OI_status_vector[7]), - .CE(N0), - .CLK(userclk2), - .D(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_269 ), - .Q(\U0/xst_options.gpcs_pma_inst/RECEIVER/FALSE_CARRIER_REG2 ), - .Q15(\NLW_U0/xst_options.gpcs_pma_inst/RECEIVER/Mshreg_FALSE_CARRIER_REG2_Q15_UNCONNECTED ) - ); - -// synthesis translate_on - -endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp.veo b/fpga/usrp3/top/x300/coregen/gige_sfp.veo deleted file mode 100644 index 89830a7c2..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp.veo +++ /dev/null @@ -1,95 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used solely * -* for design, simulation, implementation and creation of design files * -* limited to Xilinx devices or technologies. Use with non-Xilinx * -* devices or technologies is expressly prohibited and immediately * -* terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * -* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * -* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * -* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * -* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * -* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * -* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * -* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * -* PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support appliances, * -* devices, or systems. Use in such applications are expressly * -* prohibited. * -* * -* (c) Copyright 1995-2012 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ - -/******************************************************************************* -* Generated from core with identifier: * -* xilinx.com:ip:gig_eth_pcs_pma:11.4 * -* * -* The Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE(TM) provides the * -* functionality to implement one of two different specifications: * -* firstly the IEEE 802.3 1000BASE-X specification; secondly the * -* Serial-GMII (SGMII) specification which is closely based on * -* 1000BASE-X. The core provides a choice of physical interface * -* options: a Ten-Bit-Interface (TBI) for connection to an external * -* SERDES; high speed serial functionality using the device specific * -* transceivers in Virtex-7, Kintex-7, Artix-7, Virtex-4, Virtex-5, * -* Virtex-6 and Spartan-6; SGMII standard only - LVDS using SelectIO in * -* Virtex-6 devices -2 speed grade and faster. All options provide up * -* to 1 gigabit per second total bandwidth. When perfoming the SGMII * -* standard, the core can carry Ethernet traffic up to 1 gigabit per * -* second total bandwidth; this is inclusive of 10Mbps, 100Mbps and * -* 1Gbps Ethernet speeds. The core is designed to interface to the * -* LogiCORE Tri-Mode Ethernet MAC from Xilinx to provide a complete * -* solution. * -*******************************************************************************/ - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -gige_sfp your_instance_name ( - .reset(reset), // input reset - .signal_detect(signal_detect), // input signal_detect - .mgt_rx_reset(mgt_rx_reset), // output mgt_rx_reset - .mgt_tx_reset(mgt_tx_reset), // output mgt_tx_reset - .userclk(userclk), // input userclk - .userclk2(userclk2), // input userclk2 - .dcm_locked(dcm_locked), // input dcm_locked - .rxbufstatus(rxbufstatus), // input [1 : 0] rxbufstatus - .rxchariscomma(rxchariscomma), // input rxchariscomma - .rxcharisk(rxcharisk), // input rxcharisk - .rxclkcorcnt(rxclkcorcnt), // input [2 : 0] rxclkcorcnt - .rxdata(rxdata), // input [7 : 0] rxdata - .rxdisperr(rxdisperr), // input rxdisperr - .rxnotintable(rxnotintable), // input rxnotintable - .rxrundisp(rxrundisp), // input rxrundisp - .txbuferr(txbuferr), // input txbuferr - .powerdown(powerdown), // output powerdown - .txchardispmode(txchardispmode), // output txchardispmode - .txchardispval(txchardispval), // output txchardispval - .txcharisk(txcharisk), // output txcharisk - .txdata(txdata), // output [7 : 0] txdata - .enablealign(enablealign), // output enablealign - .gmii_txd(gmii_txd), // input [7 : 0] gmii_txd - .gmii_tx_en(gmii_tx_en), // input gmii_tx_en - .gmii_tx_er(gmii_tx_er), // input gmii_tx_er - .gmii_rxd(gmii_rxd), // output [7 : 0] gmii_rxd - .gmii_rx_dv(gmii_rx_dv), // output gmii_rx_dv - .gmii_rx_er(gmii_rx_er), // output gmii_rx_er - .gmii_isolate(gmii_isolate), // output gmii_isolate - .configuration_vector(configuration_vector), // input [4 : 0] configuration_vector - .status_vector(status_vector) // output [15 : 0] status_vector -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file gige_sfp.v when simulating -// the core, gige_sfp. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp.xco b/fpga/usrp3/top/x300/coregen/gige_sfp.xco deleted file mode 100644 index 87b7e9721..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.3 -# Date: Fri Dec 21 21:52:41 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.4 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg900 -SET removerpms = false -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.4 -# END Select -# BEGIN Parameters -CSET auto_negotiation=false -CSET component_name=gige_sfp -CSET management_interface=false -CSET physical_interface=Transceiver -CSET sgmii_mode=10_100_1000 -CSET sgmii_phy_mode=false -CSET standard=1000BASEX -CSET timing_sim=false -CSET transceiver_tile=A -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-06-05T17:19:16Z -# END Extra information -GENERATE -# CRC: 9dc62bf3 diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp.xise b/fpga/usrp3/top/x300/coregen/gige_sfp.xise deleted file mode 100644 index a238a5d2d..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp.xise +++ /dev/null @@ -1,361 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/doc/gig_eth_pcs_pma_v11_4_vinfo.html b/fpga/usrp3/top/x300/coregen/gige_sfp/doc/gig_eth_pcs_pma_v11_4_vinfo.html deleted file mode 100644 index c07e439b5..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/doc/gig_eth_pcs_pma_v11_4_vinfo.html +++ /dev/null @@ -1,287 +0,0 @@ - - -gig_eth_pcs_pma_v11_4_vinfo - - - -

-
-CHANGE LOG for Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v11.4
-
-Release Date:  July 25, 2012 
---------------------------------------------------------------------------------
-
-    
-Table of Contents
-
-1. INTRODUCTION 
-2. DEVICE SUPPORT    
-3. NEW FEATURE HISTORY   
-4. RESOLVED ISSUES 
-5. KNOWN ISSUES & LIMITATIONS 
-6. TECHNICAL SUPPORT & FEEDBACK
-7. CORE RELEASE HISTORY 
-8. LEGAL DISCLAIMER 
-
---------------------------------------------------------------------------------
-
-1. INTRODUCTION
-
-  This file contains the change log for all released versions of the Xilinx 
-  LogiCORE IP core  Ethernet 1000BASE-X PCS/PMA or SGMII. 
-  
-  For the latest core updates, see the product page at:
-
-    www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm
-
-  For installation instructions for this release, please go to:
-
-    www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-  For system requirements, see:
-
-    www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-
-2. DEVICE SUPPORT 
-
-  2.1. ISE
-
-    The following device families are supported by the core for this release:
-
-    Virtex-7 devices
-      Virtex-7                            
-      Virtex-7 HT/XT                
-
-    Kintex-7 devices
-      Kintex-7
-
-    Artix-7 devices
-      Artix-7
-
-    Zynq-7000 devices
-      Zynq-7000
-
-    Virtex-6 devices                        
-      Virtex-6                              CXT/LXT/SXT/HXT
-      Virtex-6 Lower Power (-1L)            LXT/SXT
-      Defense Grade Virtex-6Q     (XQ)      LXT/SXT
-
-    Spartan-6 devices
-      Spartan-6                             LX/LXT
-      Defense Grade Spartan-6Q              LX/LXT
-
-    All Virtex-5 devices
-
-    Virtex-4 devices
-      Virtex-4                              LX/SX/FX
-
-    Spartan-3 device families
-      Spartan-3
-      Spartan-3A and Spartan-3AN
-
-      Spartan-3A DSP
-
-      Spartan-3E
-
-    
-  2.2. VIVADO
-
- 
-    The following device families are supported by the core for this release:
-
-    Virtex-7 devices
-      Virtex-7                            
-      Virtex-7 HT/XT                
-
-    Kintex-7 devices
-      Kintex-7
-
-    Artix-7 devices
-      Artix-7
-
-    Zynq-7000 devices
-      Zynq-7000
-
-
-3. NEW FEATURE HISTORY
-
-
-  3.1 ISE
-
-    v11.4  
-  
-    - ISE 14.2 software support
-    - Support for Zynq Devices
-
-
-    v11.3
-  
-    - ISE 14.1 software support
-    - Support for Artix7 Devices
-    - Support for Virtex-7 HT Devices
-
-    v11.2 
-  
-    - ISE 13.4 software support
-    - Added programability through configuration vector
-
-
-    v11.1
-
-    - ISE 13.1 software support
-    - Updated status vector
-    - SGMII PHY mode
-    - Support for Kintex7 Devices
-    - Support for Virtex7 Devices
-
-
-  3.2 Vivado
-
-    v11.4
-    - Vivado 2012.2 software support
-    - Initial public release
-    - Block level user editable logic delivered as part of the core
-
-
-
-4. RESOLVED ISSUES 
-
-  4.1 ISE
-
-    The following issues are resolved in the indicated IP versions:
-
-    v11.4
-      - None
-
-    v11.3
-      - AR: 45676
-      - AR: 46123
-
-    v11.2
-      - AR: 42672
-      - AR: 36961
-      - AR: 42842
-      - AR: 43421
-      - AR: 43482
-
-    v11.1
-      - AR: 36957
-      - AR: 36961
-      - AR: 35681
-
-
-  4.2 Vivado
-
-    v11.4
-      - None
-
-
-5. KNOWN ISSUES & LIMITATIONS 
-
-
-  - For a comprehensive listing of Known Issues for this core, please see the IP 
-    Release Notes Guide,  
-    
-    www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-
-
-6. TECHNICAL SUPPORT & FEEDBACK
-
-   To obtain technical support, create a WebCase at www.xilinx.com/support.  
-   Questions are routed to a team with expertise using this product.  
-   Feedback on this IP core may also be submitted under the "Leave Feedback" 
-   menu item in Vivado/PlanAhead.
-
-   Xilinx provides technical support for use of this product when used
-   according to the guidelines described in the core documentation, and
-   cannot guarantee timing, functionality, or support of this product for
-   designs that do not follow specified guidelines.
-
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-07/25/2012  Xilinx, Inc. 11.4          ISE 14.2 and Vivado 2012.2.
-                                       Support for Zynq Devices. Sync LVDS Solution
-04/24/2012  Xilinx, Inc. 11.3          ISE 14.1, Artix-7 and Vivado 2012.1 support
-01/18/2012  Xilinx, Inc. 11.2          ISE 13.4 Support
-09/06/2011  Xilinx, Inc. 11.1 Rev 1    Patch release for ISE 13.1
-03/01/2011  Xilinx, Inc. 11.1          ISE 13.1  and Virtex-7 / Kintex-7 support
-07/30/2010  Xilinx, Inc. 10.5 Rev 1    Patch release for ISE 12.2
-07/23/2010  Xilinx, Inc. 10.5          ISE 12.2 support and Virtex-6 LVDS I/O
-04/19/2010  Xilinx, Inc. 10.4          Release for ISE 12.1
-03/09/2010  Xilinx, Inc. 10.3 Rev 1    Patch release for ISE 11.5
-09/16/2009  Xilinx, Inc. 10.3          11.3, Virtex-6 HXT and Lower Power support
-06/24/2009  Xilinx, Inc. 10.2          Release for ISE 11.2 and Spartan-6 support
-04/27/2009  Xilinx, Inc. 10.1          Release for ISE 11.1
-03/24/2008  Xilinx, Inc.  9.1          Release for ISE 10.1
-08/15/2007  Xilinx, Inc.  9.0          Release for 9.2i
-04/02/2007  Xilinx, Inc.  8.1 Rev 1    Spartan-3A DSP support
-03/05/2007  Xilinx, Inc.  8.1          Release for ISE 9.1i
-10/26/2006  Xilinx, Inc.  8.0          Release for Virtex-5 and Spartan-3A
-07/19/2006  Xilinx, Inc.  7.1          Release for ISE 8.2i
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- - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/doc/pg047-gig-eth-pcs-pma.pdf b/fpga/usrp3/top/x300/coregen/gige_sfp/doc/pg047-gig-eth-pcs-pma.pdf deleted file mode 100644 index 9598f5ffe..000000000 Binary files a/fpga/usrp3/top/x300/coregen/gige_sfp/doc/pg047-gig-eth-pcs-pma.pdf and /dev/null differ diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_block.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_block.v deleted file mode 100644 index 1f1aed3e7..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_block.v +++ /dev/null @@ -1,259 +0,0 @@ -//------------------------------------------------------------------------------ -// File : gige_sfp_block.v -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// Description: This Core Block Level wrapper connects the core to a -// Series-7 Transceiver. -// -// -// ------------------------------------------------------------ -// | Core Block wrapper | -// | | -// | ------------------ ----------------- | -// | | Core | | Transceiver | | -// | | | | | | -// | | | | | | -// | | | | | | -// ---------->| GMII |--------->| TXP |--------> -// | | Tx | | TXN | | -// | | | | | | -// | | | | | | -// | | | | | | -// | | | | | | -// | | | | | | -// | | GMII | | RXP | | -// <----------| Rx |<---------| RXN |<-------- -// | | | | | | -// | ------------------ ----------------- | -// | | -// ------------------------------------------------------------ -// -// - - -`timescale 1 ps/1 ps - -//------------------------------------------------------------------------------ -// The module declaration for the Core Block wrapper. -//------------------------------------------------------------------------------ - -module gige_sfp_block - ( - // Transceiver Interface - //---------------------- - - input gtrefclk, // Very high quality 125MHz clock for GT transceiver. - output txp, // Differential +ve of serial transmission from PMA to PMD. - output txn, // Differential -ve of serial transmission from PMA to PMD. - input rxp, // Differential +ve for serial reception from PMD to PMA. - input rxn, // Differential -ve for serial reception from PMD to PMA. - - output txoutclk, // txoutclk from GT transceiver (62.5MHz) - output resetdone, // The GT transceiver has completed its reset cycle - input mmcm_locked, // locked indication from MMCM - input userclk, // 62.5MHz global clock. - input userclk2, // 125MHz global clock. - input independent_clock_bufg,// 200MHz Independent clock, - input pma_reset, // transceiver PMA reset signal - - // GMII Interface - //--------------- - input [7:0] gmii_txd, // Transmit data from client MAC. - input gmii_tx_en, // Transmit control signal from client MAC. - input gmii_tx_er, // Transmit control signal from client MAC. - output [7:0] gmii_rxd, // Received Data to client MAC. - output gmii_rx_dv, // Received control signal to client MAC. - output gmii_rx_er, // Received control signal to client MAC. - output gmii_isolate, // Tristate control to electrically isolate GMII. - - // Management: Alternative to MDIO Interface - //------------------------------------------ - - input [4:0] configuration_vector, // Alternative to MDIO interface. - - // General IO's - //------------- - output [15:0] status_vector, // Core status. - input reset, // Asynchronous reset for entire core. - input signal_detect, // Input from PMD to indicate presence of optical input. - output [31:0] misc_debug, - output [15:0] int_data - - ); - - - //--------------------------------------------------------------------------- - // Internal signals used in this block level wrapper. - //--------------------------------------------------------------------------- - - // Core <=> Transceiver interconnect - wire plllock; // The PLL Locked status of the Transceiver - wire mgt_rx_reset; // Reset for the receiver half of the Transceiver - wire mgt_tx_reset; // Reset for the transmitter half of the Transceiver - wire [1:0] rxbufstatus; // Elastic Buffer Status (bit 1 asserted indicates overflow or underflow). - wire rxchariscomma; // Comma detected in RXDATA. - wire rxcharisk; // K character received (or extra data bit) in RXDATA. - wire [2:0] rxclkcorcnt; // Indicates clock correction. - wire [7:0] rxdata; // Data after 8B/10B decoding. - wire rxrundisp; // Running Disparity after current byte, becomes 9th data bit when RXNOTINTABLE='1'. - wire rxdisperr; // Disparity-error in RXDATA. - wire rxnotintable; // Non-existent 8B/10 code indicated. - wire txbuferr; // TX Buffer error (overflow or underflow). - wire loopback; // Set the Transceiver for loopback. - wire powerdown; // Powerdown the Transceiver - wire txchardispmode; // Set running disparity for current byte. - wire txchardispval; // Set running disparity value. - wire txcharisk; // K character transmitted in TXDATA. - wire [7:0] txdata; // Data for 8B/10B encoding. - wire enablealign; // Allow the transceivers to serially realign to a comma character. - - assign misc_debug = { - plllock, mgt_rx_reset, mgt_tx_reset, rxbufstatus/*2*/, rxchariscomma, rxcharisk, 1'b0, //8 - rxclkcorcnt/*3*/, rxrundisp, rxdisperr, rxnotintable, txbuferr, loopback, //8 - powerdown, txchardispmode, txchardispval, txcharisk, enablealign, 3'b0, //8 - 8'b0 - }; - assign int_data = {txdata, rxdata}; - - //--------------------------------------------------------------------------- - // Instantiate the core - //--------------------------------------------------------------------------- - gige_sfp gig_eth_pcs_pma_core - ( - .mgt_rx_reset (mgt_rx_reset), - .mgt_tx_reset (mgt_tx_reset), - .userclk (userclk2), - .userclk2 (userclk2), - .dcm_locked (mmcm_locked), - .rxbufstatus (rxbufstatus), - .rxchariscomma (rxchariscomma), - .rxcharisk (rxcharisk), - .rxclkcorcnt (rxclkcorcnt), - .rxdata (rxdata), - .rxdisperr (rxdisperr), - .rxnotintable (rxnotintable), - .rxrundisp (rxrundisp), - .txbuferr (txbuferr), - .powerdown (powerdown), - .txchardispmode (txchardispmode), - .txchardispval (txchardispval), - .txcharisk (txcharisk), - .txdata (txdata), - .enablealign (enablealign), - .gmii_txd (gmii_txd), - .gmii_tx_en (gmii_tx_en), - .gmii_tx_er (gmii_tx_er), - .gmii_rxd (gmii_rxd), - .gmii_rx_dv (gmii_rx_dv), - .gmii_rx_er (gmii_rx_er), - .gmii_isolate (gmii_isolate), - .configuration_vector (configuration_vector), - .status_vector (status_vector), - .reset (reset), - .signal_detect (signal_detect) - - ); - - - //--------------------------------------------------------------------------- - // Component Instantiation for the Series-7 Transceiver wrapper - //--------------------------------------------------------------------------- - - gige_sfp_transceiver transceiver_inst ( - .encommaalign (enablealign), - .loopback (loopback), - .powerdown (powerdown), - .usrclk (userclk), - .usrclk2 (userclk2), - .independent_clock (independent_clock_bufg), - .data_valid (status_vector[1]), - .txreset (mgt_tx_reset), - .txchardispmode (txchardispmode), - .txchardispval (txchardispval), - .txcharisk (txcharisk), - .txdata (txdata), - .rxreset (mgt_rx_reset), - .rxchariscomma (rxchariscomma), - .rxcharisk (rxcharisk), - .rxclkcorcnt (rxclkcorcnt), - .rxdata (rxdata), - .rxdisperr (rxdisperr), - .rxnotintable (rxnotintable), - .rxrundisp (rxrundisp), - .rxbuferr (rxbufstatus[1]), - .txbuferr (txbuferr), - .plllkdet (plllock), - .txoutclk (txoutclk), - .rxelecidle (), - .txn (txn), - .txp (txp), - .rxn (rxn), - .rxp (rxp), - .gtrefclk (gtrefclk), - .pmareset (pma_reset), - .mmcm_locked (mmcm_locked), - .resetdone (resetdone) - ); - - - // Unused - assign rxbufstatus[0] = 1'b0; - - - - // Loopback is performed in the core itself. To alternatively use - // Transceiver loopback, please drive this port appropriately. - assign loopback = 1'b0; - - - -endmodule // gige_sfp_block - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.ucf b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.ucf deleted file mode 100755 index 91218b162..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.ucf +++ /dev/null @@ -1,201 +0,0 @@ -# This value should be modified to match your device -CONFIG PART = xc7k325t-ffg900-2; - - -#*********************************************************** -# The following constraints target the Transceiver Physical* -# Interface which is instantiated in the Example Design. * -#*********************************************************** - -#----------------------------------------------------------- -# Clock source used for the IDELAY Controller (if present) - -# and for the transceiver reset circuitry - -#----------------------------------------------------------- - -NET "independent_clock" TNM_NET = "independent_clock"; -TIMESPEC "ts_independent_clock" = PERIOD "independent_clock" 5000 ps HIGH 50 %; - - -#----------------------------------------------------------- -# PCS/PMA Clock period Constraints: please do not relax - -#----------------------------------------------------------- - -NET "gtrefclk" TNM_NET = "gtrefclk"; -TIMESPEC "ts_gtrefclk" = PERIOD "gtrefclk" 8 ns HIGH 50 %; - -NET "txoutclk" TNM_NET = "txoutclk"; -TIMESPEC "TS_txoutclk" = PERIOD "txoutclk" 16 ns HIGH 50 %; - - -#----------------------------------------------------------- -# Transceiver I/O placement: - -#----------------------------------------------------------- - -#INST "gtrefclk_p" LOC = "G7"; -#INST "gtrefclk_n" LOC = "G8"; -INST "core_wrapper?transceiver_inst?gtwizard_inst?gtwizard_i?gt0_gtwizard_i?gtxe2_i" LOC = "GTXE2_CHANNEL_X0Y10"; - -#----------------------------------------------------------- -# Setting TIG constraints for rx and tx sync sms - -#----------------------------------------------------------- - -INST "*/*/*/gt0_txresetfsm_i/mmcm_lock_int*" TNM = tx_mmcm_lock_delay_grp; -INST "*/*/*/gt0_txresetfsm_i/*mmcm_lock_reclocke*" TNM = tx_mmcm_lock_reclocked_delay_grp; -TIMESPEC TS_TX_MMCM_LOCK = FROM tx_mmcm_lock_delay_grp TO tx_mmcm_lock_reclocked_delay_grp TIG; - -INST "*/*/*/gt0_rxresetfsm_i/time_out_wait_bypass*" TNM = rx_time_out_wait_bypass_delay_grp; -INST "*/*/*/gt0_rxresetfsm_i/rx_state*" TNM = rx_state_delay_grp; -TIMESPEC TS_RX_TIME_OUT_WAIT = FROM rx_time_out_wait_bypass_delay_grp TO rx_state_delay_grp TIG; - -INST "*/*/*/gt0_txresetfsm_i/time_out_wait_bypass*" TNM = tx_time_out_wait_bypass_delay_grp; -INST "*/*/*/gt0_txresetfsm_i/tx_state*" TNM = tx_state_delay_grp; -TIMESPEC TS_TX_TIME_OUT_WAIT = FROM tx_time_out_wait_bypass_delay_grp TO tx_state_delay_grp TIG; - -INST "*/*/*/gt0_txresetfsm_i/run_phase_alignment_int*" TNM = tx_run_phase_alignment_grp; -INST "*/*/*/gt0_txresetfsm_i/sync_block_run_phase_alignment/data_sync" TNM = tx_phase_alignment_grp; -TIMESPEC TS_TX_PHASE_ALIGNMENT = FROM tx_run_phase_alignment_grp TO tx_phase_alignment_grp TIG; - -INST "*/*/*/gt0_rxresetfsm_i/run_phase_alignment_int*" TNM = rx_run_phase_alignment_grp; -INST "*/*/*/gt0_rxresetfsm_i/sync_block_run_phase_alignment/data_sync" TNM = rx_phase_alignment_grp; -TIMESPEC TS_RX_PHASE_ALIGNMENT = FROM rx_run_phase_alignment_grp TO rx_phase_alignment_grp TIG; - -INST "*/*/*/gt0_txresetfsm_i/tx_fsm_reset_done_int*" TNM = tx_fsm_reset_done_int_grp; -INST "*/*/*/gt0_txresetfsm_i/sync_block_tx_fsm_reset_done/data_sync" TNM = tx_fsm_reset_done_grp; -TIMESPEC TS_TX_FSM_RESET_DONE = FROM tx_fsm_reset_done_int_grp TO tx_fsm_reset_done_grp TIG; - -INST "*/*/*/gt0_rxresetfsm_i/rx_fsm_reset_done_int*" TNM = rx_fsm_reset_done_int_grp; -INST "*/*/*/gt0_rxresetfsm_i/sync_block_rx_fsm_reset_done/data_sync" TNM = rx_fsm_reset_done_grp; -TIMESPEC TS_RX_FSM_RESET_DONE = FROM rx_fsm_reset_done_int_grp TO rx_fsm_reset_done_grp TIG; - -INST "status_vector*" TNM = data_valid_delay_grp; -INST "*/*/sync_block_data_valid/data_sync" TNM = data_valid_reg_delay_grp; -TIMESPEC TS_TX_DATA_VALID = FROM data_valid_delay_grp TO data_valid_reg_delay_grp TIG; - -INST "*/*/*ata_valid*" TNM = data_valid_delay_grp_2; -TIMESPEC TS_TX_DATA_VALID_opt = FROM data_valid_delay_grp_2 TO data_valid_reg_delay_grp TIG; - -INST "core_wrapper/transceiver_inst/gtwizard_inst/GTWIZARD_i/gt0_GTWIZARD_i/gtxe2_i" TNM = gtwizard_grp; -INST "*/*/*/sync_block_txresetdone/data_sync" TNM = tx_resetdone_grp; -INST "*/*/*/sync_block_rxresetdone/data_sync" TNM = rx_resetdone_grp; -TIMESPEC TS_TX_RESETDONE = FROM gtwizard_grp TO tx_resetdone_grp TIG; -TIMESPEC TS_RX_RESETDONE = FROM gtwizard_grp TO rx_resetdone_grp TIG; - -#*********************************************************** -# The following constraints target the GMII implemented in * -# the Example Design. * -#*********************************************************** -# If the GMII is intended to be an internal interface, * -# the GMII signals can be connected directly to user * -# logic and all of the following constraints in this file * -# should be removed. * -# * -# If the GMII is intended to be an external interface, * -# all of the following constraints in this file should be * -# maintained. * -#*********************************************************** - -#----------------------------------------------------------- -# GMII IOSTANDARD Constraints: please select an I/O - -# Standard (LVTTL is suggested). - -#----------------------------------------------------------- - -INST "gmii_txd" IOSTANDARD = LVCMOS33; -INST "gmii_tx_en" IOSTANDARD = LVCMOS33; -INST "gmii_tx_er" IOSTANDARD = LVCMOS33; - -INST "gmii_rxd" IOSTANDARD = LVCMOS33; -INST "gmii_rx_dv" IOSTANDARD = LVCMOS33; -INST "gmii_rx_er" IOSTANDARD = LVCMOS33; - -INST "gmii_tx_clk" IOSTANDARD = LVCMOS33; -INST "gmii_rx_clk" IOSTANDARD = LVCMOS33; - - -#----------------------------------------------------------- -# Lock down the GMII Tx signals to the same bank for low - -# skew. This is an example placement only. - -#----------------------------------------------------------- - - -#----------------------------------------------------------- -# To Adjust GMII Tx Input Setup/Hold Timing - -#----------------------------------------------------------- -# These constraints will be set at a later date when device speed files have matured - -#INST "delay_gmii_tx_en" IDELAY_VALUE = 0; -#INST "delay_gmii_tx_er" IDELAY_VALUE = 0; - -#INST "gmii_data_bus[7].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[6].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[5].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[4].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[3].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[2].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[1].delay_gmii_txd" IDELAY_VALUE = 0; -#INST "gmii_data_bus[0].delay_gmii_txd" IDELAY_VALUE = 0; - - -#----------------------------------------------------------- -# To check (analyze) GMII Tx Input Setup/Hold Timing - -#----------------------------------------------------------- -INST "gmii_txd*" TNM = IN_GMII; -INST "gmii_tx_en" TNM = IN_GMII; -INST "gmii_tx_er" TNM = IN_GMII; - -# This check will be enabled at a later date when device speed files have matured - -#TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_tx_clk"; - - -#----------------------------------------------------------- -# Fast Skew maximises output setup and hold timing - -#----------------------------------------------------------- -INST "gmii_rxd" SLEW = FAST; -INST "gmii_rx_dv" SLEW = FAST; -INST "gmii_rx_er" SLEW = FAST; -INST "gmii_rx_clk" SLEW = FAST; - - -#----------------------------------------------------------- -# GMII Transmitter Constraints: place flip-flops in IOB - -#----------------------------------------------------------- -INST "gmii_txd_iff*" IOB = true; -INST "gmii_tx_en_iff" IOB = true; -INST "gmii_tx_er_iff" IOB = true; - - -#----------------------------------------------------------- -# GMII Receiver Constraints: place flip-flops in IOB - -#----------------------------------------------------------- -INST "gmii_rxd_obuf*" IOB = true; -INST "gmii_rx_dv_obuf" IOB = true; -INST "gmii_rx_er_obuf" IOB = true; - - -#----------------------------------------------------------- -# GMII Clock period Constraints: please do not relax - -#----------------------------------------------------------- - -# Describe the GMII Tx clock at the input pads -NET "gmii_tx_clk" TNM_NET = "gmii_tx_clk"; -TIMESPEC "ts_gmii_tx_clk" = PERIOD "gmii_tx_clk" 8000 ps HIGH 50 %; - - -#----------------------------------------------------------- -# GMII Tx Elastic Buffer Constraints - -#----------------------------------------------------------- - -# Identify clock domain crossing registers -INST "tx_elastic_buffer_inst/rd_addrgray*" TNM = "rd_graycode"; -INST "tx_elastic_buffer_inst/wr_addrgray*" TNM = "wr_graycode"; - -# Control Gray Code delay and skew across clock boundary -TIMESPEC "ts_tx_skew_control1" = FROM "rd_graycode" TO "FFS" 6 ns DATAPATHONLY; -TIMESPEC "ts_tx_skew_control2" = FROM "wr_graycode" TO "FFS" 6 ns DATAPATHONLY; - -# Constrain between Distributed Memory (output data) and the 1st set of flip-flops -INST "tx_elastic_buffer_inst/txd_fifo_reg1*" TNM = "TX_FIFO_SAMPLE"; -INST "tx_elastic_buffer_inst/tx_en_fifo_reg1" TNM = "TX_FIFO_SAMPLE"; -INST "tx_elastic_buffer_inst/tx_er_fifo_reg1" TNM = "TX_FIFO_SAMPLE"; -TIMESPEC "ts_tx_rams_to_ffs" = FROM "RAMS" TO "TX_FIFO_SAMPLE" 6 ns DATAPATHONLY; - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.v deleted file mode 100755 index 20411f633..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.v +++ /dev/null @@ -1,622 +0,0 @@ -//------------------------------------------------------------------------------ -// File : gige_sfp_example_design.v -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// Description: This is the top level verilog example design for the -// Ethernet SGMII core. The block level wrapper for the -// core is instantiated and the tranceiver clock circuitry is -// created. Additionally, the I/O of the GMII-style -// interface is provided with IOB flip-flops (infered) -// which enables this example design to be implemented -// using the Xilinx tools. -// -// * Please refer to the Getting Started User Guide for -// details of the example design file hierarchy. - - -`timescale 1 ps/1 ps - - -//------------------------------------------------------------------------------ -// The module declaration for the example design -//------------------------------------------------------------------------------ - -module gige_sfp_example_design - ( - - // An independent clock source used as the reference clock for an - // IDELAYCTRL (if present) and for the main GT transceiver reset logic. - // This example design assumes that this is of frequency 200MHz. - input independent_clock, - - // Tranceiver Interface - //--------------------- - - input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality. - input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality. - output txp, // Differential +ve of serial transmission from PMA to PMD. - output txn, // Differential -ve of serial transmission from PMA to PMD. - input rxp, // Differential +ve for serial reception from PMD to PMA. - input rxn, // Differential -ve for serial reception from PMD to PMA. - - // GMII Interface (client MAC <=> PCS) - //------------------------------------ - input gmii_tx_clk, // Transmit clock from client MAC. - output gmii_rx_clk, // Receive clock to client MAC. - input [7:0] gmii_txd, // Transmit data from client MAC. - input gmii_tx_en, // Transmit control signal from client MAC. - input gmii_tx_er, // Transmit control signal from client MAC. - output [7:0] gmii_rxd, // Received Data to client MAC. - output gmii_rx_dv, // Received control signal to client MAC. - output gmii_rx_er, // Received control signal to client MAC. - // Management: Alternative to MDIO Interface - //------------------------------------------ - - input [4:0] configuration_vector, // Alternative to MDIO interface. - - // General IO's - //------------- - output reg [15:0] status_vector, // Core status. - input reset, // Asynchronous reset for entire core. - input signal_detect // Input from PMD to indicate presence of optical input. - - ); - - - - //---------------------------------------------------------------------------- - // internal signals used in this top level example design. - //---------------------------------------------------------------------------- - - // clock generation signals for tranceiver - wire gtrefclk; // gtrefclk routed through an IBUFG. - wire txoutclk; // txoutclk from GT transceiver. - wire txoutclk_bufg; // txoutclk from GT transceiver routed onto global routing. - wire resetdone; // To indicate that the GT transceiver has completed its reset cycle - wire mmcm_locked; // MMCM Locked signal. - wire mmcm_reset; // MMCM reset signal. - wire clkfbout; // MMCM feedback clock - wire clkout0; // MMCM clock0 output (62.5MHz). - wire clkout1; // MMCM clock1 output (125MHz). - wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks - wire userclk2; // 125MHz clock for core reference clock. - - (* ASYNC_REG = "TRUE" *) - reg [3:0] pma_reset_pipe; // flip-flop pipeline for reset duration stretch - - wire pma_reset; // Synchronous transcevier PMA reset - - // An independent clock source used as the reference clock for an - // IDELAYCTRL (if present) and for the main GT transceiver reset logic. - wire independent_clock_bufg; - - // Signals used for an IDELAYCTRL - wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL clock domain. - reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse. - reg idelayctrl_reset; // The reset pulse for the IDELAYCTRL. - - // GMII signals - wire gmii_tx_clk_bufio; // gmii_tx_clk routed through an BUFIO. - wire gmii_tx_clk_bufr; // gmii_tx_clk_ibuf routed through a BUFR. - wire [7:0] gmii_txd_delay; // Internal gmii_txd signal after IDELAY. - wire gmii_tx_en_delay; // Internal gmii_tx_en signal after IDELAY. - wire gmii_tx_er_delay; // Internal gmii_tx_er signal after IDELAY. - wire gmii_isolate; // internal gmii_isolate signal. - reg [7:0] gmii_txd_iff; // gmii_txd signal for input IOB flip-flop. - reg gmii_tx_en_iff; // gmii_tx_en signal for input IOB flip-flop. - reg gmii_tx_er_iff; // gmii_tx_er signal for input IOB flip-flop. - reg [7:0] gmii_txd_reg; // internal gmii_txd signal. - reg gmii_tx_en_reg; // internal gmii_tx_en signal. - reg gmii_tx_er_reg; // internal gmii_tx_er signal. - wire [7:0] gmii_txd_fifo; // gmii_txd signal after Tx Elastic Buffer. - wire gmii_tx_en_fifo; // gmii_tx_en signal after Tx Elastic Buffer. - wire gmii_tx_er_fifo; // gmii_tx_er signal after Tx Elastic Buffer. - wire [7:0] gmii_rxd_int; // internal gmii_rxd signal. - wire gmii_rx_dv_int; // internal gmii_rx_dv signal. - wire gmii_rx_er_int; // internal gmii_rx_er signal. - wire gmii_rx_clk_obuf; // gmii_rx_clk registered in IOBs prior to an OBUF. - reg [7:0] gmii_rxd_obuf; // gmii_rxd registered in IOBs prior to an OBUF. - reg gmii_rx_dv_obuf; // gmii_rx_dv registered in IOBs prior to an OBUF. - reg gmii_rx_er_obuf; // gmii_rx_er registered in IOBs prior to an OBUF. - - // Extra registers to ease IOB placement - wire [15:0] status_vector_int; - - - - //--------------------------------------------------------------------------- - // An independent clock source used as the reference clock for an - // IDELAYCTRL (if present) and for the main GT transceiver reset logic. - //--------------------------------------------------------------------------- - - // Route independent_clock input through a BUFG - BUFG bufg_independent_clock ( - .I (independent_clock), - .O (independent_clock_bufg) - ); - - - //--------------------------------------------------------------------------- - // Instantiate an IDELAYCTRL and its reset circuitry - //--------------------------------------------------------------------------- - - // Instantiate the IDELAY Controller. - IDELAYCTRL dlyctrl - ( - .RDY (), - .REFCLK (independent_clock_bufg), - .RST (idelayctrl_reset) - ); - - - // Create a synchronous reset in the IDELAYCTRL clock domain. - gige_sfp_reset_sync idelayctrl_reset_gen ( - .clk (independent_clock_bufg), - .reset_in (reset), - .reset_out (idelayctrl_reset_sync) - ); - - - // Reset circuitry for the IDELAYCTRL reset. - - // The IDELAYCTRL must experience a pulse which is at least 50 ns in - // duration. This is ten clock cycles of the 200MHz independent_clock. - // Here we drive the reset pulse for 12 clock cycles. - always @(posedge independent_clock_bufg) - begin - if (idelayctrl_reset_sync) begin - idelay_reset_cnt <= 4'b0000; - idelayctrl_reset <= 1'b1; - end - - else begin - - case (idelay_reset_cnt) - 4'b0000 : idelay_reset_cnt <= 4'b0001; - 4'b0001 : idelay_reset_cnt <= 4'b0010; - 4'b0010 : idelay_reset_cnt <= 4'b0011; - 4'b0011 : idelay_reset_cnt <= 4'b0100; - 4'b0100 : idelay_reset_cnt <= 4'b0101; - 4'b0101 : idelay_reset_cnt <= 4'b0110; - 4'b0110 : idelay_reset_cnt <= 4'b0111; - 4'b0111 : idelay_reset_cnt <= 4'b1000; - 4'b1000 : idelay_reset_cnt <= 4'b1001; - 4'b1001 : idelay_reset_cnt <= 4'b1010; - 4'b1010 : idelay_reset_cnt <= 4'b1011; - 4'b1011 : idelay_reset_cnt <= 4'b1100; - default : idelay_reset_cnt <= 4'b1100; - endcase - - if (idelay_reset_cnt === 4'b1100) begin - idelayctrl_reset <= 1'b0; - end - - else begin - idelayctrl_reset <= 1'b1; - end - - end - end - - - //--------------------------------------------------------------------------- - // Transceiver Clock Management - //--------------------------------------------------------------------------- - - // Clock circuitry for the Transceiver uses a differential input clock. - // gtrefclk is routed to the tranceiver. - IBUFDS_GTE2 ibufds_gtrefclk ( - .I (gtrefclk_p), - .IB (gtrefclk_n), - .CEB (1'b0), - .O (gtrefclk), - .ODIV2 () - ); - - - // Route txoutclk input through a BUFG - BUFG bufg_txoutclk ( - .I (txoutclk), - .O (txoutclk_bufg) - ); - - - // The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is - // routed to an MMCM module where it is used to create phase and frequency - // related 62.5MHz and 125MHz clock sources - MMCME2_ADV # ( - .BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (16.000), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (8.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.5), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (16), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.5), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (16.0), - .REF_JITTER1 (0.010) - ) mmcm_adv_inst ( - // Output clocks - .CLKFBOUT (clkfbout), - .CLKFBOUTB (), - .CLKOUT0 (clkout0), - .CLKOUT0B (), - .CLKOUT1 (clkout1), - .CLKOUT1B (), - .CLKOUT2 (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - // Input clock control - .CLKFBIN (clkfbout), - .CLKIN1 (txoutclk_bufg), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (), - .DRDY (), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - // Other control and status signals - .LOCKED (mmcm_locked), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_reset) - ); - - assign mmcm_reset = reset||!resetdone; - - // This 62.5MHz clock is placed onto global clock routing and is then used - // for tranceiver TXUSRCLK/RXUSRCLK. - BUFG bufg_userclk ( - .I (clkout1), - .O (userclk) - ); - - - // This 125MHz clock is placed onto global clock routing and is then used - // to clock all Ethernet core logic. - BUFG bufg_userclk2 ( - .I (clkout0), - .O (userclk2) - ); - - - //--------------------------------------------------------------------------- - // Transceiver PMA reset circuitry - //--------------------------------------------------------------------------- - - always@(posedge independent_clock_bufg or posedge reset) - if (reset == 1'b1) - pma_reset_pipe <= 4'b1111; - else - pma_reset_pipe <= {pma_reset_pipe[2:0], reset}; - - assign pma_reset = pma_reset_pipe[3]; - - - //---------------------------------------------------------------------------- - // Instantiate the Core Block (core wrapper). - //---------------------------------------------------------------------------- - gige_sfp_block core_wrapper - ( - .gtrefclk (gtrefclk), - .txp (txp), - .txn (txn), - .rxp (rxp), - .rxn (rxn), - .txoutclk (txoutclk), - .resetdone (resetdone), - .mmcm_locked (mmcm_locked), - .userclk (userclk), - .userclk2 (userclk2), - .independent_clock_bufg(independent_clock_bufg), - .pma_reset (pma_reset), - .gmii_txd (gmii_txd_fifo), - .gmii_tx_en (gmii_tx_en_fifo), - .gmii_tx_er (gmii_tx_er_fifo), - .gmii_rxd (gmii_rxd_int), - .gmii_rx_dv (gmii_rx_dv_int), - .gmii_rx_er (gmii_rx_er_int), - .gmii_isolate (gmii_isolate), - .configuration_vector (configuration_vector), - .status_vector (status_vector_int), - .reset (reset), - .signal_detect (signal_detect) - ); - - - - //--------------------------------------------------------------------------- - // GMII transmitter clock logic - //--------------------------------------------------------------------------- - - // Route gmii_tx_clk from PAD through a BUFIO Buffer - BUFIO receive_gmii_tx_clk ( - .I (gmii_tx_clk), - .O (gmii_tx_clk_bufio) - ); - - - // Route gmii_tx_clk through a BUFR onto regional clock routing - BUFR drive_tx_clk ( - .I (gmii_tx_clk), - .CE (1'b1), - .CLR (1'b0), - .O (gmii_tx_clk_bufr) - ); - - - //--------------------------------------------------------------------------- - // GMII transmitter data logic - //--------------------------------------------------------------------------- - - // An IOBDELAY is used with Series-7 devices to meet the GMII input - // setup and hold specifications. The data is delayed so to compensate for - // the clock routing delay so that the GMII input data will be correctly - // sampled at the IOB flip-flops - - // Please modify the value of the IOBDELAY according to your design. - // The value in this file will be overridden with the value in the - // UCF. For more information, please refer to the User Guide. - - // The tap delay values can also be adjusted to compensate for PCB routing - // deskew. - - // IODELAY for GMII_TXD - genvar i; - generate for (i=0; i<8; i=i+1) - begin : gmii_data_bus - - IODELAYE1 # ( - .IDELAY_TYPE ("FIXED"), - .IDELAY_VALUE (0) - - ) delay_gmii_txd ( - .IDATAIN (gmii_txd[i]), - .ODATAIN (1'b0), - .DATAOUT (gmii_txd_delay[i]), - .DATAIN (1'b0), - .CNTVALUEIN (5'b0), - .CNTVALUEOUT (), - .CLKIN (1'b0), - .CINVCTRL (1'b0), - .T (1'b1), - .C (1'b0), - .CE (1'b0), - .INC (1'b0), - .RST (1'b0) - ); - - end - endgenerate - - - // IODELAY for GMII_TX_EN - IODELAYE1 # ( - .IDELAY_TYPE ("FIXED"), - .IDELAY_VALUE (0) - - ) delay_gmii_tx_en ( - .IDATAIN (gmii_tx_en), - .ODATAIN (1'b0), - .DATAOUT (gmii_tx_en_delay), - .DATAIN (1'b0), - .CNTVALUEIN (5'b0), - .CNTVALUEOUT (), - .CLKIN (1'b0), - .CINVCTRL (1'b0), - .T (1'b1), - .C (1'b0), - .CE (1'b0), - .INC (1'b0), - .RST (1'b0) - ); - - - // IODELAY for GMII_TX_ER - IODELAYE1 # ( - .IDELAY_TYPE ("FIXED"), - .IDELAY_VALUE (0) - - ) delay_gmii_tx_er ( - .IDATAIN (gmii_tx_er), - .ODATAIN (1'b0), - .DATAOUT (gmii_tx_er_delay), - .DATAIN (1'b0), - .CNTVALUEIN (5'b0), - .CNTVALUEOUT (), - .CLKIN (1'b0), - .CINVCTRL (1'b0), - .T (1'b1), - .C (1'b0), - .CE (1'b0), - .INC (1'b0), - .RST (1'b0) - ); - - - // Drive input GMII through IOB input flip-flops (inferred). - always @ (posedge gmii_tx_clk_bufio) - begin - gmii_txd_iff <= gmii_txd_delay; - gmii_tx_en_iff <= gmii_tx_en_delay; - gmii_tx_er_iff <= gmii_tx_er_delay; - end - - - - // Reclock onto regional clock routing - always @ (posedge gmii_tx_clk_bufr) - begin - gmii_txd_reg <= gmii_txd_iff; - gmii_tx_en_reg <= gmii_tx_en_iff; - gmii_tx_er_reg <= gmii_tx_er_iff; - end - - - // Component Instantiation for the Transmitter Elastic Buffer - gige_sfp_tx_elastic_buffer tx_elastic_buffer_inst - ( - .reset (reset), - .gmii_tx_clk_wr (gmii_tx_clk_bufr), - .gmii_txd_wr (gmii_txd_reg), - .gmii_tx_en_wr (gmii_tx_en_reg), - .gmii_tx_er_wr (gmii_tx_er_reg), - .gmii_tx_clk_rd (userclk2), - .gmii_txd_rd (gmii_txd_fifo), - .gmii_tx_en_rd (gmii_tx_en_fifo), - .gmii_tx_er_rd (gmii_tx_er_fifo) - ); - - - - //--------------------------------------------------------------------------- - // GMII receiver clock logic - //--------------------------------------------------------------------------- - - // This instantiates a DDR output register. This is a nice way to - // drive the GMII output clock since the clock-to-PAD delay will the - // same as that of data driven from an IOB Ouput flip-flop. This is - // set to produce an inverted clock w.r.t. userclk2 so that clock - // rising edge appears in the centre of GMII data. - ODDR rx_clk_ddr_iob ( - .Q (gmii_rx_clk_obuf), - .C (userclk2), - .D1 (1'b0), - .D2 (1'b1), - .CE (1'b1), - .R (1'b0), - .S (1'b0) - ); - - - // Finally the clock is driven onto the PAD from an Output Buffer. - OBUFT drive_gmii_gtx_clk ( - .I (gmii_rx_clk_obuf), - .O (gmii_rx_clk), - .T (gmii_isolate) - ); - - - - //--------------------------------------------------------------------------- - // GMII receiver data logic - //--------------------------------------------------------------------------- - - - // Drive Rx GMII signals through IOB output flip-flops (inferred). - always @ (posedge userclk2) - begin - gmii_rxd_obuf <= gmii_rxd_int; - gmii_rx_dv_obuf <= gmii_rx_dv_int; - gmii_rx_er_obuf <= gmii_rx_er_int; - end - - - // drive GMII Rx signals through output PADS. - OBUFT rx_data_valid ( - .I (gmii_rx_dv_obuf), - .O (gmii_rx_dv), - .T (gmii_isolate) - ); - - OBUFT rx_data_error ( - .I (gmii_rx_er_obuf), - .O (gmii_rx_er), - .T (gmii_isolate) - ); - - genvar j; - generate for (j=0; j<8; j=j+1) - begin : rx_data_bus - - OBUFT rx_data_bits ( - .I (gmii_rxd_obuf[j]), - .O (gmii_rxd[j]), - .T (gmii_isolate)); - - end - endgenerate - - - - //--------------------------------------------------------------------------- - // Extra registers to ease IOB placement - //--------------------------------------------------------------------------- - always @ (posedge userclk2) - begin - status_vector <= status_vector_int; - end - - -endmodule // gige_sfp_example_design diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.xdc b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.xdc deleted file mode 100755 index be4d8a6db..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_example_design.xdc +++ /dev/null @@ -1,170 +0,0 @@ -# This value should be modified to match your device -#CONFIG PART = xc7k70t-fbg676-1; - - -#*********************************************************** -# The following constraints target the Transceiver Physical* -# Interface which is instantiated in the Example Design. * -#*********************************************************** - -#----------------------------------------------------------- -# Clock source used for the IDELAY Controller (if present) - -# and for the transceiver reset circuitry - -#----------------------------------------------------------- - - -create_clock -name independent_clock -period 5.000 [get_ports independent_clock] -set_propagated_clock independent_clock - -#----------------------------------------------------------- -# PCS/PMA Clock period Constraints: please do not relax - -#----------------------------------------------------------- - -create_clock -name gtrefclk -period 8.000 [get_pins ibufds_gtrefclk/O] -set_propagated_clock gtrefclk - -create_clock -name TXOUTCLK_OUT -period 16.000 [get_pins core_wrapper/transceiver_inst/gtwizard_inst/gtwizard_i/gt0_gtwizard_i/gtxe2_i/TXOUTCLK] -set_propagated_clock TXOUTCLK_OUT - - -set_false_path -from [get_clocks -include_generated_clocks independent_clock] -to [get_clocks -include_generated_clocks {gtrefclk TXOUTCLK_OUT}] -set_false_path -from [get_clocks -include_generated_clocks gtrefclk] -to [get_clocks -include_generated_clocks {independent_clock TXOUTCLK_OUT}] -set_false_path -from [get_clocks -include_generated_clocks TXOUTCLK_OUT] -to [get_clocks -include_generated_clocks {independent_clock gtrefclk}] - -#----------------------------------------------------------- -# Transceiver I/O placement: - -#----------------------------------------------------------- - -#set_property LOC H6 [get_ports gtrefclk_p] -#set_property LOC H5 [get_ports gtrefclk_n] -set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells core_wrapper/transceiver_inst/gtwizard_inst/gtwizard_i/gt0_gtwizard_i/gtxe2_i] - - -#*********************************************************** -# The following constraints target the GMII implemented in * -# the Example Design. * -#*********************************************************** -# If the GMII is intended to be an internal interface, * -# the GMII signals can be connected directly to user * -# logic and all of the following constraints in this file * -# should be removed. * -# * -# If the GMII is intended to be an external interface, * -# all of the following constraints in this file should be * -# maintained. * -#*********************************************************** - -#----------------------------------------------------------- -# GMII IOSTANDARD Constraints: please select an I/O - -# Standard (LVTTL is suggested). - -#----------------------------------------------------------- - -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en] -set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er] - -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv] -set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er] - -set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk] -set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk] - - -#----------------------------------------------------------- -# Lock down the GMII Tx signals to the same bank for low - -# skew. This is an example placement only. - -#----------------------------------------------------------- - - -#----------------------------------------------------------- -# To Adjust GMII Tx Input Setup/Hold Timing - -#----------------------------------------------------------- -# These constraints will be set at a later date when device speed files have matured - -#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en] -#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er] - -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}] -#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}] - - - -#----------------------------------------------------------- -# To check (analyze) GMII Tx Input Setup/Hold Timing - -#----------------------------------------------------------- - -create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk] -set_propagated_clock gmii_tx_clk - -# This check will be enabled at a later date when device speed files have matured -#set_input_delay -clock gmii_tx_clk -max 6.000 [get_ports {gmii_tx_en gmii_tx_er {gmii_txd[*]}}] -#set_input_delay -clock gmii_tx_clk -min 0.000 [get_ports {gmii_tx_en gmii_tx_er {gmii_txd[*]}}] - -set_false_path -from [get_clocks -include_generated_clocks independent_clock] -to [get_clocks -include_generated_clocks gmii_tx_clk] -set_false_path -from [get_clocks -include_generated_clocks gtrefclk] -to [get_clocks -include_generated_clocks gmii_tx_clk] -set_false_path -from [get_clocks -include_generated_clocks TXOUTCLK_OUT] -to [get_clocks -include_generated_clocks gmii_tx_clk] -set_false_path -from [get_clocks -include_generated_clocks gmii_tx_clk] -to [get_clocks -include_generated_clocks {independent_clock gtrefclk TXOUTCLK_OUT}] - - - -#----------------------------------------------------------- -# Fast Skew maximises output setup and hold timing - -#----------------------------------------------------------- -set_property SLEW FAST [get_ports {gmii_rxd[*]}] -set_property SLEW FAST [get_ports gmii_rx_dv] -set_property SLEW FAST [get_ports gmii_rx_er] -set_property SLEW FAST [get_ports gmii_rx_clk] - - -#----------------------------------------------------------- -# GMII Transmitter Constraints: place flip-flops in IOB - -#----------------------------------------------------------- -set_property IOB TRUE [get_cells gmii_txd*] -set_property IOB TRUE [get_cells gmii_tx_en*] -set_property IOB TRUE [get_cells gmii_tx_er*] - -#----------------------------------------------------------- -# GMII Receiver Constraints: place flip-flops in IOB - -#----------------------------------------------------------- -set_property IOB TRUE [get_cells gmii_rxd_obuf_reg[*]] -set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg] -set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg] - - - -#----------------------------------------------------------- -# GMII Tx Elastic Buffer Constraints - -#----------------------------------------------------------- - -# Control Gray Code delay and skew across clock boundary -set_max_delay 6.000 -from [get_cells -hier -filter {name =~ tx_elastic_buffer_inst/rd_addrgray*}] -to [all_registers -edge_triggered] - -set_max_delay 6.000 -from [get_cells -hier -filter {name =~ tx_elastic_buffer_inst/wr_addrgray*}] -to [all_registers -edge_triggered] - -# Constrain between Distributed Memory (output data) and the 1st set of flip-flops -set_max_delay 6.000 -from [all_rams] -to [get_cells -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1_reg}] -set_max_delay 6.000 -from [all_rams] -to [get_cells -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1_reg}] -set_max_delay 6.000 -from [all_rams] -to [get_cells -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*}] - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_mod.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_mod.v deleted file mode 100755 index 7fc8872d6..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_mod.v +++ /dev/null @@ -1,110 +0,0 @@ -//------------------------------------------------------------------------------ -// File : gige_sfp_mod.v -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// (c) Copyright 2002-2008 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// Description: This package holds the top level component declaration -// for the Ethernet 1000BASE-X PCS/PMA core. - - - -module gige_sfp - ( - // Core <=> tranceiver Interface - //------------------------------ - - output mgt_rx_reset, // tranceiver connection: reset for the receiver half of the tranceiver - output mgt_tx_reset, // tranceiver connection: reset for the transmitter half of the tranceiver - input userclk, // Routed to TXUSERCLK and RXUSERCLK of Transceiver. - input userclk2, // Routed to TXUSERCLK2 and RXUSERCLK2 of Transceiver. - input dcm_locked, // LOCKED signal from DCM. - - input [1:0] rxbufstatus, // tranceiver connection: Elastic Buffer Status. - input rxchariscomma, // tranceiver connection: Comma detected in RXDATA. - input rxcharisk, // tranceiver connection: K character received (or extra data bit) in RXDATA. - input [2:0] rxclkcorcnt, // tranceiver connection: Indicates clock correction. - input [7:0] rxdata, // tranceiver connection: Data after 8B/10B decoding. - input rxdisperr, // tranceiver connection: Disparity-error in RXDATA. - input rxnotintable, // tranceiver connection: Non-existent 8B/10 code indicated. - input rxrundisp, // tranceiver connection: Running Disparity of RXDATA (or extra data bit). - input txbuferr, // tranceiver connection: TX Buffer error (overflow or underflow). - - output powerdown, // tranceiver connection: Powerdown the tranceiver - output txchardispmode, // tranceiver connection: Set running disparity for current byte. - output txchardispval, // tranceiver connection: Set running disparity value. - output txcharisk, // tranceiver connection: K character transmitted in TXDATA. - output [7:0] txdata, // tranceiver connection: Data for 8B/10B encoding. - output enablealign, // Allow the transceivers to serially realign to a comma character. - - // GMII Interface (MAC <=> PCS) - //----------------------------- - - input [7:0] gmii_txd, // Transmit data from client MAC. - input gmii_tx_en, // Transmit control signal from client MAC. - input gmii_tx_er, // Transmit control signal from client MAC. - output [7:0] gmii_rxd, // Received Data to client MAC. - output gmii_rx_dv, // Received control signal to client MAC. - output gmii_rx_er, // Received control signal to client MAC. - output gmii_isolate, // Tristate control to electrically isolate GMII. - - // Alternative to MDIO Interface - //------------------------------ - - input [4:0] configuration_vector, // Alternative to MDIO interface. - - // General IO's - //------------- - output [15:0] status_vector, // Core status. - input reset, // Asynchronous reset for entire core. - input signal_detect // Input from PMD to indicate presence of optical input. - ); - -endmodule // gige_sfp - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_reset_sync.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_reset_sync.v deleted file mode 100755 index bbc5210e8..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_reset_sync.v +++ /dev/null @@ -1,101 +0,0 @@ -//------------------------------------------------------------------------------ -// File : gige_sfp_reset_sync.v -// Author : Xilinx, Inc. -//------------------------------------------------------------------------------ -// Description: Both flip-flops have the same asynchronous reset signal. -// Together the flops create a minimum of a 1 clock period -// duration pulse which is used for synchronous reset. -// -// The flops are placed, using RLOCs, into the same slice. -//------------------------------------------------------------------------------ -// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ - -`timescale 1ps/1ps - -module gige_sfp_reset_sync #( - parameter INITIALISE = 2'b11 -) -( - input reset_in, - input clk, - output reset_out -); - - - (* shreg_extract = "no", ASYNC_REG = "TRUE" *) - wire reset_stage1; - - (* shreg_extract = "no", ASYNC_REG = "TRUE" *) - wire reset_stage2; - - FDP #( - .INIT (INITIALISE[0]) - ) reset_sync1 ( - .C (clk), - .PRE(reset_in), - .D (1'b0), - .Q (reset_stage1) - ); - - FDP #( - .INIT (INITIALISE[1]) - ) reset_sync2 ( - .C (clk), - .PRE(reset_in), - .D (reset_stage1), - .Q (reset_stage2) - ); - - -assign reset_out = reset_stage2; - - - -endmodule diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_sync_block.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_sync_block.v deleted file mode 100755 index 9d587a7e4..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_sync_block.v +++ /dev/null @@ -1,101 +0,0 @@ -//------------------------------------------------------------------------------ -// File : gige_sfp_sync_block.vhd -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// Description: Used on signals crossing from one clock domain to -// another, this is a flip-flop pair, with both flops -// placed together with RLOCs into the same slice. Thus -// the routing delay between the two is minimum to safe- -// guard against metastability issues. -//------------------------------------------------------------------------------ -// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ - -`timescale 1ps / 1ps - -module gige_sfp_sync_block #( - parameter INITIALISE = 2'b00 -) -( - input clk, // clock to be sync'ed to - input data_in, // Data to be 'synced' - output data_out // synced data -); - - // Internal Signals - wire data_sync1; - wire data_sync2; - - - (* shreg_extract = "no", ASYNC_REG = "TRUE", RLOC = "X0Y0" *) - FD #( - .INIT (INITIALISE[0]) - ) data_sync ( - .C (clk), - .D (data_in), - .Q (data_sync1) - ); - - - (* shreg_extract = "no", RLOC = "X0Y0" *) - FD #( - .INIT (INITIALISE[1]) - ) data_sync_reg ( - .C (clk), - .D (data_sync1), - .Q (data_sync2) - ); - - - assign data_out = data_sync2; - - -endmodule - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_tx_elastic_buffer.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_tx_elastic_buffer.v deleted file mode 100755 index 13b74dd4d..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/gige_sfp_tx_elastic_buffer.v +++ /dev/null @@ -1,617 +0,0 @@ -//------------------------------------------------------------------------------ -// File : gige_sfp_tx_elastic_buffer.v -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// (c) Copyright 2002-2008 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// Description: This is the Transmitter Elastic Buffer for the design -// example of the Ethernet 1000BASE-X PCS/PMA or SGMII -// core. -// -// The FIFO is created from Distributed Memory and is of -// depth 16 words. -// -// When the write clock is a few parts per million faster -// than the read clock, the occupancy of the FIFO will -// increase and Idles should be removed. A MAC transmitter -// should always insert a minimum of 12 Idles in a single -// Inter-Packet Gap. The IEEE802.3 specification allows -// for up to 4 Idles to be lost within the system (eg. due -// to clock correction) so that a minimum of 8 Idles should -// always be presented to a MAC receiver. Consequently the -// logic in this example design will only remove a single -// Idle per minimum Inter-Packet Gap. This leaves clock -// correction potential for other components in the overall -// system. -// -// When the read clock is a few parts per million faster -// than the write clock, the occupancy of the FIFO will -// decrease and Idles should be inserted. The logic in -// this example design will always insert as many idles as -// necessary in every Inter-frame Gap period to restore the -// FIFO occupancy. -// -// Because the Idle insertion logic is stronger than the -// Idle removal logic, the bias in this example design is -// to keep the occupancy of the FIFO low. This allows more -// overhead for the FIFO to fill up during heavy bursts of -// traffic. - - -`timescale 1 ps/1 ps - - -//------------------------------------------------------------------------------ -// Module declaration. -//------------------------------------------------------------------------------ - -module gige_sfp_tx_elastic_buffer - ( - - input reset, // Asynchronous Reset - - // Signals received from the input gmii_tx_clk_wr domain. - //------------------------------------------------------ - - input gmii_tx_clk_wr, // Write clock domain. - input [7:0] gmii_txd_wr, // gmii_txd synchronous to gmii_tx_clk_wr. - input gmii_tx_en_wr, // gmii_tx_en synchronous to gmii_tx_clk_wr. - input gmii_tx_er_wr, // gmii_tx_er synchronous to gmii_tx_clk_wr. - - // Signals transfered onto the new gmii_tx_clk_rd domain. - //------------------------------------------------------- - - input gmii_tx_clk_rd, // Read clock domain. - output [7:0] gmii_txd_rd, // gmii_txd synchronous to gmii_tx_clk_rd. - output gmii_tx_en_rd, // gmii_tx_en synchronous to gmii_tx_clk_rd. - output gmii_tx_er_rd // gmii_tx_er synchronous to gmii_tx_clk_rd. - ); - - - - //---------------------------------------------------------------------------- - // Signal declarations - //---------------------------------------------------------------------------- - - wire [3:0] lower_threshold; // FIFO occupancy should be kept at 6 or above. - wire [3:0] upper_threshold; // FIFO occupancy should be kept at 9 or below. - - - // create a synchronous reset in the write clock domain - wire reset_wr; - - // create a synchronous reset in the read clock domain - wire reset_rd; - - reg [7:0] gmii_txd_wr_reg; // Registered version of gmii_txd_wr. - reg gmii_tx_en_wr_reg; // Registered version of gmii_tx_en_wr. - reg gmii_tx_er_wr_reg; // Registered version of gmii_tx_er_wr. - reg wr_enable; // write enable for FIFO. - reg rd_enable; // read enable for FIFO. - wire nearly_full; // FIFO is getting full. - wire nearly_empty; // FIFO is running empty. - reg [3:0] wr_addr_plus2; // Always ahead of the FIFO write address by 2. - reg [3:0] wr_addr_plus1; // Always ahead of the FIFO write address by 1. - reg [3:0] wr_addr; // FIFO write address. - reg [3:0] wr_addrgray; // FIFO write address converted to Gray Code. - wire [3:0] wag_readsync; // wr_addrgray Registered on read clock for the 2nd time. - wire [3:0] wr_addrbin; // wag_readsync converted back to binary - on READ clock. - reg [3:0] rd_addr_plus2; // Always ahead of the FIFO read address by 2. - reg [3:0] rd_addr_plus1; // Always ahead of the FIFO read address by 1. - reg [3:0] rd_addr; // FIFO read address. - reg [3:0] rd_addrgray; // FIFO read address converted to Gray Code. - wire [3:0] rag_writesync; // rd_addrgray Registered on write clock for the 2nd time. - wire [3:0] rd_addrbin; // rag_writesync converted back to binary - on WRITE clock. - wire tx_en_fifo; // gmii_tx_en_wr read out of FIFO. - wire tx_er_fifo; // gmii_tx_er_wr read out of FIFO. - wire [7:0] txd_fifo; // gmii_txd_wr read out of FIFO. - reg tx_en_fifo_reg1; // Registered version of tx_en_fifo. - reg tx_er_fifo_reg1; // Registered version of tx_er_fifo. - reg [7:0] txd_fifo_reg1; // Registered version of txd_fifo. - reg tx_en_fifo_reg2; // Registered version of tx_en_fifo_reg1. - reg tx_er_fifo_reg2; // Registered version of tx_er_fifo_reg1. - reg [7:0] txd_fifo_reg2; // Registered version of txd_fifo_reg1. - reg [3:0] wr_occupancy; // The occupancy of the FIFO in write clock domain. - reg [3:0] rd_occupancy; // The occupancy of the FIFO in read clock domain. - wire wr_idle; // Detect an Idle written into the FIFO in the write clock domain. - wire rd_idle; // Detect an Idle read out of the FIFO in the read clock domain. - reg [3:0] ipg_count; // Count the Inter-Packet Gap period. - reg allow_idle_removal; // Allow the removal of a single Idle. - - - // Assign the Upper and Lower thresholds for the FIFO. These are used - // to determine the nearly_full and nearly_empty signals. - - // FIFO occupancy should be kept at 6 or above. - assign lower_threshold = 4'b0110; - - // FIFO occupancy should be kept at 9 or below. - assign upper_threshold = 4'b1001; - - - -//------------------------------------------------------------------------------ -// FIFO write logic (Idles are removed as necessary). -//------------------------------------------------------------------------------ - - - - // Create a synchronous reset in the write clock domain. - gige_sfp_reset_sync gen_wr_reset ( - .clk (gmii_tx_clk_wr), - .reset_in (reset), - .reset_out (reset_wr) - ); - - - - // Reclock the GMII Tx inputs. - always @(posedge gmii_tx_clk_wr) - begin : reclock_gmii - if (reset_wr == 1'b1) begin - gmii_txd_wr_reg <= 8'b0; - gmii_tx_en_wr_reg <= 1'b0; - gmii_tx_er_wr_reg <= 1'b0; - end - - else begin - gmii_txd_wr_reg <= gmii_txd_wr; - gmii_tx_en_wr_reg <= gmii_tx_en_wr; - gmii_tx_er_wr_reg <= gmii_tx_er_wr; - end - end // reclock_gmii - - - - // Detect Idles (Normal inter-frame encodings as desribed in - // IEEE802.3 table 35-2) - assign wr_idle = ( - // 1st type of Idle. - (gmii_tx_en_wr == 1'b0 && gmii_tx_er_wr == 1'b0) - || - // 2nd type of Idle. - (gmii_tx_en_wr == 1'b0 && gmii_tx_er_wr == 1'b1 - && gmii_txd_wr == 8'b0) - - ) ? 1'b1 : 1'b0; - - - - // Create a counter to count from 0 to 8. When the counter reaches 8 - // it is reset to 0 and a pulse is generated (allow_idle_removal). - - // allow_idle_removal is therefore high for a single clock cycle once - // every 9 clock periods. This is used to ensure that the Idle - // removal logic will only ever remove a single idle from a minimum - // transmitter interframe gap (12 idles). This leaves clock - // correction potential for other components in the overall system - // (the IEEE802.3 spec allows for a total of 4 idles to be lost - // between a MAC transmitter and a MAC receiver). - always @(posedge gmii_tx_clk_wr) - begin : idle_removal_control - if (reset_wr == 1'b1) begin - ipg_count <= 4'b0; - allow_idle_removal <= 1'b0; - end - else begin - if (ipg_count[3] == 1'b1) begin - ipg_count <= 4'b0; - allow_idle_removal <= 1'b1; - end - else begin - ipg_count <= ipg_count + 4'b1; - allow_idle_removal <= 1'b0; - end - end - end // idle_removal_control - - - - // Create the FIFO write enable. This is not asserted when Idles are - // to be removed. - always @(posedge gmii_tx_clk_wr) - begin : gen_wr_enable - if (reset_wr == 1'b1) - wr_enable <= 1'b0; - else begin - if (wr_idle == 1'b1 && allow_idle_removal == 1'b1 - && nearly_full == 1'b1) // remove 1 Idle. - wr_enable <= 1'b0; - else - wr_enable <= 1'b1; - end - end // gen_wr_enable - - - - // Create the FIFO write address pointer. Note that wr_addr_plus2 - // will be converted to gray code and passed across the async clock - // boundary. - always @(posedge gmii_tx_clk_wr) - begin : gen_wr_addr - if (reset_wr == 1'b1) begin - wr_addr_plus2 <= 4'b0010; - wr_addr_plus1 <= 4'b0001; - wr_addr <= 4'b0000; - end - - else if (wr_enable == 1'b1) begin - wr_addr_plus2 <= wr_addr_plus2 + 4'b0001; - wr_addr_plus1 <= wr_addr_plus2; - wr_addr <= wr_addr_plus1; - end - end // gen_wr_addr - - - -//------------------------------------------------------------------------------ -// Build FIFO out of distributed RAM. -//------------------------------------------------------------------------------ - - - - genvar i; - generate for (i=0; i<8; i=i+1) - begin : gen_txd_fifo_bus - - RAM16X1D gen_txd_fifo_bit - ( - .D(gmii_txd_wr_reg[i]), - .WE(wr_enable), - .WCLK(gmii_tx_clk_wr), - .A0(wr_addr[0]), - .A1(wr_addr[1]), - .A2(wr_addr[2]), - .A3(wr_addr[3]), - .DPRA0(rd_addr[0]), - .DPRA1(rd_addr[1]), - .DPRA2(rd_addr[2]), - .DPRA3(rd_addr[3]), - - .SPO(), - .DPO(txd_fifo[i]) - ); - - end - endgenerate - - - - RAM16X1D gen_tx_en_fifo - ( - .D(gmii_tx_en_wr_reg), - .WE(wr_enable), - .WCLK(gmii_tx_clk_wr), - .A0(wr_addr[0]), - .A1(wr_addr[1]), - .A2(wr_addr[2]), - .A3(wr_addr[3]), - .DPRA0(rd_addr[0]), - .DPRA1(rd_addr[1]), - .DPRA2(rd_addr[2]), - .DPRA3(rd_addr[3]), - - .SPO(), - .DPO(tx_en_fifo) - ); - - - - RAM16X1D gen_tx_er_fifo - ( - .D(gmii_tx_er_wr_reg), - .WE(wr_enable), - .WCLK(gmii_tx_clk_wr), - .A0(wr_addr[0]), - .A1(wr_addr[1]), - .A2(wr_addr[2]), - .A3(wr_addr[3]), - .DPRA0(rd_addr[0]), - .DPRA1(rd_addr[1]), - .DPRA2(rd_addr[2]), - .DPRA3(rd_addr[3]), - - .SPO(), - .DPO(tx_er_fifo) - ); - - - -//------------------------------------------------------------------------------ -// FIFO read logic (Idles are repeated as necessary). -//------------------------------------------------------------------------------ - - - - // Create a synchronous reset in the read clock domain. - gige_sfp_reset_sync gen_rd_reset ( - .clk (gmii_tx_clk_rd), - .reset_in (reset), - .reset_out (reset_rd) - ); - - - - // Register the FIFO outputs. - always @(posedge gmii_tx_clk_rd) - begin : drive_new_gmii - if (reset_rd == 1'b1) begin - txd_fifo_reg1 <= 8'b0; - tx_en_fifo_reg1 <= 1'b0; - tx_er_fifo_reg1 <= 1'b0; - txd_fifo_reg2 <= 8'b0; - tx_en_fifo_reg2 <= 1'b0; - tx_er_fifo_reg2 <= 1'b0; - end - - else begin - txd_fifo_reg1 <= txd_fifo; - tx_en_fifo_reg1 <= tx_en_fifo; - tx_er_fifo_reg1 <= tx_er_fifo; - txd_fifo_reg2 <= txd_fifo_reg1; - tx_en_fifo_reg2 <= tx_en_fifo_reg1; - tx_er_fifo_reg2 <= tx_er_fifo_reg1; - end - end // drive_new_gmii - - - - // Route GMII outputs, now synchronous to gmii_tx_clk_rd. - assign gmii_txd_rd = txd_fifo_reg2; - assign gmii_tx_en_rd = tx_en_fifo_reg2; - assign gmii_tx_er_rd = tx_er_fifo_reg2; - - - - // Detect Idles (Normal inter-frame encodings as desribed in - // IEEE802.3 table 35-2) - assign rd_idle = ( - // 1st type of Idle. - (tx_en_fifo_reg1 == 1'b0 && tx_er_fifo_reg1 == 1'b0) - || - // 2nd type of Idle. - (tx_en_fifo_reg1 == 1'b0 && tx_er_fifo_reg1 == 1'b1 - && txd_fifo_reg1 == 8'b0) - - ) ? 1'b1 : 1'b0; - - - - // Create the FIFO read enable. This is not asserted when Idles are - // to be repeated. - always @(posedge gmii_tx_clk_rd) - begin : gen_rd_enable - if (reset_rd == 1'b1) - rd_enable <= 1'b0; - - else begin - if (rd_idle == 1'b1 // Detect an Idle - && nearly_empty == 1'b1) // when FIFO is running empty. - - // Repeat the Idle by freezing read pointer of FIFO (as - // many times as necessary). - rd_enable <= 1'b0; - - else - rd_enable <= 1'b1; - end - end // gen_rd_enable - - - - // Create the FIFO read address pointer. Note that rd_addr_plus2 - // will be converted to gray code and passed across the async clock - // boundary. - always @(posedge gmii_tx_clk_rd) - begin : gen_rd_addr - if (reset_rd == 1'b1) begin - rd_addr_plus2 <= 4'b0010; - rd_addr_plus1 <= 4'b0001; - rd_addr <= 4'b0000; - end - - else if (rd_enable == 1'b1) begin - rd_addr_plus2 <= rd_addr_plus2 + 4'b0001; - rd_addr_plus1 <= rd_addr_plus2; - rd_addr <= rd_addr_plus1; - end - end // gen_rd_addr - - - -//------------------------------------------------------------------------------ -// Create nearly_full threshold in write clock domain. -//------------------------------------------------------------------------------ - -// Please refer to Xilinx Application Note 131 for a complete -// description of this logic. - - - - // Convert Binary Read Pointer to Gray Code. - always @(posedge gmii_tx_clk_rd) - begin : rd_addrgray_bits - if (reset_rd == 1'b1) - rd_addrgray <= 4'b0; - - else begin - rd_addrgray[3] <= rd_addr_plus2[3]; - rd_addrgray[2] <= rd_addr_plus2[3] ^ rd_addr_plus2[2]; - rd_addrgray[1] <= rd_addr_plus2[2] ^ rd_addr_plus2[1]; - rd_addrgray[0] <= rd_addr_plus2[1] ^ rd_addr_plus2[0]; - end - end // rd_addrgray_bits - - - - // Register rd_addrgray on gmii_tx_clk_wr. By reclocking the gray - // code, the worst case senario is that the reclocked value is only - // in error by -1, since only 1 bit at a time changes between gray - // code increment. - genvar j; - generate for (j=0; j<4; j=j+1) - begin : reclock_rd_addrgray - - gige_sfp_sync_block sync_rd_addrgray - ( - .clk (gmii_tx_clk_wr), - .data_in (rd_addrgray[j]), - .data_out (rag_writesync[j]) - ); - - end - endgenerate - - - - // Convert rag_writesync Gray Code read address back to binary. - // This has crossed clock domains from gmii_tx_clk_rd to - // gmii_tx_clk_wr. - assign rd_addrbin[3] = rag_writesync[3]; - assign rd_addrbin[2] = rag_writesync[3] ^ rag_writesync[2]; - - assign rd_addrbin[1] = rag_writesync[3] ^ rag_writesync[2] - ^ rag_writesync[1]; - - assign rd_addrbin[0] = rag_writesync[3] ^ rag_writesync[2] - ^ rag_writesync[1] ^ rag_writesync[0]; - - - - // Determine the occupancy of the FIFO. One clock of latency is - // created here by registering wr_occupancy. - always @(posedge gmii_tx_clk_wr) - begin : gen_wr_occupancy - wr_occupancy <= wr_addr - rd_addrbin; - end // gen_wr_occupancy - - - - // Set nearly_full flag if FIFO occupancy is greater than - // upper_threshold. - assign nearly_full = (wr_occupancy > upper_threshold) ? 1'b1 : 1'b0; - - - -//------------------------------------------------------------------------------ -// Create nearly_empty threshold logic in read clock domain. -//------------------------------------------------------------------------------ - -// Please refer to Xilinx Application Note 131 for a complete -// description of this logic. - - - - // Convert Binary Write Pointer to Gray Code. - always @(posedge gmii_tx_clk_wr) - begin : wr_addrgray_bits - if (reset_wr == 1'b1) - wr_addrgray <= 4'b0; - - else begin - wr_addrgray[3] <= wr_addr_plus2[3]; - wr_addrgray[2] <= wr_addr_plus2[3] ^ wr_addr_plus2[2]; - wr_addrgray[1] <= wr_addr_plus2[2] ^ wr_addr_plus2[1]; - wr_addrgray[0] <= wr_addr_plus2[1] ^ wr_addr_plus2[0]; - end - end // wr_addrgray_bits - - - - // Register wr_addrgray on gmii_tx_clk_rd. By reclocking the gray - // code, the worst case senario is that the reclocked value is only - // in error by -1, since only 1 bit at a time changes between gray - // code increment. - genvar k; - generate for (k=0; k<4; k=k+1) - begin : reclock_wr_addrgray - - gige_sfp_sync_block sync_wr_addrgray - ( - .clk (gmii_tx_clk_rd), - .data_in (wr_addrgray[k]), - .data_out (wag_readsync[k]) - ); - - end - endgenerate - - - - // Convert wag_readsync Gray Code write address back to binary. - // This has crossed clock domains from gmii_tx_clk_wr to - // gmii_tx_clk_rd. - assign wr_addrbin[3] = wag_readsync[3]; - assign wr_addrbin[2] = wag_readsync[3] ^ wag_readsync[2]; - - assign wr_addrbin[1] = wag_readsync[3] ^ wag_readsync[2] - ^ wag_readsync[1]; - - assign wr_addrbin[0] = wag_readsync[3] ^ wag_readsync[2] - ^ wag_readsync[1] ^ wag_readsync[0]; - - - - // Determine the occupancy of the FIFO. One clock of latency is - // created here by registering rd_occupancy. - always @(posedge gmii_tx_clk_rd) - begin : gen_rd_occupancy - rd_occupancy <= wr_addrbin - rd_addr; - end // gen_rd_occupancy - - - - // Set nearly_empty flag if FIFO occupancy is less than - // lower_threshold. - assign nearly_empty = (rd_occupancy < lower_threshold) ? 1'b1 : 1'b0; - - - -endmodule - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v deleted file mode 100755 index 453ab48d5..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v +++ /dev/null @@ -1,267 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version : 2.1 -// \ \ Application : 7 Series FPGAs Transceivers Wizard -// / / Filename : gige_sfp_gtwizard.v -// /___/ /\ -// \ \ / \ -// \___\/\___\ -// -// -// Module GTWIZARD (a GT Wrapper) -// Generated by Xilinx 7 Series FPGAs Transceivers Wizard -// -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -`default_nettype wire - -`timescale 1ns / 1ps -`define DLY #1 - -//***************************** Entity Declaration **************************** - -(* CORE_GENERATION_INFO = "gige_sfp_GTWIZARD,gtwizard_v2_2,{protocol_file=gigabit_ethernet_CC}" *) module gige_sfp_GTWIZARD # - - - - - - -( - // Simulation attributes - parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset - parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C, - parameter PMA_RSV_IN = 32'h00018480, - parameter SIM_VERSION = "3.0" -) -( - //_________________________________________________________________________ - //_________________________________________________________________________ - //GT0 (X0Y4) - //____________________________CHANNEL PORTS________________________________ - //----------------------- Channel - Ref Clock Ports ------------------------ - input GT0_GTREFCLK0_IN, - //------------------------------ Channel PLL ------------------------------- - output GT0_CPLLFBCLKLOST_OUT, - output GT0_CPLLLOCK_OUT, - input GT0_CPLLLOCKDETCLK_IN, - output GT0_CPLLREFCLKLOST_OUT, - input GT0_CPLLRESET_IN, - //----------------------------- Eye Scan Ports ----------------------------- - output GT0_EYESCANDATAERROR_OUT, - //---------------------- Loopback and Powerdown Ports ---------------------- - input [2:0] GT0_LOOPBACK_IN, - input [1:0] GT0_RXPD_IN, - input [1:0] GT0_TXPD_IN, - //----------------------------- Receive Ports ------------------------------ - input GT0_RXUSERRDY_IN, - //--------------------- Receive Ports - 8b10b Decoder ---------------------- - output [1:0] GT0_RXCHARISCOMMA_OUT, - output [1:0] GT0_RXCHARISK_OUT, - output [1:0] GT0_RXDISPERR_OUT, - output [1:0] GT0_RXNOTINTABLE_OUT, - //----------------- Receive Ports - Clock Correction Ports ----------------- - output [1:0] GT0_RXCLKCORCNT_OUT, - //------------- Receive Ports - Comma Detection and Alignment -------------- - input GT0_RXMCOMMAALIGNEN_IN, - input GT0_RXPCOMMAALIGNEN_IN, - //----------------- Receive Ports - RX Data Path interface ----------------- - input GT0_GTRXRESET_IN, - output [15:0] GT0_RXDATA_OUT, - output GT0_RXOUTCLK_OUT, - input GT0_RXPCSRESET_IN, - input GT0_RXUSRCLK_IN, - input GT0_RXUSRCLK2_IN, - //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ - input GT0_GTXRXN_IN, - input GT0_GTXRXP_IN, - output GT0_RXCDRLOCK_OUT, - output GT0_RXELECIDLE_OUT, - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- - input GT0_RXBUFRESET_IN, - output [2:0] GT0_RXBUFSTATUS_OUT, - //---------------------- Receive Ports - RX PLL Ports ---------------------- - output GT0_RXRESETDONE_OUT, - //----------------------------- Transmit Ports ----------------------------- - input GT0_TXUSERRDY_IN, - //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- - input [1:0] GT0_TXCHARDISPMODE_IN, - input [1:0] GT0_TXCHARDISPVAL_IN, - input [1:0] GT0_TXCHARISK_IN, - //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- - output [1:0] GT0_TXBUFSTATUS_OUT, - //---------------- Transmit Ports - TX Data Path interface ----------------- - input GT0_GTTXRESET_IN, - input [15:0] GT0_TXDATA_IN, - output GT0_TXOUTCLK_OUT, - output GT0_TXOUTCLKFABRIC_OUT, - output GT0_TXOUTCLKPCS_OUT, - input GT0_TXPCSRESET_IN, - input GT0_TXUSRCLK_IN, - input GT0_TXUSRCLK2_IN, - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - output GT0_GTXTXN_OUT, - output GT0_GTXTXP_OUT, - //--------------------- Transmit Ports - TX PLL Ports ---------------------- - output GT0_TXRESETDONE_OUT - - - - -); - -//***************************** Wire Declarations ***************************** - - // ground and vcc signals - wire tied_to_ground_i; - wire [63:0] tied_to_ground_vec_i; - wire tied_to_vcc_i; - wire [63:0] tied_to_vcc_vec_i; - - wire gt0_qpllclk_i; - wire gt0_qpllrefclk_i; - - -//********************************* Main Body of Code************************** - - assign tied_to_ground_i = 1'b0; - assign tied_to_ground_vec_i = 64'h0000000000000000; - assign tied_to_vcc_i = 1'b1; - assign tied_to_vcc_vec_i = 64'hffffffffffffffff; - - - -//------------------------- GT Instances ------------------------------- - //_________________________________________________________________________ - //_________________________________________________________________________ - //GT0 (X0Y4) - - gige_sfp_GTWIZARD_GT # - ( - // Simulation attributes - .GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), - .SIM_VERSION (SIM_VERSION), - .RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN), - .PCS_RSVD_ATTR_IN (48'h000000000000), - .PMA_RSV_IN (PMA_RSV_IN) - ) - gt0_GTWIZARD_i - ( - //----------------------- Channel - Ref Clock Ports ------------------------ - .GTREFCLK0_IN (GT0_GTREFCLK0_IN), - //------------------------------ Channel PLL ------------------------------- - .CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT), - .CPLLLOCK_OUT (GT0_CPLLLOCK_OUT), - .CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN), - .CPLLREFCLKLOST_OUT (GT0_CPLLREFCLKLOST_OUT), - .CPLLRESET_IN (GT0_CPLLRESET_IN), - //----------------------------- Eye Scan Ports ----------------------------- - .EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT), - //---------------------- Loopback and Powerdown Ports ---------------------- - .LOOPBACK_IN (GT0_LOOPBACK_IN), - .RXPD_IN (GT0_RXPD_IN), - .TXPD_IN (GT0_TXPD_IN), - //----------------------------- Receive Ports ------------------------------ - .RXUSERRDY_IN (GT0_RXUSERRDY_IN), - //--------------------- Receive Ports - 8b10b Decoder ---------------------- - .RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT), - .RXCHARISK_OUT (GT0_RXCHARISK_OUT), - .RXDISPERR_OUT (GT0_RXDISPERR_OUT), - .RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT), - //----------------- Receive Ports - Clock Correction Ports ----------------- - .RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT), - //------------- Receive Ports - Comma Detection and Alignment -------------- - .RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN), - .RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN), - //----------------- Receive Ports - RX Data Path interface ----------------- - .GTRXRESET_IN (GT0_GTRXRESET_IN), - .RXDATA_OUT (GT0_RXDATA_OUT), - .RXOUTCLK_OUT (GT0_RXOUTCLK_OUT), - .RXPCSRESET_IN (GT0_RXPCSRESET_IN), - .RXUSRCLK_IN (GT0_RXUSRCLK_IN), - .RXUSRCLK2_IN (GT0_RXUSRCLK2_IN), - //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ - .GTXRXN_IN (GT0_GTXRXN_IN), - .GTXRXP_IN (GT0_GTXRXP_IN), - .RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT), - .RXELECIDLE_OUT (GT0_RXELECIDLE_OUT), - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- - .RXBUFRESET_IN (GT0_RXBUFRESET_IN), - .RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT), - //---------------------- Receive Ports - RX PLL Ports ---------------------- - .RXRESETDONE_OUT (GT0_RXRESETDONE_OUT), - //----------------------------- Transmit Ports ----------------------------- - .TXUSERRDY_IN (GT0_TXUSERRDY_IN), - //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- - .TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN), - .TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN), - .TXCHARISK_IN (GT0_TXCHARISK_IN), - //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- - .TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT), - //---------------- Transmit Ports - TX Data Path interface ----------------- - .GTTXRESET_IN (GT0_GTTXRESET_IN), - .TXDATA_IN (GT0_TXDATA_IN), - .TXOUTCLK_OUT (GT0_TXOUTCLK_OUT), - .TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT), - .TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT), - .TXPCSRESET_IN (GT0_TXPCSRESET_IN), - .TXUSRCLK_IN (GT0_TXUSRCLK_IN), - .TXUSRCLK2_IN (GT0_TXUSRCLK2_IN), - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - .GTXTXN_OUT (GT0_GTXTXN_OUT), - .GTXTXP_OUT (GT0_GTXTXP_OUT), - //--------------------- Transmit Ports - TX PLL Ports ---------------------- - .TXRESETDONE_OUT (GT0_TXRESETDONE_OUT) - - ); -endmodule - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.xco b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.xco deleted file mode 100755 index 1796ae0d2..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.xco +++ /dev/null @@ -1,565 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.2 -# Date: Sat Jun 16 13:46:27 2012 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:gtwizard:2.2 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7vx485t -SET devicefamily = virtex7 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg1157 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT 7_Series_FPGAs_Transceivers_Wizard xilinx.com:ip:gtwizard:2.2 -# END Select -# BEGIN Parameters -CSET advanced_clocking=false -CSET component_name=gige_sfp_GTWIZARD -CSET gt0_pll0_fbdiv=1 -CSET gt0_pll0_fbdiv_45=4 -CSET gt0_pll0_refclk_div=1 -CSET gt0_pll0_rxout_div=0 -CSET gt0_pll0_txout_div=0 -CSET gt0_pll1_fbdiv=1 -CSET gt0_pll1_fbdiv_45=4 -CSET gt0_pll1_refclk_div=1 -CSET gt0_pll1_rxout_div=0 -CSET gt0_pll1_txout_div=0 -CSET gt0_val=false -CSET gt0_val_agc_mode=Auto -CSET gt0_val_align_comma_double=false -CSET gt0_val_align_comma_enable=0001111111 -CSET gt0_val_align_comma_word=Two_Byte_Boundaries -CSET gt0_val_align_mcomma_det=true -CSET gt0_val_align_mcomma_value=1010000011 -CSET gt0_val_align_pcomma_det=true -CSET gt0_val_align_pcomma_value=0101111100 -CSET gt0_val_cb=false -CSET gt0_val_cc=true -CSET gt0_val_cc_seq_periodicity=5000 -CSET gt0_val_chan_bond_max_skew=1 -CSET gt0_val_chan_bond_seq_1_1=00000000 -CSET gt0_val_chan_bond_seq_1_1_disp=false -CSET gt0_val_chan_bond_seq_1_1_k=false -CSET gt0_val_chan_bond_seq_1_1_mask=false -CSET gt0_val_chan_bond_seq_1_2=00000000 -CSET gt0_val_chan_bond_seq_1_2_disp=false -CSET gt0_val_chan_bond_seq_1_2_k=false -CSET gt0_val_chan_bond_seq_1_2_mask=false -CSET gt0_val_chan_bond_seq_1_3=00000000 -CSET gt0_val_chan_bond_seq_1_3_disp=false -CSET gt0_val_chan_bond_seq_1_3_k=false -CSET gt0_val_chan_bond_seq_1_3_mask=false -CSET gt0_val_chan_bond_seq_1_4=00000000 -CSET gt0_val_chan_bond_seq_1_4_disp=false -CSET gt0_val_chan_bond_seq_1_4_k=false -CSET gt0_val_chan_bond_seq_1_4_mask=false -CSET gt0_val_chan_bond_seq_2_1=00000000 -CSET gt0_val_chan_bond_seq_2_1_disp=false -CSET gt0_val_chan_bond_seq_2_1_k=false -CSET gt0_val_chan_bond_seq_2_1_mask=false -CSET gt0_val_chan_bond_seq_2_2=00000000 -CSET gt0_val_chan_bond_seq_2_2_disp=false -CSET gt0_val_chan_bond_seq_2_2_k=false -CSET gt0_val_chan_bond_seq_2_2_mask=false -CSET gt0_val_chan_bond_seq_2_3=00000000 -CSET gt0_val_chan_bond_seq_2_3_disp=false -CSET gt0_val_chan_bond_seq_2_3_k=false -CSET gt0_val_chan_bond_seq_2_3_mask=false -CSET gt0_val_chan_bond_seq_2_4=00000000 -CSET gt0_val_chan_bond_seq_2_4_disp=false -CSET gt0_val_chan_bond_seq_2_4_k=false -CSET gt0_val_chan_bond_seq_2_4_mask=false -CSET gt0_val_chan_bond_seq_2_use=false -CSET gt0_val_chan_bond_seq_len=1 -CSET gt0_val_clk_cor_seq_1_1=10111100 -CSET gt0_val_clk_cor_seq_1_1_disp=false -CSET gt0_val_clk_cor_seq_1_1_k=true -CSET gt0_val_clk_cor_seq_1_1_mask=false -CSET gt0_val_clk_cor_seq_1_2=01010000 -CSET gt0_val_clk_cor_seq_1_2_disp=false -CSET gt0_val_clk_cor_seq_1_2_k=false -CSET gt0_val_clk_cor_seq_1_2_mask=false -CSET gt0_val_clk_cor_seq_1_3=00000000 -CSET gt0_val_clk_cor_seq_1_3_disp=false -CSET gt0_val_clk_cor_seq_1_3_k=false -CSET gt0_val_clk_cor_seq_1_3_mask=false -CSET gt0_val_clk_cor_seq_1_4=00000000 -CSET gt0_val_clk_cor_seq_1_4_disp=false -CSET gt0_val_clk_cor_seq_1_4_k=false -CSET gt0_val_clk_cor_seq_1_4_mask=false -CSET gt0_val_clk_cor_seq_2_1=10111100 -CSET gt0_val_clk_cor_seq_2_1_disp=false -CSET gt0_val_clk_cor_seq_2_1_k=true -CSET gt0_val_clk_cor_seq_2_1_mask=false -CSET gt0_val_clk_cor_seq_2_2=10110101 -CSET gt0_val_clk_cor_seq_2_2_disp=false -CSET gt0_val_clk_cor_seq_2_2_k=false -CSET gt0_val_clk_cor_seq_2_2_mask=false -CSET gt0_val_clk_cor_seq_2_3=00000000 -CSET gt0_val_clk_cor_seq_2_3_disp=false -CSET gt0_val_clk_cor_seq_2_3_k=false -CSET gt0_val_clk_cor_seq_2_3_mask=false -CSET gt0_val_clk_cor_seq_2_4=00000000 -CSET gt0_val_clk_cor_seq_2_4_disp=false -CSET gt0_val_clk_cor_seq_2_4_k=false -CSET gt0_val_clk_cor_seq_2_4_mask=false -CSET gt0_val_clk_cor_seq_2_use=true -CSET gt0_val_clk_cor_seq_len=2 -CSET gt0_val_comma_preset=K28.5 -CSET gt0_val_cpll_fbdiv=4 -CSET gt0_val_cpll_fbdiv_45=5 -CSET gt0_val_cpll_refclk_div=1 -CSET gt0_val_cpll_rxout_div=4 -CSET gt0_val_cpll_txout_div=4 -CSET gt0_val_dec_mcomma_detect=true -CSET gt0_val_dec_pcomma_detect=true -CSET gt0_val_dec_valid_comma_only=false -CSET gt0_val_decoding=8B/10B -CSET gt0_val_dfe_mode=DFE-Auto -CSET gt0_val_drp=false -CSET gt0_val_drp_clock=100 -CSET gt0_val_encoding=8B/10B -CSET gt0_val_max_cb_level=7 -CSET gt0_val_no_rx=false -CSET gt0_val_no_tx=false -CSET gt0_val_oob=false -CSET gt0_val_pcs_pcie_en=false -CSET gt0_val_pd_trans_time_from_p2=60 -CSET gt0_val_pd_trans_time_non_p2=25 -CSET gt0_val_pd_trans_time_to_p2=100 -CSET gt0_val_port_cominitdet=false -CSET gt0_val_port_comsasdet=false -CSET gt0_val_port_comwakedet=false -CSET gt0_val_port_cpllpd=false -CSET gt0_val_port_loopback=true -CSET gt0_val_port_phystatus=false -CSET gt0_val_port_pll0pd=false -CSET gt0_val_port_pll1pd=false -CSET gt0_val_port_qpllpd=false -CSET gt0_val_port_rxbufreset=true -CSET gt0_val_port_rxbufstatus=true -CSET gt0_val_port_rxbyteisaligned=false -CSET gt0_val_port_rxbyterealign=false -CSET gt0_val_port_rxcdrhold=false -CSET gt0_val_port_rxchariscomma=true -CSET gt0_val_port_rxcharisk=true -CSET gt0_val_port_rxcommadet=false -CSET gt0_val_port_rxdfeagcovrden=false -CSET gt0_val_port_rxdfereset=false -CSET gt0_val_port_rxelecidle=true -CSET gt0_val_port_rxlpmhfovrden=false -CSET gt0_val_port_rxlpmlfklovrden=false -CSET gt0_val_port_rxmcommaalignen=true -CSET gt0_val_port_rxoutclk=true -CSET gt0_val_port_rxpcommaalignen=true -CSET gt0_val_port_rxpcsreset=true -CSET gt0_val_port_rxpmareset=false -CSET gt0_val_port_rxpolarity=false -CSET gt0_val_port_rxpowerdown=true -CSET gt0_val_port_rxqpien=false -CSET gt0_val_port_rxqpisenn=false -CSET gt0_val_port_rxqpisenp=false -CSET gt0_val_port_rxrate=false -CSET gt0_val_port_rxslide=false -CSET gt0_val_port_rxstatus=false -CSET gt0_val_port_rxsysclksel=false -CSET gt0_val_port_rxvalid=false -CSET gt0_val_port_tx8b10bbypass=false -CSET gt0_val_port_txbufstatus=true -CSET gt0_val_port_txchardispmode=true -CSET gt0_val_port_txchardispval=true -CSET gt0_val_port_txcomfinish=false -CSET gt0_val_port_txcominit=false -CSET gt0_val_port_txcomsas=false -CSET gt0_val_port_txcomwake=false -CSET gt0_val_port_txdetectrx=false -CSET gt0_val_port_txelecidle=false -CSET gt0_val_port_txinhibit=false -CSET gt0_val_port_txoutclk=true -CSET gt0_val_port_txpcsreset=true -CSET gt0_val_port_txpmareset=false -CSET gt0_val_port_txpolarity=false -CSET gt0_val_port_txpowerdown=true -CSET gt0_val_port_txprbsforceerr=false -CSET gt0_val_port_txprbssel=false -CSET gt0_val_port_txqpibiasen=false -CSET gt0_val_port_txqpisenn=false -CSET gt0_val_port_txqpisenp=false -CSET gt0_val_port_txqpistrongpdown=false -CSET gt0_val_port_txqpiweakpup=false -CSET gt0_val_port_txrate=false -CSET gt0_val_port_txsysclksel=false -CSET gt0_val_ppm_offset=100 -CSET gt0_val_prbs_detector=false -CSET gt0_val_protocol_file=gigabit_ethernet_CC -CSET gt0_val_qpll_fbdiv=16 -CSET gt0_val_qpll_refclk_div=1 -CSET gt0_val_rx_buffer_bypass_mode=Auto -CSET gt0_val_rx_cm_trim=100 -CSET gt0_val_rx_data_width=16 -CSET gt0_val_rx_int_datawidth=20 -CSET gt0_val_rx_line_rate=1.25 -CSET gt0_val_rx_refclk=REFCLK1_Q0 -CSET gt0_val_rx_reference_clock=125.000 -CSET gt0_val_rx_termination_voltage=GND -CSET gt0_val_rxbuf_en=true -CSET gt0_val_rxcomma_deten=true -CSET gt0_val_rxoutclk_source=false -CSET gt0_val_rxprbs_err_loopback=false -CSET gt0_val_rxslide_mode=OFF -CSET gt0_val_rxusrclk=RXOUTCLK -CSET gt0_val_sata_e_idle_val=4 -CSET gt0_val_sata_rx_burst_val=4 -CSET gt0_val_tx_buffer_bypass_mode=Auto -CSET gt0_val_tx_data_width=16 -CSET gt0_val_tx_int_datawidth=20 -CSET gt0_val_tx_line_rate=1.25 -CSET gt0_val_tx_refclk=REFCLK1_Q0 -CSET gt0_val_tx_reference_clock=125.000 -CSET gt0_val_txbuf_en=true -CSET gt0_val_txdiff_emph_mode=Custom -CSET gt0_val_txdiffctrl=false -CSET gt0_val_txoutclk_source=true -CSET gt0_val_txpostcursor=false -CSET gt0_val_txprecursor=false -CSET gt0_val_txusrclk=TXOUTCLK -CSET gt10_val=false -CSET gt10_val_rx_refclk=REFCLK1_Q2 -CSET gt10_val_tx_refclk=REFCLK1_Q2 -CSET gt11_val=false -CSET gt11_val_rx_refclk=REFCLK1_Q2 -CSET gt11_val_tx_refclk=REFCLK1_Q2 -CSET gt12_val=false -CSET gt12_val_rx_refclk=REFCLK1_Q3 -CSET gt12_val_tx_refclk=REFCLK1_Q3 -CSET gt13_val=false -CSET gt13_val_rx_refclk=REFCLK1_Q3 -CSET gt13_val_tx_refclk=REFCLK1_Q3 -CSET gt14_val=false -CSET gt14_val_rx_refclk=REFCLK1_Q3 -CSET gt14_val_tx_refclk=REFCLK1_Q3 -CSET gt15_val=false -CSET gt15_val_rx_refclk=REFCLK1_Q3 -CSET gt15_val_tx_refclk=REFCLK1_Q3 -CSET gt16_val=false -CSET gt16_val_rx_refclk=REFCLK1_Q4 -CSET gt16_val_tx_refclk=REFCLK1_Q4 -CSET gt17_val=false -CSET gt17_val_rx_refclk=REFCLK1_Q4 -CSET gt17_val_tx_refclk=REFCLK1_Q4 -CSET gt18_val=false -CSET gt18_val_rx_refclk=REFCLK1_Q4 -CSET gt18_val_tx_refclk=REFCLK1_Q4 -CSET gt19_val=false -CSET gt19_val_rx_refclk=REFCLK1_Q4 -CSET gt19_val_tx_refclk=REFCLK1_Q4 -CSET gt1_val=false -CSET gt1_val_rx_refclk=REFCLK1_Q0 -CSET gt1_val_tx_refclk=REFCLK1_Q0 -CSET gt20_val=false -CSET gt20_val_rx_refclk=REFCLK1_Q5 -CSET gt20_val_tx_refclk=REFCLK1_Q5 -CSET gt21_val=false -CSET gt21_val_rx_refclk=REFCLK1_Q5 -CSET gt21_val_tx_refclk=REFCLK1_Q5 -CSET gt22_val=false -CSET gt22_val_rx_refclk=REFCLK1_Q5 -CSET gt22_val_tx_refclk=REFCLK1_Q5 -CSET gt23_val=false -CSET gt23_val_rx_refclk=REFCLK1_Q5 -CSET gt23_val_tx_refclk=REFCLK1_Q5 -CSET gt24_val=false -CSET gt24_val_rx_refclk=REFCLK1_Q6 -CSET gt24_val_tx_refclk=REFCLK1_Q6 -CSET gt25_val=false -CSET gt25_val_rx_refclk=REFCLK1_Q6 -CSET gt25_val_tx_refclk=REFCLK1_Q6 -CSET gt26_val=false -CSET gt26_val_rx_refclk=REFCLK1_Q6 -CSET gt26_val_tx_refclk=REFCLK1_Q6 -CSET gt27_val=false -CSET gt27_val_rx_refclk=REFCLK1_Q6 -CSET gt27_val_tx_refclk=REFCLK1_Q6 -CSET gt28_val=false -CSET gt28_val_rx_refclk=REFCLK1_Q7 -CSET gt28_val_tx_refclk=REFCLK1_Q7 -CSET gt29_val=false -CSET gt29_val_rx_refclk=REFCLK1_Q7 -CSET gt29_val_tx_refclk=REFCLK1_Q7 -CSET gt2_val=false -CSET gt2_val_rx_refclk=REFCLK1_Q0 -CSET gt2_val_tx_refclk=REFCLK1_Q0 -CSET gt30_val=false -CSET gt30_val_rx_refclk=REFCLK1_Q7 -CSET gt30_val_tx_refclk=REFCLK1_Q7 -CSET gt31_val=false -CSET gt31_val_rx_refclk=REFCLK1_Q7 -CSET gt31_val_tx_refclk=REFCLK1_Q7 -CSET gt32_val=false -CSET gt32_val_rx_refclk=REFCLK1_Q8 -CSET gt32_val_tx_refclk=REFCLK1_Q8 -CSET gt33_val=false -CSET gt33_val_rx_refclk=REFCLK1_Q8 -CSET gt33_val_tx_refclk=REFCLK1_Q8 -CSET gt34_val=false -CSET gt34_val_rx_refclk=REFCLK1_Q8 -CSET gt34_val_tx_refclk=REFCLK1_Q8 -CSET gt35_val=false -CSET gt35_val_rx_refclk=REFCLK1_Q8 -CSET gt35_val_tx_refclk=REFCLK1_Q8 -CSET gt36_val=false -CSET gt36_val_rx_refclk=REFCLK1_Q9 -CSET gt36_val_tx_refclk=REFCLK1_Q9 -CSET gt37_val=false -CSET gt37_val_rx_refclk=REFCLK1_Q9 -CSET gt37_val_tx_refclk=REFCLK1_Q9 -CSET gt38_val=false -CSET gt38_val_rx_refclk=REFCLK1_Q9 -CSET gt38_val_tx_refclk=REFCLK1_Q9 -CSET gt39_val=false -CSET gt39_val_rx_refclk=REFCLK1_Q9 -CSET gt39_val_tx_refclk=REFCLK1_Q9 -CSET gt3_val=false -CSET gt3_val_rx_refclk=REFCLK1_Q0 -CSET gt3_val_tx_refclk=REFCLK1_Q0 -CSET gt4_val=true -CSET gt4_val_rx_refclk=REFCLK1_Q1 -CSET gt4_val_tx_refclk=REFCLK1_Q1 -CSET gt5_val=false -CSET gt5_val_rx_refclk=REFCLK1_Q1 -CSET gt5_val_tx_refclk=REFCLK1_Q1 -CSET gt6_val=false -CSET gt6_val_rx_refclk=REFCLK1_Q1 -CSET gt6_val_tx_refclk=REFCLK1_Q1 -CSET gt7_val=false -CSET gt7_val_rx_refclk=REFCLK1_Q1 -CSET gt7_val_tx_refclk=REFCLK1_Q1 -CSET gt8_val=false -CSET gt8_val_rx_refclk=REFCLK1_Q2 -CSET gt8_val_tx_refclk=REFCLK1_Q2 -CSET gt9_val=false -CSET gt9_val_rx_refclk=REFCLK1_Q2 -CSET gt9_val_tx_refclk=REFCLK1_Q2 -CSET gt_column=right_column -CSET gt_row=top_row -CSET gt_type=GTX -CSET gt_val_drp=false -CSET gt_val_drp_clock=60 -CSET gt_val_rx_pll=CPLL -CSET gt_val_tx_pll=CPLL -CSET gtz0_val_data_width=160 -CSET gtz0_val_encoding=100GBASER_MODE -CSET gtz0_val_no_rx=false -CSET gtz0_val_no_tx=false -CSET gtz0_val_port_corecntl=false -CSET gtz0_val_port_loopback=false -CSET gtz0_val_port_pllrecalen=false -CSET gtz0_val_port_refsel=false -CSET gtz0_val_port_rxbitslip=false -CSET gtz0_val_port_rxen=false -CSET gtz0_val_port_rxfibreset=false -CSET gtz0_val_port_rxfifostatus=false -CSET gtz0_val_port_rxpolarity=false -CSET gtz0_val_port_rxprbs=false -CSET gtz0_val_port_rxratesel=false -CSET gtz0_val_port_rxsignalok=false -CSET gtz0_val_port_txattnctrl=false -CSET gtz0_val_port_txen=false -CSET gtz0_val_port_txeqpostctrl=false -CSET gtz0_val_port_txeqprectrl=false -CSET gtz0_val_port_txfibreset=false -CSET gtz0_val_port_txfifostatus=false -CSET gtz0_val_port_txoutputen=false -CSET gtz0_val_port_txpolarity=false -CSET gtz0_val_port_txprbs=false -CSET gtz0_val_port_txratesel=false -CSET gtz0_val_port_txslewctrl=false -CSET gtz0_val_protocol_file=Start_from_scratch -CSET gtz0_val_refclk_source=REFCLK0 -CSET gtz0_val_reference_clock=322.266 -CSET gtz0_val_rx_line_rate=25.78125 -CSET gtz0_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz0_val_rxusrclk_source=RXUSRCLK0 -CSET gtz0_val_tx_line_rate=25.78125 -CSET gtz0_val_txoutclk_source=TX_FIFO_CLK -CSET gtz0_val_txusrclk_source=TXUSRCLK0 -CSET gtz1_val_data_width=160 -CSET gtz1_val_encoding=100GBASER_MODE -CSET gtz1_val_no_rx=false -CSET gtz1_val_no_tx=false -CSET gtz1_val_protocol_file=Start_from_scratch -CSET gtz1_val_refclk_source=REFCLK0 -CSET gtz1_val_reference_clock=322.266 -CSET gtz1_val_rx_line_rate=25.78125 -CSET gtz1_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz1_val_rxusrclk_source=RXUSRCLK0 -CSET gtz1_val_tx_line_rate=25.78125 -CSET gtz1_val_txoutclk_source=TX_FIFO_CLK -CSET gtz1_val_txusrclk_source=TXUSRCLK0 -CSET gtz2_val_data_width=160 -CSET gtz2_val_encoding=100GBASER_MODE -CSET gtz2_val_no_rx=false -CSET gtz2_val_no_tx=false -CSET gtz2_val_protocol_file=Start_from_scratch -CSET gtz2_val_refclk_source=REFCLK0 -CSET gtz2_val_reference_clock=322.266 -CSET gtz2_val_rx_line_rate=25.78125 -CSET gtz2_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz2_val_rxusrclk_source=RXUSRCLK0 -CSET gtz2_val_tx_line_rate=25.78125 -CSET gtz2_val_txoutclk_source=TX_FIFO_CLK -CSET gtz2_val_txusrclk_source=TXUSRCLK0 -CSET gtz3_val_data_width=160 -CSET gtz3_val_encoding=100GBASER_MODE -CSET gtz3_val_no_rx=false -CSET gtz3_val_no_tx=false -CSET gtz3_val_protocol_file=Start_from_scratch -CSET gtz3_val_refclk_source=REFCLK0 -CSET gtz3_val_reference_clock=322.266 -CSET gtz3_val_rx_line_rate=25.78125 -CSET gtz3_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz3_val_rxusrclk_source=RXUSRCLK0 -CSET gtz3_val_tx_line_rate=25.78125 -CSET gtz3_val_txoutclk_source=TX_FIFO_CLK -CSET gtz3_val_txusrclk_source=TXUSRCLK0 -CSET gtz4_val_data_width=160 -CSET gtz4_val_encoding=100GBASER_MODE -CSET gtz4_val_no_rx=false -CSET gtz4_val_no_tx=false -CSET gtz4_val_protocol_file=Start_from_scratch -CSET gtz4_val_refclk_source=REFCLK0 -CSET gtz4_val_reference_clock=322.266 -CSET gtz4_val_rx_line_rate=25.78125 -CSET gtz4_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz4_val_rxusrclk_source=RXUSRCLK0 -CSET gtz4_val_tx_line_rate=25.78125 -CSET gtz4_val_txoutclk_source=TX_FIFO_CLK -CSET gtz4_val_txusrclk_source=TXUSRCLK0 -CSET gtz5_val_data_width=160 -CSET gtz5_val_encoding=100GBASER_MODE -CSET gtz5_val_no_rx=false -CSET gtz5_val_no_tx=false -CSET gtz5_val_protocol_file=Start_from_scratch -CSET gtz5_val_refclk_source=REFCLK0 -CSET gtz5_val_reference_clock=322.266 -CSET gtz5_val_rx_line_rate=25.78125 -CSET gtz5_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz5_val_rxusrclk_source=RXUSRCLK0 -CSET gtz5_val_tx_line_rate=25.78125 -CSET gtz5_val_txoutclk_source=TX_FIFO_CLK -CSET gtz5_val_txusrclk_source=TXUSRCLK0 -CSET gtz6_val_data_width=160 -CSET gtz6_val_encoding=100GBASER_MODE -CSET gtz6_val_no_rx=false -CSET gtz6_val_no_tx=false -CSET gtz6_val_protocol_file=Start_from_scratch -CSET gtz6_val_refclk_source=REFCLK0 -CSET gtz6_val_reference_clock=322.266 -CSET gtz6_val_rx_line_rate=25.78125 -CSET gtz6_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz6_val_rxusrclk_source=RXUSRCLK0 -CSET gtz6_val_tx_line_rate=25.78125 -CSET gtz6_val_txoutclk_source=TX_FIFO_CLK -CSET gtz6_val_txusrclk_source=TXUSRCLK0 -CSET gtz7_val_data_width=160 -CSET gtz7_val_encoding=100GBASER_MODE -CSET gtz7_val_no_rx=false -CSET gtz7_val_no_tx=false -CSET gtz7_val_protocol_file=Start_from_scratch -CSET gtz7_val_refclk_source=REFCLK0 -CSET gtz7_val_reference_clock=322.266 -CSET gtz7_val_rx_line_rate=25.78125 -CSET gtz7_val_rxoutclk_source=RX_FIFO_CLK -CSET gtz7_val_rxusrclk_source=RXUSRCLK0 -CSET gtz7_val_tx_line_rate=25.78125 -CSET gtz7_val_txoutclk_source=TX_FIFO_CLK -CSET gtz7_val_txusrclk_source=TXUSRCLK0 -CSET identical_config=true -CSET identical_protocol_file=gigabit_ethernet_CC -CSET identical_val_no_rx=false -CSET identical_val_no_tx=false -CSET identical_val_rx_line_rate=1.25 -CSET identical_val_rx_reference_clock=125.000 -CSET identical_val_tx_line_rate=1.25 -CSET identical_val_tx_reference_clock=125.000 -CSET octal0_val=true -CSET octal0_val_drpclk_source=DRPCLK0 -CSET octal0_val_identical_config=true -CSET octal0_val_identical_no_rx=false -CSET octal0_val_identical_no_tx=false -CSET octal0_val_identical_protocol_file=Start_from_scratch -CSET octal0_val_identical_reference_clock=322.266 -CSET octal0_val_identical_rx_line_rate=25.78125 -CSET octal0_val_identical_tx_line_rate=25.78125 -CSET octal0_val_master_slave=true -CSET octal0_val_multi_channel_mode=x4_channels_0to3 -CSET octal0_val_rxoutclk0_source=RXOUTCLK_LANE0 -CSET octal0_val_rxoutclk1_source=RXOUTCLK_LANE0 -CSET octal0_val_rxoutclk2_source=RXOUTCLK_LANE0 -CSET octal0_val_rxoutclk3_source=RXOUTCLK_LANE0 -CSET octal0_val_rxusrclk0_source=RXOUTCLK0 -CSET octal0_val_rxusrclk1_source=RXOUTCLK0 -CSET octal0_val_rxusrclk2_source=RXOUTCLK0 -CSET octal0_val_rxusrclk3_source=RXOUTCLK0 -CSET octal0_val_rxusrclk4_source=RXOUTCLK0 -CSET octal0_val_rxusrclk5_source=RXOUTCLK0 -CSET octal0_val_rxusrclk6_source=RXOUTCLK0 -CSET octal0_val_rxusrclk7_source=RXOUTCLK0 -CSET octal0_val_txoutclk0_source=TXOUTCLK_LANE0 -CSET octal0_val_txoutclk1_source=TXOUTCLK_LANE0 -CSET octal0_val_txusrclk0_source=TXOUTCLK0 -CSET octal0_val_txusrclk1_source=TXOUTCLK0 -CSET octal0_val_txusrclk2_source=TXOUTCLK0 -CSET octal0_val_txusrclk3_source=TXOUTCLK0 -CSET octal0_val_txusrclk4_source=TXOUTCLK0 -CSET octal0_val_txusrclk5_source=TXOUTCLK0 -CSET octal0_val_txusrclk6_source=TXOUTCLK0 -CSET octal0_val_txusrclk7_source=TXOUTCLK0 -CSET octal1_val=false -CSET pcie_cb_en=false -CSET pcie_cb_mode=One_Hop -CSET pcie_lpm_dfe=DFE -CSET pcie_sync_mode=false -CSET silicon_version=no_silicon_version_loaded -CSET use_gtz0=true -CSET use_gtz1=true -CSET use_gtz2=true -CSET use_gtz3=true -CSET use_gtz4=true -CSET use_gtz5=true -CSET use_gtz6=true -CSET use_gtz7=true -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-05-30T18:05:18Z -# END Extra information -GENERATE -# CRC: 16b8aa6d - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v deleted file mode 100755 index 73ce6bf83..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v +++ /dev/null @@ -1,740 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version : 2.1 -// \ \ Application : GT Wizard -// / / Filename : gige_sfp_gtwizard_gt.v -// /___/ /\ -// \ \ / \ -// \___\/\___\ -// -// -// Module GTWIZARD_GT (a GT Wrapper) -// Generated by Xilinx GT Wizard -// -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -`default_nettype wire - -`timescale 1ns / 1ps - - -//***************************** Entity Declaration **************************** - -module gige_sfp_GTWIZARD_GT # -( - // Simulation attributes - parameter GT_SIM_GTRESET_SPEEDUP = "false", // Set to 1 to speed up sim reset; - parameter RX_DFE_KL_CFG2_IN = 32'h3008E56A, - parameter PMA_RSV_IN = 32'h00000000, - parameter PCS_RSVD_ATTR_IN = 48'h000000000000, - parameter SIM_VERSION = ("3.0") -) -( - //----------------------- Channel - Ref Clock Ports ------------------------ - input GTREFCLK0_IN, - //------------------------------ Channel PLL ------------------------------- - output CPLLFBCLKLOST_OUT, - output CPLLLOCK_OUT, - input CPLLLOCKDETCLK_IN, - output CPLLREFCLKLOST_OUT, - input CPLLRESET_IN, - //----------------------------- Eye Scan Ports ----------------------------- - output EYESCANDATAERROR_OUT, - //---------------------- Loopback and Powerdown Ports ---------------------- - input [2:0] LOOPBACK_IN, - input [1:0] RXPD_IN, - input [1:0] TXPD_IN, - //----------------------------- Receive Ports ------------------------------ - input RXUSERRDY_IN, - //--------------------- Receive Ports - 8b10b Decoder ---------------------- - output [1:0] RXCHARISCOMMA_OUT, - output [1:0] RXCHARISK_OUT, - output [1:0] RXDISPERR_OUT, - output [1:0] RXNOTINTABLE_OUT, - //----------------- Receive Ports - Clock Correction Ports ----------------- - output [1:0] RXCLKCORCNT_OUT, - //------------- Receive Ports - Comma Detection and Alignment -------------- - input RXMCOMMAALIGNEN_IN, - input RXPCOMMAALIGNEN_IN, - //----------------- Receive Ports - RX Data Path interface ----------------- - input GTRXRESET_IN, - output [15:0] RXDATA_OUT, - output RXOUTCLK_OUT, - input RXPCSRESET_IN, - input RXUSRCLK_IN, - input RXUSRCLK2_IN, - //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ - input GTXRXN_IN, - input GTXRXP_IN, - output RXCDRLOCK_OUT, - output RXELECIDLE_OUT, - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- - input RXBUFRESET_IN, - output [2:0] RXBUFSTATUS_OUT, - //---------------------- Receive Ports - RX PLL Ports ---------------------- - output RXRESETDONE_OUT, - //----------------------------- Transmit Ports ----------------------------- - input TXUSERRDY_IN, - //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- - input [1:0] TXCHARDISPMODE_IN, - input [1:0] TXCHARDISPVAL_IN, - input [1:0] TXCHARISK_IN, - //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- - output [1:0] TXBUFSTATUS_OUT, - //---------------- Transmit Ports - TX Data Path interface ----------------- - input GTTXRESET_IN, - input [15:0] TXDATA_IN, - output TXOUTCLK_OUT, - output TXOUTCLKFABRIC_OUT, - output TXOUTCLKPCS_OUT, - input TXPCSRESET_IN, - input TXUSRCLK_IN, - input TXUSRCLK2_IN, - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - output GTXTXN_OUT, - output GTXTXP_OUT, - //--------------------- Transmit Ports - TX PLL Ports ---------------------- - output TXRESETDONE_OUT - - -); - - -//***************************** Wire Declarations ***************************** - - // ground and vcc signals - wire tied_to_ground_i; - wire [63:0] tied_to_ground_vec_i; - wire tied_to_vcc_i; - wire [63:0] tied_to_vcc_vec_i; - - - //RX Datapath signals - wire [63:0] rxdata_i; - wire [5:0] rxchariscomma_float_i; - wire [5:0] rxcharisk_float_i; - wire [5:0] rxdisperr_float_i; - wire [5:0] rxnotintable_float_i; - wire [5:0] rxrundisp_float_i; - - - //TX Datapath signals - wire [63:0] txdata_i; - wire [5:0] txkerr_float_i; - wire [5:0] txrundisp_float_i; - -// -//********************************* Main Body of Code************************** - - //------------------------- Static signal Assigments --------------------- - - assign tied_to_ground_i = 1'b0; - assign tied_to_ground_vec_i = 64'h0000000000000000; - assign tied_to_vcc_i = 1'b1; - assign tied_to_vcc_vec_i = 64'hffffffffffffffff; - - //------------------- GT Datapath byte mapping ----------------- - assign RXDATA_OUT = rxdata_i[15:0]; - - - assign txdata_i = {tied_to_ground_vec_i[47:0],TXDATA_IN}; - - - - - //------------------------- GT Instantiations -------------------------- - GTXE2_CHANNEL # - ( - //_______________________ Simulation-Only Attributes __________________ - - .SIM_RECEIVER_DETECT_PASS ("TRUE"), - .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), - .SIM_RESET_SPEEDUP (GT_SIM_GTRESET_SPEEDUP), - .SIM_CPLLREFCLK_SEL (3'b001), - .SIM_VERSION (SIM_VERSION), - - - //----------------RX Byte and Word Alignment Attributes--------------- - .ALIGN_COMMA_DOUBLE ("FALSE"), - .ALIGN_COMMA_ENABLE (10'b0001111111), - .ALIGN_COMMA_WORD (2), - .ALIGN_MCOMMA_DET ("TRUE"), - .ALIGN_MCOMMA_VALUE (10'b1010000011), - .ALIGN_PCOMMA_DET ("TRUE"), - .ALIGN_PCOMMA_VALUE (10'b0101111100), - .SHOW_REALIGN_COMMA ("TRUE"), - .RXSLIDE_AUTO_WAIT (7), - .RXSLIDE_MODE ("OFF"), - .RX_SIG_VALID_DLY (10), - - //----------------RX 8B/10B Decoder Attributes--------------- - .RX_DISPERR_SEQ_MATCH ("TRUE"), - .DEC_MCOMMA_DETECT ("TRUE"), - .DEC_PCOMMA_DETECT ("TRUE"), - .DEC_VALID_COMMA_ONLY ("FALSE"), - - //----------------------RX Clock Correction Attributes---------------------- - .CBCC_DATA_SOURCE_SEL ("DECODED"), - .CLK_COR_SEQ_2_USE ("TRUE"), - .CLK_COR_KEEP_IDLE ("FALSE"), - .CLK_COR_MAX_LAT (15), - .CLK_COR_MIN_LAT (12), - .CLK_COR_PRECEDENCE ("TRUE"), - .CLK_COR_REPEAT_WAIT (0), - .CLK_COR_SEQ_LEN (2), - .CLK_COR_SEQ_1_ENABLE (4'b1111), - .CLK_COR_SEQ_1_1 (10'b0110111100), - .CLK_COR_SEQ_1_2 (10'b0001010000), - .CLK_COR_SEQ_1_3 (10'b0000000000), - .CLK_COR_SEQ_1_4 (10'b0000000000), - .CLK_CORRECT_USE ("TRUE"), - .CLK_COR_SEQ_2_ENABLE (4'b1111), - .CLK_COR_SEQ_2_1 (10'b0110111100), - .CLK_COR_SEQ_2_2 (10'b0010110101), - .CLK_COR_SEQ_2_3 (10'b0000000000), - .CLK_COR_SEQ_2_4 (10'b0000000000), - - //----------------------RX Channel Bonding Attributes---------------------- - .CHAN_BOND_KEEP_ALIGN ("FALSE"), - .CHAN_BOND_MAX_SKEW (1), - .CHAN_BOND_SEQ_LEN (1), - .CHAN_BOND_SEQ_1_1 (10'b0000000000), - .CHAN_BOND_SEQ_1_2 (10'b0000000000), - .CHAN_BOND_SEQ_1_3 (10'b0000000000), - .CHAN_BOND_SEQ_1_4 (10'b0000000000), - .CHAN_BOND_SEQ_1_ENABLE (4'b1111), - .CHAN_BOND_SEQ_2_1 (10'b0000000000), - .CHAN_BOND_SEQ_2_2 (10'b0000000000), - .CHAN_BOND_SEQ_2_3 (10'b0000000000), - .CHAN_BOND_SEQ_2_4 (10'b0000000000), - .CHAN_BOND_SEQ_2_ENABLE (4'b1111), - .CHAN_BOND_SEQ_2_USE ("FALSE"), - .FTS_DESKEW_SEQ_ENABLE (4'b1111), - .FTS_LANE_DESKEW_CFG (4'b1111), - .FTS_LANE_DESKEW_EN ("FALSE"), - - //-------------------------RX Margin Analysis Attributes---------------------------- - .ES_CONTROL (6'b000000), - .ES_ERRDET_EN ("FALSE"), - .ES_EYE_SCAN_EN ("TRUE"), - .ES_HORZ_OFFSET (12'h000), - .ES_PMA_CFG (10'b0000000000), - .ES_PRESCALE (5'b00000), - .ES_QUALIFIER (80'h00000000000000000000), - .ES_QUAL_MASK (80'h00000000000000000000), - .ES_SDATA_MASK (80'h00000000000000000000), - .ES_VERT_OFFSET (9'b000000000), - - //-----------------------FPGA RX Interface Attributes------------------------- - .RX_DATA_WIDTH (20), - - //-------------------------PMA Attributes---------------------------- - .OUTREFCLK_SEL_INV (2'b11), - .PMA_RSV (PMA_RSV_IN), - .PMA_RSV2 (16'h2050), - .PMA_RSV3 (2'b00), - .PMA_RSV4 (32'h00000000), - .RX_BIAS_CFG (12'b000000000100), - .DMONITOR_CFG (24'h000A00), - .RX_CM_SEL (2'b11), - .RX_CM_TRIM (3'b010), - .RX_DEBUG_CFG (12'b000000000000), - .RX_OS_CFG (13'b0000010000000), - .TERM_RCAL_CFG (5'b10000), - .TERM_RCAL_OVRD (1'b0), - .TST_RSV (32'h00000000), - .RX_CLK25_DIV (5), - .TX_CLK25_DIV (5), - .UCODEER_CLR (1'b0), - - //-------------------------PCI Express Attributes---------------------------- - .PCS_PCIE_EN ("FALSE"), - - //-------------------------PCS Attributes---------------------------- - .PCS_RSVD_ATTR (PCS_RSVD_ATTR_IN), - - //-----------RX Buffer Attributes------------ - .RXBUF_ADDR_MODE ("FULL"), - .RXBUF_EIDLE_HI_CNT (4'b1000), - .RXBUF_EIDLE_LO_CNT (4'b0000), - .RXBUF_EN ("TRUE"), - .RX_BUFFER_CFG (6'b000000), - .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), - .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), - .RXBUF_RESET_ON_EIDLE ("FALSE"), - .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), - .RXBUFRESET_TIME (5'b00001), - .RXBUF_THRESH_OVFLW (61), - .RXBUF_THRESH_OVRD ("FALSE"), - .RXBUF_THRESH_UNDFLW (4), - .RXDLY_CFG (16'h001F), - .RXDLY_LCFG (9'h030), - .RXDLY_TAP_CFG (16'h0000), - .RXPH_CFG (24'h000000), - .RXPHDLY_CFG (24'h084020), - .RXPH_MONITOR_SEL (5'b00000), - .RX_XCLK_SEL ("RXREC"), - .RX_DDI_SEL (6'b000000), - .RX_DEFER_RESET_BUF_EN ("TRUE"), - - //---------------------CDR Attributes------------------------- - .RXCDR_CFG (72'h03000023ff40080020), - .RXCDR_FR_RESET_ON_EIDLE (1'b0), - .RXCDR_HOLD_DURING_EIDLE (1'b0), - .RXCDR_PH_RESET_ON_EIDLE (1'b0), - .RXCDR_LOCK_CFG (6'b010101), - - //-----------------RX Initialization and Reset Attributes------------------- - .RXCDRFREQRESET_TIME (5'b00001), - .RXCDRPHRESET_TIME (5'b00001), - .RXISCANRESET_TIME (5'b00001), - .RXPCSRESET_TIME (5'b00001), - .RXPMARESET_TIME (5'b00011), - - //-----------------RX OOB Signaling Attributes------------------- - .RXOOB_CFG (7'b0000110), - - //-----------------------RX Gearbox Attributes--------------------------- - .RXGEARBOX_EN ("FALSE"), - .GEARBOX_MODE (3'b000), - - //-----------------------PRBS Detection Attribute----------------------- - .RXPRBS_ERR_LOOPBACK (1'b0), - - //-----------Power-Down Attributes---------- - .PD_TRANS_TIME_FROM_P2 (12'h03c), - .PD_TRANS_TIME_NONE_P2 (8'h19), - .PD_TRANS_TIME_TO_P2 (8'h64), - - //-----------RX OOB Signaling Attributes---------- - .SAS_MAX_COM (64), - .SAS_MIN_COM (36), - .SATA_BURST_SEQ_LEN (4'b1111), - .SATA_BURST_VAL (3'b100), - .SATA_EIDLE_VAL (3'b100), - .SATA_MAX_BURST (8), - .SATA_MAX_INIT (21), - .SATA_MAX_WAKE (7), - .SATA_MIN_BURST (4), - .SATA_MIN_INIT (12), - .SATA_MIN_WAKE (4), - - //-----------RX Fabric Clock Output Control Attributes---------- - .TRANS_TIME_RATE (8'h0E), - - //------------TX Buffer Attributes---------------- - .TXBUF_EN ("TRUE"), - .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), - .TXDLY_CFG (16'h001F), - .TXDLY_LCFG (9'h030), - .TXDLY_TAP_CFG (16'h0000), - .TXPH_CFG (16'h0780), - .TXPHDLY_CFG (24'h084020), - .TXPH_MONITOR_SEL (5'b00000), - .TX_XCLK_SEL ("TXOUT"), - - //-----------------------FPGA TX Interface Attributes------------------------- - .TX_DATA_WIDTH (20), - - //-----------------------TX Configurable Driver Attributes------------------------- - .TX_DEEMPH0 (5'b00000), - .TX_DEEMPH1 (5'b00000), - .TX_EIDLE_ASSERT_DELAY (3'b110), - .TX_EIDLE_DEASSERT_DELAY (3'b100), - .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), - .TX_MAINCURSOR_SEL (1'b0), - .TX_DRIVE_MODE ("DIRECT"), - .TX_MARGIN_FULL_0 (7'b1001110), - .TX_MARGIN_FULL_1 (7'b1001001), - .TX_MARGIN_FULL_2 (7'b1000101), - .TX_MARGIN_FULL_3 (7'b1000010), - .TX_MARGIN_FULL_4 (7'b1000000), - .TX_MARGIN_LOW_0 (7'b1000110), - .TX_MARGIN_LOW_1 (7'b1000100), - .TX_MARGIN_LOW_2 (7'b1000010), - .TX_MARGIN_LOW_3 (7'b1000000), - .TX_MARGIN_LOW_4 (7'b1000000), - - //-----------------------TX Gearbox Attributes-------------------------- - .TXGEARBOX_EN ("FALSE"), - - //-----------------------TX Initialization and Reset Attributes-------------------------- - .TXPCSRESET_TIME (5'b00001), - .TXPMARESET_TIME (5'b00001), - - //-----------------------TX Receiver Detection Attributes-------------------------- - .TX_RXDETECT_CFG (14'h1832), - .TX_RXDETECT_REF (3'b100), - - //--------------------------CPLL Attributes---------------------------- - .CPLL_CFG (24'hBC07DC), - .CPLL_FBDIV (4), - .CPLL_FBDIV_45 (5), - .CPLL_INIT_CFG (24'h00001E), - .CPLL_LOCK_CFG (16'h01E8), - .CPLL_REFCLK_DIV (1), - .RXOUT_DIV (4), - .TXOUT_DIV (4), - .SATA_CPLL_CFG ("VCO_3000MHZ"), - - //------------RX Initialization and Reset Attributes------------- - .RXDFELPMRESET_TIME (7'b0001111), - - //------------RX Equalizer Attributes------------- - .RXLPM_HF_CFG (14'b00000011110000), - .RXLPM_LF_CFG (14'b00000011110000), - .RX_DFE_GAIN_CFG (23'h020FEA), - .RX_DFE_H2_CFG (12'b000000000000), - .RX_DFE_H3_CFG (12'b000001000000), - .RX_DFE_H4_CFG (11'b00011110000), - .RX_DFE_H5_CFG (11'b00011100000), - .RX_DFE_KL_CFG (13'b0000011111110), - .RX_DFE_LPM_CFG (16'h0954), - .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), - .RX_DFE_UT_CFG (17'b10001111000000000), - .RX_DFE_VP_CFG (17'b00011111100000011), - - //-----------------------Power-Down Attributes------------------------- - .RX_CLKMUX_PD (1'b1), - .TX_CLKMUX_PD (1'b1), - - //-----------------------FPGA RX Interface Attribute------------------------- - .RX_INT_DATAWIDTH (0), - - //-----------------------FPGA TX Interface Attribute------------------------- - .TX_INT_DATAWIDTH (0), - - //----------------TX Configurable Driver Attributes--------------- - .TX_QPI_STATUS_EN (1'b0), - - //-----------------------RX Equalizer Attributes-------------------------- - .RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2_IN), - .RX_DFE_XYD_CFG (13'b0001100010000), - - //-----------------------TX Configurable Driver Attributes-------------------------- - .TX_PREDRIVER_MODE (1'b0) - - - ) - gtxe2_i - ( - - //-------------------------------- Channel --------------------------------- - .CFGRESET (tied_to_ground_i), - .CLKRSVD (4'b0000), - .DMONITOROUT (), - .GTRESETSEL (tied_to_ground_i), - .GTRSVD (16'b0000000000000000), - .QPLLCLK (tied_to_ground_i), - .QPLLREFCLK (tied_to_ground_i), - .RESETOVRD (tied_to_ground_i), - //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- - .DRPADDR (tied_to_ground_vec_i[8:0]), - .DRPCLK (tied_to_ground_i), - .DRPDI (tied_to_ground_vec_i[15:0]), - .DRPDO (), - .DRPEN (tied_to_ground_i), - .DRPRDY (), - .DRPWE (tied_to_ground_i), - //----------------------- Channel - Ref Clock Ports ------------------------ - .GTGREFCLK (tied_to_ground_i), - .GTNORTHREFCLK0 (tied_to_ground_i), - .GTNORTHREFCLK1 (tied_to_ground_i), - .GTREFCLK0 (GTREFCLK0_IN), - .GTREFCLK1 (tied_to_ground_i), - .GTREFCLKMONITOR (), - .GTSOUTHREFCLK0 (tied_to_ground_i), - .GTSOUTHREFCLK1 (tied_to_ground_i), - //------------------------------ Channel PLL ------------------------------- - .CPLLFBCLKLOST (CPLLFBCLKLOST_OUT), - .CPLLLOCK (CPLLLOCK_OUT), - .CPLLLOCKDETCLK (CPLLLOCKDETCLK_IN), - .CPLLLOCKEN (tied_to_vcc_i), - .CPLLPD (tied_to_ground_i), - .CPLLREFCLKLOST (CPLLREFCLKLOST_OUT), - .CPLLREFCLKSEL (3'b001), - .CPLLRESET (CPLLRESET_IN), - //----------------------------- Eye Scan Ports ----------------------------- - .EYESCANDATAERROR (EYESCANDATAERROR_OUT), - .EYESCANMODE (tied_to_ground_i), - .EYESCANRESET (tied_to_ground_i), - .EYESCANTRIGGER (tied_to_ground_i), - //---------------------- Loopback and Powerdown Ports ---------------------- - .LOOPBACK (LOOPBACK_IN), - .RXPD (RXPD_IN), - .TXPD (TXPD_IN), - //--------------------------- PCS Reserved Ports --------------------------- - .PCSRSVDIN (16'b0000000000000000), - .PCSRSVDIN2 (5'b00000), - .PCSRSVDOUT (), - //--------------------------- PMA Reserved Ports --------------------------- - .PMARSVDIN (5'b00000), - .PMARSVDIN2 (5'b00000), - //----------------------------- Receive Ports ------------------------------ - .RXQPIEN (tied_to_ground_i), - .RXQPISENN (), - .RXQPISENP (), - .RXSYSCLKSEL (2'b00), - .RXUSERRDY (RXUSERRDY_IN), - //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- - .RXDATAVALID (), - .RXGEARBOXSLIP (tied_to_ground_i), - .RXHEADER (), - .RXHEADERVALID (), - .RXSTARTOFSEQ (), - //--------------------- Receive Ports - 8b10b Decoder ---------------------- - .RX8B10BEN (tied_to_vcc_i), - .RXCHARISCOMMA ({rxchariscomma_float_i,RXCHARISCOMMA_OUT}), - .RXCHARISK ({rxcharisk_float_i,RXCHARISK_OUT}), - .RXDISPERR ({rxdisperr_float_i,RXDISPERR_OUT}), - .RXNOTINTABLE ({rxnotintable_float_i,RXNOTINTABLE_OUT}), - //----------------- Receive Ports - Channel Bonding Ports ------------------ - .RXCHANBONDSEQ (), - .RXCHBONDEN (tied_to_ground_i), - .RXCHBONDI (5'b00000), - .RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]), - .RXCHBONDMASTER (tied_to_ground_i), - .RXCHBONDO (), - .RXCHBONDSLAVE (tied_to_ground_i), - //----------------- Receive Ports - Channel Bonding Ports ----------------- - .RXCHANISALIGNED (), - .RXCHANREALIGN (), - //----------------- Receive Ports - Clock Correction Ports ----------------- - .RXCLKCORCNT (RXCLKCORCNT_OUT), - //------------- Receive Ports - Comma Detection and Alignment -------------- - .RXBYTEISALIGNED (), - .RXBYTEREALIGN (), - .RXCOMMADET (), - .RXCOMMADETEN (tied_to_vcc_i), - .RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_IN), - .RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_IN), - .RXSLIDE (tied_to_ground_i), - //--------------------- Receive Ports - PRBS Detection --------------------- - .RXPRBSCNTRESET (tied_to_ground_i), - .RXPRBSERR (), - .RXPRBSSEL (tied_to_ground_vec_i[2:0]), - //----------------- Receive Ports - RX Data Path interface ----------------- - .GTRXRESET (GTRXRESET_IN), - .RXDATA (rxdata_i), - .RXOUTCLK (RXOUTCLK_OUT), - .RXOUTCLKFABRIC (), - .RXOUTCLKPCS (), - .RXOUTCLKSEL (3'b010), - .RXPCSRESET (RXPCSRESET_IN), - .RXPMARESET (tied_to_ground_i), - .RXUSRCLK (RXUSRCLK_IN), - .RXUSRCLK2 (RXUSRCLK2_IN), - //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- - .RXDFEAGCHOLD (tied_to_ground_i), - .RXDFEAGCOVRDEN (tied_to_ground_i), - .RXDFECM1EN (tied_to_ground_i), - .RXDFELFHOLD (tied_to_ground_i), - .RXDFELFOVRDEN (tied_to_vcc_i), - .RXDFELPMRESET (tied_to_ground_i), - .RXDFETAP2HOLD (tied_to_ground_i), - .RXDFETAP2OVRDEN (tied_to_ground_i), - .RXDFETAP3HOLD (tied_to_ground_i), - .RXDFETAP3OVRDEN (tied_to_ground_i), - .RXDFETAP4HOLD (tied_to_ground_i), - .RXDFETAP4OVRDEN (tied_to_ground_i), - .RXDFETAP5HOLD (tied_to_ground_i), - .RXDFETAP5OVRDEN (tied_to_ground_i), - .RXDFEUTHOLD (tied_to_ground_i), - .RXDFEUTOVRDEN (tied_to_ground_i), - .RXDFEVPHOLD (tied_to_ground_i), - .RXDFEVPOVRDEN (tied_to_ground_i), - .RXDFEVSEN (tied_to_ground_i), - .RXDFEXYDEN (tied_to_ground_i), - .RXDFEXYDHOLD (tied_to_ground_i), - .RXDFEXYDOVRDEN (tied_to_ground_i), - .RXMONITOROUT (), - .RXMONITORSEL (2'b00), - .RXOSHOLD (tied_to_ground_i), - .RXOSOVRDEN (tied_to_ground_i), - //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ - .GTXRXN (GTXRXN_IN), - .GTXRXP (GTXRXP_IN), - .RXCDRFREQRESET (tied_to_ground_i), - .RXCDRHOLD (tied_to_ground_i), - .RXCDRLOCK (RXCDRLOCK_OUT), - .RXCDROVRDEN (tied_to_ground_i), - .RXCDRRESET (tied_to_ground_i), - .RXCDRRESETRSV (tied_to_ground_i), - .RXELECIDLE (RXELECIDLE_OUT), - .RXELECIDLEMODE (2'b10), - .RXLPMEN (tied_to_ground_i), - .RXLPMHFHOLD (tied_to_ground_i), - .RXLPMHFOVRDEN (tied_to_ground_i), - .RXLPMLFHOLD (tied_to_ground_i), - .RXLPMLFKLOVRDEN (tied_to_ground_i), - .RXOOBRESET (tied_to_ground_i), - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- - .RXBUFRESET (RXBUFRESET_IN), - .RXBUFSTATUS (RXBUFSTATUS_OUT), - .RXDDIEN (tied_to_ground_i), - .RXDLYBYPASS (tied_to_vcc_i), - .RXDLYEN (tied_to_ground_i), - .RXDLYOVRDEN (tied_to_ground_i), - .RXDLYSRESET (tied_to_ground_i), - .RXDLYSRESETDONE (), - .RXPHALIGN (tied_to_ground_i), - .RXPHALIGNDONE (), - .RXPHALIGNEN (tied_to_ground_i), - .RXPHDLYPD (tied_to_ground_i), - .RXPHDLYRESET (tied_to_ground_i), - .RXPHMONITOR (), - .RXPHOVRDEN (tied_to_ground_i), - .RXPHSLIPMONITOR (), - .RXSTATUS (), - //---------------------- Receive Ports - RX PLL Ports ---------------------- - .RXRATE (tied_to_ground_vec_i[2:0]), - .RXRATEDONE (), - .RXRESETDONE (RXRESETDONE_OUT), - //------------ Receive Ports - RX Pipe Control for PCI Express ------------- - .PHYSTATUS (), - .RXVALID (), - //--------------- Receive Ports - RX Polarity Control Ports ---------------- - .RXPOLARITY (tied_to_ground_i), - //------------------- Receive Ports - RX Ports for SATA -------------------- - .RXCOMINITDET (), - .RXCOMSASDET (), - .RXCOMWAKEDET (), - //----------------------------- Transmit Ports ----------------------------- - .SETERRSTATUS (tied_to_ground_i), - .TSTIN (20'b11111111111111111111), - .TSTOUT (), - .TXPHDLYTSTCLK (tied_to_ground_i), - .TXPOSTCURSOR (5'b00000), - .TXPOSTCURSORINV (tied_to_ground_i), - .TXPRECURSOR (tied_to_ground_vec_i[4:0]), - .TXPRECURSORINV (tied_to_ground_i), - .TXQPIBIASEN (tied_to_ground_i), - .TXQPISENN (), - .TXQPISENP (), - .TXQPISTRONGPDOWN (tied_to_ground_i), - .TXQPIWEAKPUP (tied_to_ground_i), - .TXSYSCLKSEL (2'b00), - .TXUSERRDY (TXUSERRDY_IN), - //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ - .TXGEARBOXREADY (), - .TXHEADER (tied_to_ground_vec_i[2:0]), - .TXSEQUENCE (tied_to_ground_vec_i[6:0]), - .TXSTARTSEQ (tied_to_ground_i), - //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- - .TX8B10BBYPASS (tied_to_ground_vec_i[7:0]), - .TX8B10BEN (tied_to_vcc_i), - .TXCHARDISPMODE ({tied_to_ground_vec_i[5:0],TXCHARDISPMODE_IN}), - .TXCHARDISPVAL ({tied_to_ground_vec_i[5:0],TXCHARDISPVAL_IN}), - .TXCHARISK ({tied_to_ground_vec_i[5:0],TXCHARISK_IN}), - //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- - .TXBUFSTATUS (TXBUFSTATUS_OUT), - .TXDLYBYPASS (tied_to_vcc_i), - .TXDLYEN (tied_to_ground_i), - .TXDLYHOLD (tied_to_ground_i), - .TXDLYOVRDEN (tied_to_ground_i), - .TXDLYSRESET (tied_to_ground_i), - .TXDLYSRESETDONE (), - .TXDLYUPDOWN (tied_to_ground_i), - .TXPHALIGN (tied_to_ground_i), - .TXPHALIGNDONE (), - .TXPHALIGNEN (tied_to_ground_i), - .TXPHDLYPD (tied_to_ground_i), - .TXPHDLYRESET (tied_to_ground_i), - .TXPHINIT (tied_to_ground_i), - .TXPHINITDONE (), - .TXPHOVRDEN (tied_to_ground_i), - //---------------- Transmit Ports - TX Data Path interface ----------------- - .GTTXRESET (GTTXRESET_IN), - .TXDATA (txdata_i), - .TXOUTCLK (TXOUTCLK_OUT), - .TXOUTCLKFABRIC (TXOUTCLKFABRIC_OUT), - .TXOUTCLKPCS (TXOUTCLKPCS_OUT), - .TXOUTCLKSEL (3'b100), - .TXPCSRESET (TXPCSRESET_IN), - .TXPMARESET (tied_to_ground_i), - .TXUSRCLK (TXUSRCLK_IN), - .TXUSRCLK2 (TXUSRCLK2_IN), - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - .GTXTXN (GTXTXN_OUT), - .GTXTXP (GTXTXP_OUT), - .TXBUFDIFFCTRL (3'b100), - .TXDIFFCTRL (4'b1000), - .TXDIFFPD (tied_to_ground_i), - .TXINHIBIT (tied_to_ground_i), - .TXMAINCURSOR (7'b0000000), - .TXPDELECIDLEMODE (tied_to_ground_i), - .TXPISOPD (tied_to_ground_i), - //--------------------- Transmit Ports - TX PLL Ports ---------------------- - .TXRATE (tied_to_ground_vec_i[2:0]), - .TXRATEDONE (), - .TXRESETDONE (TXRESETDONE_OUT), - //------------------- Transmit Ports - TX PRBS Generator ------------------- - .TXPRBSFORCEERR (tied_to_ground_i), - .TXPRBSSEL (tied_to_ground_vec_i[2:0]), - //------------------ Transmit Ports - TX Polarity Control ------------------ - .TXPOLARITY (tied_to_ground_i), - //--------------- Transmit Ports - TX Ports for PCI Express ---------------- - .TXDEEMPH (tied_to_ground_i), - .TXDETECTRX (tied_to_ground_i), - .TXELECIDLE (TXPD_IN[0]), - .TXMARGIN (tied_to_ground_vec_i[2:0]), - .TXSWING (tied_to_ground_i), - //------------------- Transmit Ports - TX Ports for SATA ------------------- - .TXCOMFINISH (), - .TXCOMINIT (tied_to_ground_i), - .TXCOMSAS (tied_to_ground_i), - .TXCOMWAKE (tied_to_ground_i) - - ); - -endmodule - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v deleted file mode 100755 index de881abbf..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v +++ /dev/null @@ -1,466 +0,0 @@ -//------------------------------------------------------------------------------ -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version : 2.1 -// \ \ Application : 7 Series FPGAs Transceivers Wizard -// / / Filename : gige_sfp_gtwizard_init.v -// /___/ /\ -// \ \ / \ -// \___\/\___\ -// -// Description : This module instantiates the modules required for -// reset and initialisation of the Transceiver -// -// Module GTWIZARD_init -// Generated by Xilinx 7 Series FPGAs Transceivers Wizard -// -// -// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -`timescale 1ns / 1ps -`define DLY #1 - -//***********************************Entity Declaration************************ - -module gige_sfp_GTWIZARD_init # -( - parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE", // Simulation setting for GT SecureIP model - parameter EXAMPLE_SIMULATION = 0, // Set to 1 for simulation - parameter EXAMPLE_USE_CHIPSCOPE = 0 // Set to 1 to use Chipscope to drive resets - -) -( - input SYSCLK_IN, - input SOFT_RESET_IN, - output GT0_TX_FSM_RESET_DONE_OUT, - output GT0_RX_FSM_RESET_DONE_OUT, - input GT0_DATA_VALID_IN, - - //_________________________________________________________________________ - //GT0 (X1Y4) - //____________________________CHANNEL PORTS________________________________ - //----------------------- Channel - Ref Clock Ports ------------------------ - input GT0_GTREFCLK0_IN, - //------------------------------ Channel PLL ------------------------------- - output GT0_CPLLFBCLKLOST_OUT, - output GT0_CPLLLOCK_OUT, - input GT0_CPLLLOCKDETCLK_IN, - input GT0_CPLLRESET_IN, - //----------------------------- Eye Scan Ports ----------------------------- - output GT0_EYESCANDATAERROR_OUT, - //---------------------- Loopback and Powerdown Ports ---------------------- - input [2:0] GT0_LOOPBACK_IN, - input [1:0] GT0_RXPD_IN, - input [1:0] GT0_TXPD_IN, - //----------------------------- Receive Ports ------------------------------ - input GT0_RXUSERRDY_IN, - //--------------------- Receive Ports - 8b10b Decoder ---------------------- - output [1:0] GT0_RXCHARISCOMMA_OUT, - output [1:0] GT0_RXCHARISK_OUT, - output [1:0] GT0_RXDISPERR_OUT, - output [1:0] GT0_RXNOTINTABLE_OUT, - //----------------- Receive Ports - Clock Correction Ports ----------------- - output [1:0] GT0_RXCLKCORCNT_OUT, - //------------- Receive Ports - Comma Detection and Alignment -------------- - input GT0_RXMCOMMAALIGNEN_IN, - input GT0_RXPCOMMAALIGNEN_IN, - //----------------- Receive Ports - RX Data Path interface ----------------- - input GT0_GTRXRESET_IN, - output [15:0] GT0_RXDATA_OUT, - output GT0_RXOUTCLK_OUT, - input GT0_RXUSRCLK_IN, - input GT0_RXUSRCLK2_IN, - //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ - input GT0_GTXRXN_IN, - input GT0_GTXRXP_IN, - output GT0_RXCDRLOCK_OUT, - output GT0_RXELECIDLE_OUT, - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- - input GT0_RXBUFRESET_IN, - output [2:0] GT0_RXBUFSTATUS_OUT, - //---------------------- Receive Ports - RX PLL Ports ---------------------- - output GT0_RXRESETDONE_OUT, - //----------------------------- Transmit Ports ----------------------------- - input GT0_TXUSERRDY_IN, - //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- - input [1:0] GT0_TXCHARDISPMODE_IN, - input [1:0] GT0_TXCHARDISPVAL_IN, - input [1:0] GT0_TXCHARISK_IN, - //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- - output [1:0] GT0_TXBUFSTATUS_OUT, - //---------------- Transmit Ports - TX Data Path interface ----------------- - input GT0_GTTXRESET_IN, - input [15:0] GT0_TXDATA_IN, - output GT0_TXOUTCLK_OUT, - output GT0_TXOUTCLKFABRIC_OUT, - output GT0_TXOUTCLKPCS_OUT, - input GT0_TXUSRCLK_IN, - input GT0_TXUSRCLK2_IN, - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - output GT0_GTXTXN_OUT, - output GT0_GTXTXP_OUT, - //--------------------- Transmit Ports - TX PLL Ports ---------------------- - output GT0_TXRESETDONE_OUT - - - -); - - - -//***********************************Parameter Declarations******************** - - parameter STABLE_CLOCK_PERIOD = 5; //Period of the stable clock driving this state-machine, unit is [ns] - - //Typical CDRLOCK Time is 50,000UI, as per DS183 - parameter RX_CDRLOCK_TIME = (EXAMPLE_SIMULATION == 1) ? 1000 : 50000/1.25; - - integer WAIT_TIME_CDRLOCK = RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; - -//-------------------------- GT Wrapper Wires ------------------------------ - wire gt0_cpllreset_i; - wire gt0_cpllreset_t; - wire gt0_cpllrefclklost_i; - wire gt0_cplllock_i; - wire gt0_txresetdone_i; - wire gt0_rxresetdone_i; - wire gt0_gttxreset_i; - wire gt0_gttxreset_t; - wire gt0_gtrxreset_i; - wire gt0_gtrxreset_t; - wire gt0_txpcsreset_i; - wire gt0_rxpcsreset_i; - wire gt0_txuserrdy_i; - wire gt0_txuserrdy_t; - wire gt0_rxuserrdy_i; - wire gt0_rxuserrdy_t; - - wire gt0_rxdfeagchold_i; - wire gt0_rxdfelfhold_i; - wire gt0_rxlpmlfhold_i; - wire gt0_rxlpmhfhold_i; - - - - -//------------------------------- Global Signals ----------------------------- - wire tied_to_ground_i; - wire tied_to_vcc_i; - - wire gt0_rxoutclk_i; - wire gt0_recclk_stable_i; - wire gt0_rxelecidle_i; - - - integer rx_cdrlock_counter= 0; - reg rx_cdrlocked; - - wire gt0_txresetdone_sync; - wire gt0_rxresetdone_sync; - wire gt0_gttxreset_gt; - wire gt0_gtrxreset_gt; - -//**************************** Main Body of Code ******************************* - // Static signal Assigments - assign tied_to_ground_i = 1'b0; - assign tied_to_vcc_i = 1'b1; - assign gt0_cpllrefclklost_i = 1'b0; - assign gt0_gttxreset_gt = gt0_gttxreset_t || GT0_GTTXRESET_IN; - assign gt0_gtrxreset_gt = gt0_gtrxreset_t || GT0_GTRXRESET_IN; - -gige_sfp_sync_block sync_block_txresetdone - ( - .clk (SYSCLK_IN), - .data_in (gt0_txresetdone_i), - .data_out (gt0_txresetdone_sync) - ); - -gige_sfp_sync_block sync_block_rxresetdone - ( - .clk (SYSCLK_IN), - .data_in (gt0_rxresetdone_i), - .data_out (gt0_rxresetdone_sync) - ); - -// ----------------------------- The GT Wrapper ----------------------------- - - // Use the instantiation template in the example directory to add the GT wrapper to your design. - // In this example, the wrapper is wired up for basic operation with a frame generator and frame - // checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is - // enabled, bonding should occur after alignment. - - - gige_sfp_GTWIZARD # - ( - .WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP) - ) - GTWIZARD_i - ( - - //_____________________________________________________________________ - //_____________________________________________________________________ - //GT0 (X1Y4) - - //----------------------- Channel - Ref Clock Ports ------------------------ - .GT0_GTREFCLK0_IN (GT0_GTREFCLK0_IN), - //------------------------------ Channel PLL ------------------------------- - .GT0_CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT), - .GT0_CPLLLOCK_OUT (gt0_cplllock_i), - .GT0_CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN), - .GT0_CPLLREFCLKLOST_OUT (), - .GT0_CPLLRESET_IN (gt0_cpllreset_i), - //----------------------------- Eye Scan Ports ----------------------------- - .GT0_EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT), - //---------------------- Loopback and Powerdown Ports ---------------------- - .GT0_LOOPBACK_IN (GT0_LOOPBACK_IN), - .GT0_RXPD_IN (GT0_RXPD_IN), - .GT0_TXPD_IN (GT0_TXPD_IN), - //----------------------------- Receive Ports ------------------------------ - .GT0_RXUSERRDY_IN (gt0_rxuserrdy_i), - //--------------------- Receive Ports - 8b10b Decoder ---------------------- - .GT0_RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT), - .GT0_RXCHARISK_OUT (GT0_RXCHARISK_OUT), - .GT0_RXDISPERR_OUT (GT0_RXDISPERR_OUT), - .GT0_RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT), - //----------------- Receive Ports - Clock Correction Ports ----------------- - .GT0_RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT), - //------------- Receive Ports - Comma Detection and Alignment -------------- - .GT0_RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN), - .GT0_RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN), - //----------------- Receive Ports - RX Data Path interface ----------------- - .GT0_GTRXRESET_IN (gt0_gtrxreset_gt), - .GT0_RXDATA_OUT (GT0_RXDATA_OUT), - .GT0_RXOUTCLK_OUT (gt0_rxoutclk_i), - .GT0_RXPCSRESET_IN (gt0_rxpcsreset_i), - .GT0_RXUSRCLK_IN (GT0_RXUSRCLK_IN), - .GT0_RXUSRCLK2_IN (GT0_RXUSRCLK2_IN), - //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ - .GT0_GTXRXN_IN (GT0_GTXRXN_IN), - .GT0_GTXRXP_IN (GT0_GTXRXP_IN), - .GT0_RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT), - .GT0_RXELECIDLE_OUT (gt0_rxelecidle_i), - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- - .GT0_RXBUFRESET_IN (GT0_RXBUFRESET_IN), - .GT0_RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT), - //---------------------- Receive Ports - RX PLL Ports ---------------------- - .GT0_RXRESETDONE_OUT (gt0_rxresetdone_i), - //----------------------------- Transmit Ports ----------------------------- - .GT0_TXUSERRDY_IN (gt0_txuserrdy_i), - //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- - .GT0_TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN), - .GT0_TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN), - .GT0_TXCHARISK_IN (GT0_TXCHARISK_IN), - //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- - .GT0_TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT), - //---------------- Transmit Ports - TX Data Path interface ----------------- - .GT0_GTTXRESET_IN (gt0_gttxreset_gt), - .GT0_TXDATA_IN (GT0_TXDATA_IN), - .GT0_TXOUTCLK_OUT (GT0_TXOUTCLK_OUT), - .GT0_TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT), - .GT0_TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT), - .GT0_TXPCSRESET_IN (gt0_txpcsreset_i), - .GT0_TXUSRCLK_IN (GT0_TXUSRCLK_IN), - .GT0_TXUSRCLK2_IN (GT0_TXUSRCLK2_IN), - //-------------- Transmit Ports - TX Driver and OOB signaling -------------- - .GT0_GTXTXN_OUT (GT0_GTXTXN_OUT), - .GT0_GTXTXP_OUT (GT0_GTXTXP_OUT), - //--------------------- Transmit Ports - TX PLL Ports ---------------------- - .GT0_TXRESETDONE_OUT (gt0_txresetdone_i) - - - - ); - - assign gt0_rxpcsreset_i = tied_to_ground_i; - assign gt0_txpcsreset_i = tied_to_ground_i; - - - - assign GT0_CPLLLOCK_OUT = gt0_cplllock_i; - assign GT0_TXRESETDONE_OUT = gt0_txresetdone_i; - assign GT0_RXRESETDONE_OUT = gt0_rxresetdone_i; - assign GT0_RXELECIDLE_OUT = gt0_rxelecidle_i; - assign GT0_RXOUTCLK_OUT = gt0_rxoutclk_i; - -generate -if (EXAMPLE_USE_CHIPSCOPE == 1) -begin : chipscope - assign gt0_cpllreset_i = GT0_CPLLRESET_IN; - assign gt0_gttxreset_i = GT0_GTTXRESET_IN; - assign gt0_gtrxreset_i = GT0_GTRXRESET_IN; - assign gt0_txuserrdy_i = GT0_TXUSERRDY_IN; - assign gt0_rxuserrdy_i = GT0_RXUSERRDY_IN; -end -endgenerate - -generate -if (EXAMPLE_USE_CHIPSCOPE == 0) -begin : no_chipscope - assign gt0_cpllreset_i = gt0_cpllreset_t; - assign gt0_gttxreset_i = gt0_gttxreset_t; - assign gt0_gtrxreset_i = gt0_gtrxreset_t; - assign gt0_txuserrdy_i = gt0_txuserrdy_t; - assign gt0_rxuserrdy_i = gt0_rxuserrdy_t; -end -endgenerate - - -gige_sfp_TX_STARTUP_FSM # - ( - .GT_TYPE ("GTX"), //GTX or GTH or GTP - .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD), // Period of the stable clock driving this state-machine, unit is [ns] - .RETRY_COUNTER_BITWIDTH (8), - .TX_QPLL_USED ("FALSE"), // the TX and RX Reset FSMs must - .RX_QPLL_USED ("FALSE"), // share these two generic values - .PHASE_ALIGNMENT_MANUAL ("FALSE") // Decision if a manual phase-alignment is necessary or the automatic - // is enough. For single-lane applications the automatic alignment is - // sufficient - ) -gt0_txresetfsm_i - ( - .STABLE_CLOCK (SYSCLK_IN), - .TXUSERCLK (GT0_TXUSRCLK_IN), - .SOFT_RESET (SOFT_RESET_IN), - .QPLLREFCLKLOST (tied_to_ground_i), - .CPLLREFCLKLOST (gt0_cpllrefclklost_i), - .QPLLLOCK (tied_to_vcc_i), - .CPLLLOCK (gt0_cplllock_i), - .TXRESETDONE (gt0_txresetdone_sync), - .MMCM_LOCK (tied_to_vcc_i), - .GTTXRESET (gt0_gttxreset_t), - .MMCM_RESET (), - .QPLL_RESET (), - .CPLL_RESET (gt0_cpllreset_t), - .TX_FSM_RESET_DONE (GT0_TX_FSM_RESET_DONE_OUT), - .TXUSERRDY (gt0_txuserrdy_t), - .RUN_PHALIGNMENT (), - .RESET_PHALIGNMENT (), - .PHALIGNMENT_DONE (tied_to_vcc_i), - .RETRY_COUNTER () - ); - - - - - - -gige_sfp_RX_STARTUP_FSM # - ( - .EXAMPLE_SIMULATION (EXAMPLE_SIMULATION), - .GT_TYPE ("GTX"), //GTX or GTH or GTP - .EQ_MODE ("DFE"), //Rx Equalization Mode - Set to DFE or LPM - .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD), //Period of the stable clock driving this state-machine, unit is [ns] - .RETRY_COUNTER_BITWIDTH (8), - .TX_QPLL_USED ("FALSE"), // the TX and RX Reset FSMs must - .RX_QPLL_USED ("FALSE"), // share these two generic values - .PHASE_ALIGNMENT_MANUAL ("FALSE") // Decision if a manual phase-alignment is necessary or the automatic - // is enough. For single-lane applications the automatic alignment is - // sufficient - ) -gt0_rxresetfsm_i - ( - .STABLE_CLOCK (SYSCLK_IN), - .RXUSERCLK (GT0_RXUSRCLK_IN), - .SOFT_RESET (SOFT_RESET_IN), - .QPLLREFCLKLOST (tied_to_ground_i), - .CPLLREFCLKLOST (gt0_cpllrefclklost_i), - .QPLLLOCK (tied_to_vcc_i), - .CPLLLOCK (gt0_cplllock_i), - .RXRESETDONE (gt0_rxresetdone_sync), - .MMCM_LOCK (tied_to_vcc_i), - .RECCLK_STABLE (gt0_recclk_stable_i), - .RECCLK_MONITOR_RESTART (tied_to_ground_i), - .DATA_VALID (GT0_DATA_VALID_IN), - .TXUSERRDY (tied_to_vcc_i), - .GTRXRESET (gt0_gtrxreset_t), - .MMCM_RESET (), - .QPLL_RESET (), - .CPLL_RESET (), - .RX_FSM_RESET_DONE (GT0_RX_FSM_RESET_DONE_OUT), - .RXUSERRDY (gt0_rxuserrdy_t), - .RUN_PHALIGNMENT (), - .RESET_PHALIGNMENT (), - .PHALIGNMENT_DONE (tied_to_vcc_i), - .RXDFEAGCHOLD (gt0_rxdfeagchold_i), - .RXDFELFHOLD (gt0_rxdfelfhold_i), - .RXLPMLFHOLD (gt0_rxlpmlfhold_i), - .RXLPMHFHOLD (gt0_rxlpmhfhold_i), - .RETRY_COUNTER () - ); - - - - - always @(posedge SYSCLK_IN) - begin - if(gt0_gtrxreset_i) - begin - rx_cdrlocked <= `DLY 1'b0; - rx_cdrlock_counter <= `DLY 0; - end - else if (rx_cdrlock_counter == WAIT_TIME_CDRLOCK) - begin - rx_cdrlocked <= `DLY 1'b1; - rx_cdrlock_counter <= `DLY rx_cdrlock_counter; - end - else - rx_cdrlock_counter <= `DLY rx_cdrlock_counter + 1; - end - -assign gt0_recclk_stable_i = rx_cdrlocked; - - - - - - - -endmodule - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v deleted file mode 100755 index 6367b893a..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v +++ /dev/null @@ -1,680 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version : 2.2 -// \ \ Application : 7 Series FPGAs Transceivers Wizard -// / / Filename : gige_sfp_rx_startup_fsm.v -// /___/ /\ -// \ \ / \ -// \___\/\___\ -// -// -// Description : This module performs RX reset and initialization. -// -// -// -// Module gige_sfp_rx_startup_fsm -// Generated by Xilinx 7 Series FPGAs Transceivers Wizard -// -// -// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -//***************************************************************************** - -`timescale 1ns / 1ps -`define DLY #1 - - -module gige_sfp_RX_STARTUP_FSM # - ( - parameter EXAMPLE_SIMULATION = 0, // Set to 1 for Simulation - parameter GT_TYPE = "GTX", - parameter EQ_MODE = "DFE", //Rx Equalization Mode - Set to DFE or LPM - parameter STABLE_CLOCK_PERIOD = 8, //Period of the stable clock driving this state-machine, unit is [ns] - parameter RETRY_COUNTER_BITWIDTH = 8, - parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must - parameter RX_QPLL_USED = "FALSE", // share these two generic values - - parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic - // is enough. For single-lane applications the automatic alignment is - // sufficient - ) - ( - input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB - //or reference-clock present at startup. - input wire RXUSERCLK, //RXUSERCLK as used in the design - input wire SOFT_RESET, //User Reset, can be pulled any time - input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost - input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost - input wire QPLLLOCK, //Lock Detect from the QPLL of the GT - input wire CPLLLOCK, //Lock Detect from the CPLL of the GT - input wire RXRESETDONE, - input wire MMCM_LOCK, - input wire RECCLK_STABLE, - input wire RECCLK_MONITOR_RESTART, - input wire DATA_VALID, - input wire TXUSERRDY, //TXUSERRDY from GT - output reg GTRXRESET = 1'b0, - output reg MMCM_RESET = 1'b1, - output reg QPLL_RESET = 1'b0, //Reset QPLL (only if RX usese QPLL) - output reg CPLL_RESET = 1'b0, //Reset CPLL (only if RX usese CPLL) - output RX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished. - output reg RXUSERRDY = 1'b0, - output wire RUN_PHALIGNMENT, - input wire PHALIGNMENT_DONE, - output reg RESET_PHALIGNMENT = 1'b0, - output reg RXDFEAGCHOLD = 1'b0, - output reg RXDFELFHOLD = 1'b0, - output reg RXLPMLFHOLD = 1'b0, - output reg RXLPMHFHOLD = 1'b0, - output wire [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of - // Retries it took to get the transceiver up and running - ); - - -//Interdependencies: -// * Timing depends on the frequency of the stable clock. Hence counters-sizes -// are calculated at design-time based on the Generics -// -// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX -// => signal which PLL has been reset -// * - - - - localparam [3:0] - INIT = 4'b0000, - ASSERT_ALL_RESETS = 4'b0001, - RELEASE_PLL_RESET = 4'b0010, - VERIFY_RECCLK_STABLE = 4'b0011, - RELEASE_MMCM_RESET = 4'b0100, - WAIT_RESET_DONE = 4'b0101, - DO_PHASE_ALIGNMENT = 4'b0110, - MONITOR_DATA_VALID = 4'b0111, - FSM_DONE = 4'b1000; - - reg [3:0] rx_state = INIT; - - //This function decides how many clock-cycle need to be waited until - // a time-out occurs for bypassing the TX-Buffer - function [12:0] get_max_wait_bypass; - input manual_mode; - reg [12:0] max_wait_cnt; - begin - if (manual_mode == "TRUE") - max_wait_cnt = 5000; - else - max_wait_cnt = 3100; - get_max_wait_bypass = max_wait_cnt; - end - endfunction - - localparam MMCM_LOCK_CNT_MAX = 1024; - localparam STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration - localparam WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration - localparam WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin - - localparam WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD; //2 ms time-out - localparam WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD; //100 us time-out - localparam WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD; //500 us time-out - localparam WAIT_TIMEOUT_1us = 1000 / STABLE_CLOCK_PERIOD; //1 us time-out - localparam WAIT_TIMEOUT_30us = 30000 / STABLE_CLOCK_PERIOD; //30us time-out - integer WAIT_TIME_ADAPT = (37000000 /1.25)/STABLE_CLOCK_PERIOD; - - reg [7:0] init_wait_count = 0; - reg init_wait_done = 1'b0; - reg pll_reset_asserted = 1'b0; - reg rx_fsm_reset_done_int = 1'b0; - wire rx_fsm_reset_done_sync; - - localparam MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1; - reg [7:0] retry_counter_int = 0; - reg [18:0] time_out_counter = 0; - reg [1:0] recclk_mon_restart_count = 0 ; - reg recclk_mon_count_reset = 0; - - reg reset_time_out = 1'b0; - reg time_out_2ms = 1'b0; //--\Flags that the various time-out points - reg time_tlock_max = 1'b0; //--|have been reached. - reg time_out_500us = 1'b0; //--| - reg time_out_1us = 1'b0; //--| - reg time_out_30us = 1'b0; //--/ - reg check_tlock_max = 1'b0; - - reg [9:0] mmcm_lock_count = 1'b0; - reg mmcm_lock_int = 1'b0; - reg [3:0] mmcm_lock_reclocked = 1'b0; - - reg run_phase_alignment_int = 1'b0; - wire run_phase_alignment_sync; - - localparam MAX_WAIT_BYPASS = get_max_wait_bypass(PHASE_ALIGNMENT_MANUAL);//5000 or 3100, depending on whether manual or automatic - reg [12:0] wait_bypass_count = 0; - reg time_out_wait_bypass = 1'b0; - - integer adapt_count = 0; - reg time_out_adapt = 1'b0; - reg adapt_count_reset = 1'b0; - - //Alias section, signals used within this module mapped to output ports: - assign RETRY_COUNTER = retry_counter_int; - assign RUN_PHALIGNMENT = run_phase_alignment_int; - assign RX_FSM_RESET_DONE = rx_fsm_reset_done_int; - - - always @(posedge STABLE_CLOCK) - begin - // The counter starts running when configuration has finished and - // the clock is stable. When its maximum count-value has been reached, - // the 500 ns from Answer Record 43482 have been passed. - if (init_wait_count == WAIT_MAX) - init_wait_done <= `DLY 1'b1; - else - init_wait_count <= `DLY init_wait_count + 1; - end - - - always @(posedge STABLE_CLOCK) - begin - //This counter monitors, how many retries the CDR Lock Detection - //runs. If during startup too many retries are necessary, the whole - //initialisation-process of the transceivers gets restarted. - if (recclk_mon_count_reset == 1) - recclk_mon_restart_count <= `DLY 0; - else if (RECCLK_MONITOR_RESTART == 1) - begin - if (recclk_mon_restart_count == 3) - recclk_mon_restart_count <= `DLY 0; - else - recclk_mon_restart_count <= `DLY recclk_mon_restart_count + 1; - end - end - -generate - if(EXAMPLE_SIMULATION == 1) - begin - always @(posedge STABLE_CLOCK) - begin - time_out_adapt <= `DLY 1'b1; - end - end - - else - begin - always @(posedge STABLE_CLOCK) - begin - if (adapt_count_reset == 1'b1) - begin - adapt_count <= `DLY 0; - time_out_adapt <= `DLY 1'b0; - end - else - begin - if (adapt_count >= WAIT_TIME_ADAPT) - time_out_adapt <= `DLY 1'b1; - else - adapt_count <= `DLY adapt_count + 1; - end - end - - end -endgenerate - - always @(posedge STABLE_CLOCK) - begin - // One common large counter for generating three time-out signals. - // Intermediate time-outs are derived from calculated values, based - // on the period of the provided clock. - if (reset_time_out == 1) - begin - time_out_counter <= `DLY 0; - time_out_2ms <= `DLY 1'b0; - time_tlock_max <= `DLY 1'b0; - time_out_500us <= `DLY 1'b0; - time_out_1us <= `DLY 1'b0; - time_out_30us <= `DLY 1'b0; - end - else - begin - if (time_out_counter == WAIT_TIMEOUT_2ms) - time_out_2ms <= `DLY 1'b1; - else - time_out_counter <= `DLY time_out_counter + 1; - - if (time_out_counter > WAIT_TLOCK_MAX && check_tlock_max == 1) - begin - time_tlock_max <= `DLY 1'b1; - end - - if (time_out_counter == WAIT_TIMEOUT_500us) - begin - time_out_500us <= `DLY 1'b1; - end - - if (time_out_counter == WAIT_TIMEOUT_1us) - begin - time_out_1us <= `DLY 1'b1; - end - - if (time_out_counter == WAIT_TIMEOUT_30us) - begin - time_out_30us <= `DLY 1'b1; - end - - end - end - - always @(posedge RXUSERCLK) - begin - //The lock-signal from the MMCM is not immediately used but - //enabling a counter. Only when the counter hits its maximum, - //the MMCM is considered as "really" locked. - //The counter avoids that the FSM already starts on only a - //coarse lock of the MMCM (=toggling of the LOCK-signal). - if (MMCM_LOCK == 1'b0) - begin - mmcm_lock_count <= `DLY 0; - mmcm_lock_int <= `DLY 1'b0; - end - else - begin - if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1) - mmcm_lock_count <= `DLY mmcm_lock_count + 1; - else - mmcm_lock_int <= `DLY 1'b1; - end - end - - always @(posedge STABLE_CLOCK) - //Reclocking onto the FSM-clock. - begin - if (MMCM_LOCK == 1'b0) - //The reset-signal is here on purpose. This avoids - //getting the shift-register targetted to an SRL. - //The reason for this is that an SRL will not help - //on the cross-clock domain but "real" Flip-flops will. - - mmcm_lock_reclocked <= `DLY 4'b0000; - else - begin - mmcm_lock_reclocked[3] <= `DLY mmcm_lock_int; - mmcm_lock_reclocked[2:0] <= `DLY mmcm_lock_reclocked[3:1]; - end - end - - gige_sfp_sync_block sync_block_run_phase_alignment - ( - .clk (RXUSERCLK), - .data_in (run_phase_alignment_int), - .data_out (run_phase_alignment_sync) - ); - - gige_sfp_sync_block sync_block_rx_fsm_reset_done - ( - .clk (RXUSERCLK), - .data_in (rx_fsm_reset_done_int), - .data_out (rx_fsm_reset_done_sync) - ); - - always @(posedge RXUSERCLK) - begin - if (run_phase_alignment_sync == 1'b0) - begin - wait_bypass_count <= `DLY 0; - time_out_wait_bypass <= `DLY 1'b0; - end - else if ((run_phase_alignment_sync == 1'b1) && (rx_fsm_reset_done_sync == 1'b0)) - begin - if (wait_bypass_count == MAX_WAIT_BYPASS - 1) - time_out_wait_bypass <= `DLY 1'b1; - else - wait_bypass_count <= `DLY wait_bypass_count + 1; - end - end - - - //FSM for resetting the GTX/GTH/GTP in the 7-series. - //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // - // Following steps are performed: - // 1) After configuration wait for approximately 500 ns as specified in - // answer-record 43482 - // 2) Assert all resets on the GT and on an MMCM potentially connected. - // After that wait until a reference-clock has been detected. - // 3) Release the reset to the GT and wait until the GT-PLL has locked. - // 4) Release the MMCM-reset and wait until the MMCM has signalled lock. - // Also get info from the TX-side which PLL has been reset. - // 5) Wait for the RESET_DONE-signal from the GT. - // 6) Signal to start the phase-alignment procedure and wait for it to - // finish. - // 7) Reset-sequence has successfully run through. Signal this to the - // rest of the design by asserting RX_FSM_RESET_DONE. - - always @(posedge STABLE_CLOCK) - begin - if (SOFT_RESET == 1) - begin - rx_state <= `DLY INIT; - RXUSERRDY <= `DLY 1'b0; - GTRXRESET <= `DLY 1'b0; - MMCM_RESET <= `DLY 1'b1; - rx_fsm_reset_done_int <= `DLY 1'b0; - QPLL_RESET <= `DLY 1'b0; - CPLL_RESET <= `DLY 1'b0; - pll_reset_asserted <= `DLY 1'b0; - reset_time_out <= `DLY 1'b1; - retry_counter_int <= `DLY 0; - run_phase_alignment_int <= `DLY 1'b0; - check_tlock_max <= `DLY 1'b0; - RESET_PHALIGNMENT <= `DLY 1'b1; - recclk_mon_count_reset <= `DLY 1'b1; - adapt_count_reset <= `DLY 1'b1; - RXDFEAGCHOLD <= `DLY 1'b0; - RXDFELFHOLD <= `DLY 1'b0; - RXLPMLFHOLD <= `DLY 1'b0; - RXLPMHFHOLD <= `DLY 1'b0; - end - else - begin - - case (rx_state) - INIT : - begin - //Initial state after configuration. This state will be left after - //approx. 500 ns and not be re-entered. - if (init_wait_done == 1'b1) - rx_state <= `DLY ASSERT_ALL_RESETS; - end - - ASSERT_ALL_RESETS : - begin - //This is the state into which the FSM will always jump back if any - //time-outs will occur. - //The number of retries is reported on the output RETRY_COUNTER. In - //case the transceiver never comes up for some reason, this machine - //will still continue its best and rerun until the FPGA is turned off - //or the transceivers come up correctly. - if (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE") - begin - if (pll_reset_asserted == 1'b0) - begin - QPLL_RESET <= `DLY 1'b1; - pll_reset_asserted <= `DLY 1'b1; - end - else - QPLL_RESET <= `DLY 1'b0; - end - else if (RX_QPLL_USED == "FALSE" && TX_QPLL_USED) - begin - if (pll_reset_asserted == 1'b0) - begin - CPLL_RESET <= `DLY 1'b1; - pll_reset_asserted <= `DLY 1'b1; - end - else - CPLL_RESET <= `DLY 1'b0; - end - RXUSERRDY <= `DLY 1'b0; - GTRXRESET <= `DLY 1'b1; - MMCM_RESET <= `DLY 1'b1; - run_phase_alignment_int <= `DLY 1'b0; - RESET_PHALIGNMENT <= `DLY 1'b1; - check_tlock_max <= `DLY 1'b0; - recclk_mon_count_reset <= `DLY 1'b1; - adapt_count_reset <= `DLY 1'b1; - - if ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE" && QPLLREFCLKLOST == 1'b0 && pll_reset_asserted) || - (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "TRUE" && CPLLREFCLKLOST == 1'b0 && pll_reset_asserted) || - (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b0 ) || - (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b0 ) - ) - begin - rx_state <= `DLY RELEASE_PLL_RESET; - reset_time_out <= `DLY 1'b1; - end - end - - RELEASE_PLL_RESET : - begin - //PLL-Reset of the GTX gets released and the time-out counter - //starts running. - pll_reset_asserted <= `DLY 1'b0; - reset_time_out <= `DLY 1'b0; - - if ((RX_QPLL_USED == "TRUE" && QPLLLOCK == 1'b1) || - (RX_QPLL_USED == "FALSE" && CPLLLOCK == 1'b1)) - begin - rx_state <= `DLY VERIFY_RECCLK_STABLE; - reset_time_out <= `DLY 1'b1; - recclk_mon_count_reset <= `DLY 1'b0; - adapt_count_reset <= `DLY 1'b0; - end - - if (time_out_2ms == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - begin - retry_counter_int <= `DLY retry_counter_int + 1; - end - rx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - VERIFY_RECCLK_STABLE : - begin - //reset_time_out <= `DLY '0'; - //Time-out counter is not released in this state as here the FSM - //does not wait for a certain period of time but checks on the number - //of retries in the CDR PPM detector. - GTRXRESET <= `DLY 1'b0; - if (RECCLK_STABLE == 1'b1) - begin - rx_state <= `DLY RELEASE_MMCM_RESET; - reset_time_out <= `DLY 1'b1; - end - - if (recclk_mon_restart_count == 2) - begin - //If two retries are performed in the CDR "Lock" (=CDR PPM-detector) - //the whole initialisation-sequence gets restarted. - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - begin - retry_counter_int <= `DLY retry_counter_int + 1; - end - rx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - RELEASE_MMCM_RESET : - begin - //Release of the MMCM-reset. Waiting for the MMCM to lock. - reset_time_out <= `DLY 1'b0; - check_tlock_max <= `DLY 1'b1; - - MMCM_RESET <= `DLY 1'b0; - if (mmcm_lock_reclocked[0] == 1'b1) - begin - rx_state <= `DLY WAIT_RESET_DONE; - reset_time_out <= `DLY 1'b1; - end - - if (time_tlock_max == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - begin - retry_counter_int <= `DLY retry_counter_int + 1; - end - rx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - WAIT_RESET_DONE : - begin - //When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY - //If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1' - - if(TXUSERRDY) - RXUSERRDY <= `DLY 1'b1; - - reset_time_out <= `DLY 1'b0; - if (RXRESETDONE == 1'b1) - begin - rx_state <= `DLY DO_PHASE_ALIGNMENT; - reset_time_out <= `DLY 1'b1; - end - - if (time_out_500us == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - begin - retry_counter_int <= `DLY retry_counter_int + 1; - end - rx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - DO_PHASE_ALIGNMENT : - begin - //The direct handling of the signals for the Phase Alignment is done outside - //this state-machine. - RESET_PHALIGNMENT <= `DLY 1'b0; - run_phase_alignment_int <= `DLY 1'b1; - reset_time_out <= `DLY 1'b0; - - if (PHALIGNMENT_DONE == 1'b1) - begin - rx_state <= `DLY MONITOR_DATA_VALID; - reset_time_out <= `DLY 1'b1; - end - - if (time_out_wait_bypass == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - begin - retry_counter_int <= `DLY retry_counter_int + 1; - end - rx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - MONITOR_DATA_VALID : - begin - reset_time_out <= `DLY 1'b0; - - if (DATA_VALID == 1'b0 && time_out_30us == 1'b1) - begin - rx_state <= `DLY ASSERT_ALL_RESETS; - rx_fsm_reset_done_int <= `DLY 1'b0; - end - else if (DATA_VALID == 1'b1) - begin - rx_state <= `DLY FSM_DONE; - rx_fsm_reset_done_int <= `DLY 1'b0; - reset_time_out <= `DLY 1'b1; - end - - end - - FSM_DONE : - begin - reset_time_out <= `DLY 1'b0; - - if (DATA_VALID == 1'b0) - begin - rx_fsm_reset_done_int <= `DLY 1'b0; - reset_time_out <= `DLY 1'b1; - rx_state <= `DLY MONITOR_DATA_VALID; - end - else if(time_out_1us == 1'b1) - rx_fsm_reset_done_int <= `DLY 1'b1; - - if(time_out_adapt) - begin - if((GT_TYPE == "GTX" || GT_TYPE == "GTH") && EQ_MODE == "DFE") - begin - RXDFEAGCHOLD <= `DLY 1'b1; - RXDFELFHOLD <= `DLY 1'b1; - end - else if(GT_TYPE == "GTH" && EQ_MODE == "LPM") - begin - RXLPMHFHOLD <= `DLY 1'b1; - RXLPMLFHOLD <= `DLY 1'b1; - end - end - - - end - - endcase - end - end - -endmodule - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_transceiver.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_transceiver.v deleted file mode 100755 index ffed6c519..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_transceiver.v +++ /dev/null @@ -1,519 +0,0 @@ -//------------------------------------------------------------------------------ -// Title : Top-level Transceiver GT wrapper for Ethernet -// Project : Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE -// File : gige_sfp_transceiver.v -// Author : Xilinx -//------------------------------------------------------------------------------ -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// Description: This is the top-level Transceiver GT wrapper. It -// instantiates the lower-level wrappers produced by -// the Series-7 FPGA Transceiver GT Wrapper Wizard. -//------------------------------------------------------------------------------ - -`timescale 1 ps / 1 ps - -module gige_sfp_transceiver ( - input encommaalign, - input loopback, - input powerdown, - input usrclk, - input usrclk2, - input data_valid, - input independent_clock, - input txreset, - input [7:0] txdata, - input txchardispmode, - input txchardispval, - input txcharisk, - input rxreset, - output reg rxchariscomma, - output reg rxcharisk, - output reg [2:0] rxclkcorcnt, - output reg [7:0] rxdata, - output reg rxdisperr, - output reg rxnotintable, - output reg rxrundisp, - output reg rxbuferr, - output reg txbuferr, - output plllkdet, - output txoutclk, - output rxelecidle, - output txn, - output txp, - input rxn, - input rxp, - input gtrefclk, - input pmareset, - input mmcm_locked, - output resetdone - -); - - - //---------------------------------------------------------------------------- - // Signal declarations - //---------------------------------------------------------------------------- - - wire cplllock; - wire gt_reset_rx; - wire gt_reset_tx; - wire resetdone_tx; - wire resetdone_rx; - wire pcsreset; - reg data_valid_reg; - wire data_valid_reg2; - - wire [2:0] rxbufstatus; - wire [1:0] txbufstatus; - reg [2:0] rxbufstatus_reg; - reg [1:0] txbufstatus_reg; - wire [1:0] rxclkcorcnt_int; - reg txpowerdown_reg = 1'b0; - reg txpowerdown_double = 1'b0; - reg txpowerdown = 1'b0; - wire [1:0] txpowerdown_int; - - // signal used to control sampling during bus width conversions - reg toggle; - - // signals reclocked onto the 62.5MHz userclk source of the GT transceiver - wire encommaalign_int; - wire txreset_int; - wire rxreset_int; - - // Register transmitter signals from the core - reg [7:0] txdata_reg; - reg txchardispmode_reg; - reg txchardispval_reg; - reg txcharisk_reg; - - // Signals for data bus width doubling on the transmitter path from the core - // to the GT transceiver - reg [15:0] txdata_double; - reg [1:0] txchardispmode_double; - reg [1:0] txchardispval_double; - reg [1:0] txcharisk_double; - - // Double width signals reclocked onto the 62.5MHz userclk source of the GT - // transceiver - reg [15:0] txdata_int; - reg [1:0] txchardispmode_int; - reg [1:0] txchardispval_int; - reg [1:0] txcharisk_int; - - // Double width signals output from the GT transceiver on the 62.5MHz clock - // source - wire [1:0] rxchariscomma_int; - wire [1:0] rxcharisk_int; - wire [15:0] rxdata_int; - wire [1:0] rxdisperr_int; - wire [1:0] rxnotintable_int; - wire [1:0] rxrundisp_int; - - // Double width signals reclocked on the GT's 62.5MHz clock source - reg [1:0] rxchariscomma_reg; - reg [1:0] rxcharisk_reg; - reg [15:0] rxdata_reg; - reg [1:0] rxdisperr_reg; - reg [1:0] rxnotintable_reg; - reg [1:0] rxrundisp_reg; - reg rxpowerdown_reg = 1'b0; - - // Double width signals reclocked onto the 125MHz clock source - reg [1:0] rxchariscomma_double; - reg [1:0] rxcharisk_double; - reg [15:0] rxdata_double; - reg [1:0] rxdisperr_double; - reg [1:0] rxnotintable_double; - reg [1:0] rxrundisp_double; - reg rxpowerdown_double = 1'b0; - - reg rxpowerdown = 1'b0; - wire [1:0] rxpowerdown_int; - - - assign txpowerdown_int = {2{txpowerdown}}; - assign rxpowerdown_int = {2{rxpowerdown}}; - - //--------------------------------------------------------------------------- - // The core works from a 125MHz clock source, the GT transceiver fabric - // interface works from a 62.5MHz clock source. The following signals - // sourced by the core therefore need to be reclocked onto the 62.5MHz - // clock - //--------------------------------------------------------------------------- - - // Reclock encommaalign - gige_sfp_reset_sync reclock_encommaalign - ( - .clk (usrclk), - .reset_in (encommaalign), - .reset_out (encommaalign_int) - ); - - - // Reclock txreset - gige_sfp_reset_sync reclock_txreset - ( - .clk (usrclk), - .reset_in (txreset), - .reset_out (txreset_int) - ); - - - // Reclock rxreset - gige_sfp_reset_sync reclock_rxreset - ( - .clk (usrclk), - .reset_in (rxreset), - .reset_out (rxreset_int) - ); - - - //--------------------------------------------------------------------------- - // toggle signal used to control sampling during bus width conversions - //--------------------------------------------------------------------------- - - always @(posedge usrclk2) - begin - if (txreset) begin - toggle <= 1'b0; - end - else begin - toggle <= !toggle; - end - end - - - //--------------------------------------------------------------------------- - // The core works from a 125MHz clock source, the GT transceiver fabric - // interface works from a 62.5MHz clock source. The following signals - // sourced by the core therefore need to be converted to double width, then - // resampled on the GT's 62.5MHz clock - //--------------------------------------------------------------------------- - - // Reclock the transmitter signals - always @(posedge usrclk2) - begin - if (txreset) begin - txdata_reg <= 8'b0; - txchardispmode_reg <= 1'b0; - txchardispval_reg <= 1'b0; - txcharisk_reg <= 1'b0; - txpowerdown_reg <= 1'b0; - end - else begin - txdata_reg <= txdata; - txchardispmode_reg <= txchardispmode; - txchardispval_reg <= txchardispval; - txcharisk_reg <= txcharisk; - txpowerdown_reg <= powerdown; - end - end - - - // Double the data width - always @(posedge usrclk2) - begin - if (txreset) begin - txdata_double <= 16'b0; - txchardispmode_double <= 2'b0; - txchardispval_double <= 2'b0; - txcharisk_double <= 2'b0; - txpowerdown_double <= 1'b0; - end - else begin - if (!toggle) begin - txdata_double[7:0] <= txdata_reg; - txchardispmode_double[0] <= txchardispmode_reg; - txchardispval_double[0] <= txchardispval_reg; - txcharisk_double[0] <= txcharisk_reg; - txdata_double[15:8] <= txdata; - txchardispmode_double[1] <= txchardispmode; - txchardispval_double[1] <= txchardispval; - txcharisk_double[1] <= txcharisk; - end - txpowerdown_double <= txpowerdown_reg; - end - end - - - // Cross the clock domain - always @(posedge usrclk) - begin - txdata_int <= txdata_double; - txchardispmode_int <= txchardispmode_double; - txchardispval_int <= txchardispval_double; - txcharisk_int <= txcharisk_double; - txbufstatus_reg <= txbufstatus; - txpowerdown <= txpowerdown_double; - end - - - - //--------------------------------------------------------------------------- - // The core works from a 125MHz clock source, the GT transceiver fabric - // interface works from a 62.5MHz clock source. The following signals - // sourced by the GT transceiver therefore need to converted to half width - //--------------------------------------------------------------------------- - - // Sample the double width received data from the GT transsciever on the GT's - // 62.5MHz clock - always @(posedge usrclk) - begin - rxchariscomma_reg <= rxchariscomma_int; - rxcharisk_reg <= rxcharisk_int; - rxdata_reg <= rxdata_int; - rxdisperr_reg <= rxdisperr_int; - rxnotintable_reg <= rxnotintable_int; - rxrundisp_reg <= rxrundisp_int; - rxbufstatus_reg <= rxbufstatus; - rxpowerdown <= rxpowerdown_reg; - end - - - // Reclock the double width received data from the GT transsciever onto the - // 125MHz clock source. Both clock domains are frequency related and are - // derived from the same MMCM: the Xilinx tools will accont for this. - - always @(posedge usrclk2) - begin - if (rxreset) begin - rxchariscomma_double <= 2'b0; - rxcharisk_double <= 2'b0; - rxdata_double <= 16'b0; - rxdisperr_double <= 2'b0; - rxnotintable_double <= 2'b0; - rxrundisp_double <= 2'b0; - rxpowerdown_double <= 1'b0; - end - else if (toggle) begin - rxchariscomma_double <= rxchariscomma_reg; - rxcharisk_double <= rxcharisk_reg; - rxdata_double <= rxdata_reg; - rxdisperr_double <= rxdisperr_reg; - rxnotintable_double <= rxnotintable_reg; - rxrundisp_double <= rxrundisp_reg; - end - rxpowerdown_double <= powerdown; - end - - - // Halve the bus width - always @(posedge usrclk2) - begin - if (rxreset) begin - rxchariscomma <= 1'b0; - rxcharisk <= 1'b0; - rxdata <= 8'b0; - rxdisperr <= 1'b0; - rxnotintable <= 1'b0; - rxrundisp <= 1'b0; - rxpowerdown_reg <= 1'b0; - end - else begin - if (!toggle) begin - rxchariscomma <= rxchariscomma_double[0]; - rxcharisk <= rxcharisk_double[0]; - rxdata <= rxdata_double[7:0]; - rxdisperr <= rxdisperr_double[0]; - rxnotintable <= rxnotintable_double[0]; - rxrundisp <= rxrundisp_double[0]; - end - else begin - rxchariscomma <= rxchariscomma_double[1]; - rxcharisk <= rxcharisk_double[1]; - rxdata <= rxdata_double[15:8]; - rxdisperr <= rxdisperr_double[1]; - rxnotintable <= rxnotintable_double[1]; - rxrundisp <= rxrundisp_double[1]; - end - rxpowerdown_reg <= rxpowerdown_double; - end - end - - - //--------------------------------------------------------------------------- - // Instantiate the Series-7 GTX - //--------------------------------------------------------------------------- - // Direct from the Transceiver Wizard output - gige_sfp_GTWIZARD_init # - ( - .EXAMPLE_SIM_GTRESET_SPEEDUP ("TRUE") - ) - gtwizard_inst - ( - .SYSCLK_IN (independent_clock), - .SOFT_RESET_IN (pmareset), - .GT0_TX_FSM_RESET_DONE_OUT (), - .GT0_RX_FSM_RESET_DONE_OUT (), - .GT0_DATA_VALID_IN (data_valid_reg2), - //----------------------- Channel - Ref Clock Ports //------------------ - .GT0_GTREFCLK0_IN (gtrefclk), - //------------------------------ Channel PLL //------------------------- - .GT0_CPLLFBCLKLOST_OUT (), - .GT0_CPLLLOCK_OUT (cplllock), - .GT0_CPLLLOCKDETCLK_IN (1'b1), - //.GT0_CPLLREFCLKLOST_OUT (), - .GT0_CPLLRESET_IN (pmareset), - //----------------------------- Eye Scan Ports //----------------------- - .GT0_EYESCANDATAERROR_OUT (), - //---------------------- Loopback and Powerdown Ports //---------------- - .GT0_LOOPBACK_IN (3'b0), - .GT0_RXPD_IN (rxpowerdown_int), - .GT0_TXPD_IN (txpowerdown_int), - //----------------------------- Receive Ports -------------------------- - .GT0_RXUSERRDY_IN (mmcm_locked), - //--------------------- Receive Ports - 8b10b Decoder //---------------- - .GT0_RXCHARISCOMMA_OUT (rxchariscomma_int), - .GT0_RXCHARISK_OUT (rxcharisk_int), - .GT0_RXDISPERR_OUT (rxdisperr_int), - .GT0_RXNOTINTABLE_OUT (rxnotintable_int), - //----------------- Receive Ports - Clock Correction Ports //----------- - .GT0_RXCLKCORCNT_OUT (rxclkcorcnt_int), - //------------- Receive Ports - Comma Detection and Alignment //-------- - .GT0_RXMCOMMAALIGNEN_IN (encommaalign_int), - .GT0_RXPCOMMAALIGNEN_IN (encommaalign_int), - //----------------- Receive Ports - RX Data Path interface //----------- - .GT0_GTRXRESET_IN (gt_reset_rx), -// .GT0_GTRXRESET_IN (rxreset_int), - .GT0_RXDATA_OUT (rxdata_int), - .GT0_RXOUTCLK_OUT (), - //.GT0_RXPCSRESET_IN (pcsreset), - .GT0_RXUSRCLK_IN (usrclk), - .GT0_RXUSRCLK2_IN (usrclk), - //----- Receive Ports - RX Driver),OOB signalling),Coupling and Eq.),CDR // - .GT0_GTXRXN_IN (rxn), - .GT0_GTXRXP_IN (rxp), - .GT0_RXCDRLOCK_OUT (), - .GT0_RXELECIDLE_OUT (rxelecidle), - //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports //- - .GT0_RXBUFRESET_IN (rxreset_int), - .GT0_RXBUFSTATUS_OUT (rxbufstatus), - //---------------------- Receive Ports - RX PLL Ports //---------------- - .GT0_RXRESETDONE_OUT (resetdone_rx), - //----------------------------- Transmit Ports ------------------------- - .GT0_TXUSERRDY_IN (mmcm_locked), - //-------------- Transmit Ports - 8b10b Encoder Control Ports //-------- - .GT0_TXCHARDISPMODE_IN (txchardispmode_int), - .GT0_TXCHARDISPVAL_IN (txchardispval_int), - .GT0_TXCHARISK_IN (txcharisk_int), - //---------------- Transmit Ports - TX Data Path interface //----------- - .GT0_GTTXRESET_IN (gt_reset_tx), -// .GT0_GTTXRESET_IN (txreset_int), - .GT0_TXDATA_IN (txdata_int), - .GT0_TXOUTCLK_OUT (txoutclk), - .GT0_TXOUTCLKFABRIC_OUT (), - .GT0_TXOUTCLKPCS_OUT (), - //.GT0_TXPCSRESET_IN (pcsreset), - .GT0_TXUSRCLK_IN (usrclk), - .GT0_TXUSRCLK2_IN (usrclk), - //-------------- Transmit Ports - TX Driver and OOB signaling //-------- - .GT0_GTXTXN_OUT (txn), - .GT0_GTXTXP_OUT (txp), - //--------- Transmit Ports - TX Elastic Buffer and Phase Alignment //--- - .GT0_TXBUFSTATUS_OUT (txbufstatus), - //--------------------- Transmit Ports - TX PLL Ports //---------------- - .GT0_TXRESETDONE_OUT (resetdone_tx) - //----------- Transmit Ports - TX Ports for PCI Express ---------------- - //.GT0_TXELECIDLE_IN (txpowerdown) - ); - - - // Hold the transmitter and receiver paths of the GT transceiver in reset - // until the PLL has locked. - assign gt_reset_rx = !cplllock || (rxreset_int & resetdone_rx); - assign gt_reset_tx = !cplllock || (txreset_int & resetdone_tx); - - - // Output the PLL locked status - assign plllkdet = cplllock; - - - // Report overall status for both transmitter and receiver reset done signals - assign resetdone = cplllock ; - - - // reset to PCS part of GT - assign pcsreset = !mmcm_locked; - - // temporary - assign rxrundisp_int = 2'b0; - - - // Decode the GT transceiver buffer status signals - always @(posedge usrclk2) - begin - rxbuferr <= rxbufstatus_reg[2]; - txbuferr <= txbufstatus_reg[1]; - rxclkcorcnt <= {1'b0, rxclkcorcnt_int}; - end - - //--------------------------------------------------------------------------- - // The core works from a 125MHz clock source userclk2, the init statemachines - // work at 200 MHz. - //--------------------------------------------------------------------------- - - // Cross the clock domain - always @(posedge usrclk2) - begin - data_valid_reg <= data_valid; - end - - - gige_sfp_sync_block sync_block_data_valid - ( - .clk (independent_clock), - .data_in (data_valid_reg), - .data_out (data_valid_reg2) - ); - - - -endmodule diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v b/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v deleted file mode 100755 index 5a60ab2ce..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v +++ /dev/null @@ -1,482 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor: Xilinx -// \ \ \/ Version : 2.2 -// \ \ Application : 7 Series FPGAs Transceivers Wizard -// / / Filename : gige_sfp_tx_startup_fsm.v -// /___/ /\ -// \ \ / \ -// \___\/\___\ -// -// -// Description : This module performs TX reset and initialization. -// -// -// -// Module gige_sfp_tx_startup_fsm -// Generated by Xilinx 7 Series FPGAs Transceivers Wizard -// -// -// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -//***************************************************************************** - -`timescale 1ns / 1ps -`define DLY #1 - - -module gige_sfp_TX_STARTUP_FSM # - ( - parameter GT_TYPE = "GTX", - parameter STABLE_CLOCK_PERIOD = 8, // Period of the stable clock driving this state-machine, unit is [ns] - parameter RETRY_COUNTER_BITWIDTH = 8, - parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must - parameter RX_QPLL_USED = "FALSE", // share these two generic values - parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic - // is enough. For single-lane applications the automatic alignment is - // sufficient - ) - ( - input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB - input wire TXUSERCLK, //TXUSERCLK as used in the design - input wire SOFT_RESET, //User Reset, can be pulled any time - input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost - input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost - input wire QPLLLOCK, //Lock Detect from the QPLL of the GT - input wire CPLLLOCK , //Lock Detect from the CPLL of the GT - input wire TXRESETDONE, - input wire MMCM_LOCK, - output reg GTTXRESET = 1'b0, - output reg MMCM_RESET = 1'b1, - output reg QPLL_RESET = 1'b0, //Reset QPLL - output reg CPLL_RESET = 1'b0, //Reset CPLL - output TX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished. - output reg TXUSERRDY = 1'b0, - output RUN_PHALIGNMENT, - output reg RESET_PHALIGNMENT = 1'b0, - input wire PHALIGNMENT_DONE, - - output [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of - // Retries it took to get the transceiver up and running - ); - - -//Interdependencies: -// * Timing depends on the frequency of the stable clock. Hence counters-sizes -// are calculated at design-time based on the Generics -// -// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX -// => signal which PLL has been reset -// * - - - localparam [2:0] - INIT = 3'b000, - ASSERT_ALL_RESETS = 3'b001, - RELEASE_PLL_RESET = 3'b010, - RELEASE_MMCM_RESET = 3'b011, - WAIT_RESET_DONE = 3'b100, - DO_PHASE_ALIGNMENT = 3'b101, - RESET_FSM_DONE = 3'b110; - - reg [2:0] tx_state = INIT; - - //This function decides how many clock-cycle need to be waited until - // a time-out occurs for bypassing the TX-Buffer - function [15:0] get_max_wait_bypass; - input manual_mode; - reg [15:0] max_wait_cnt; - begin - if (manual_mode == "TRUE") - max_wait_cnt = 11000; - else - max_wait_cnt = 55000; - get_max_wait_bypass = max_wait_cnt; - end - endfunction - - parameter MMCM_LOCK_CNT_MAX = 1024; - parameter STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration - parameter WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration - parameter WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin - - parameter WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD;// 2 ms time-out - parameter WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD;//100 us time-out - parameter WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD;//100 us time-out - - reg [7:0] init_wait_count = 0; - reg init_wait_done = 1'b0; - reg pll_reset_asserted = 1'b0; - - reg tx_fsm_reset_done_int = 1'b0; - wire tx_fsm_reset_done_sync; - - parameter MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1; - reg [7:0] retry_counter_int = 0; - reg [18:0] time_out_counter = 0; - - reg reset_time_out = 1'b0; - reg time_out_2ms = 1'b0; //--\Flags that the various time-out points - reg time_tlock_max = 1'b0; //--|have been reached. - reg time_out_500us = 1'b0; //--/ - - reg [9:0] mmcm_lock_count = 0; - reg mmcm_lock_int = 1'b0; - reg [3:0] mmcm_lock_reclocked = 3'b0; - - reg run_phase_alignment_int = 1'b0; - wire run_phase_alignment_sync; - - parameter MAX_WAIT_BYPASS = get_max_wait_bypass(PHASE_ALIGNMENT_MANUAL);//11000 or 55000, depending on whether manual or automatic - reg [15:0] wait_bypass_count = 0; - reg time_out_wait_bypass = 1'b0; - - //Alias section, signals used within this module mapped to output ports: - assign RETRY_COUNTER = retry_counter_int; - assign RUN_PHALIGNMENT = run_phase_alignment_int; - assign TX_FSM_RESET_DONE = tx_fsm_reset_done_int; - - - - always @(posedge STABLE_CLOCK) - begin - // The counter starts running when configuration has finished and - // the clock is stable. When its maximum count-value has been reached, - // the 500 ns from Answer Record 43482 have been passed. - if (init_wait_count == WAIT_MAX) - init_wait_done <= `DLY 1'b1; - else - init_wait_count <= `DLY init_wait_count + 1; - end - - - always @(posedge STABLE_CLOCK) - begin - // One common large counter for generating three time-out signals. - // Intermediate time-outs are derived from calculated values, based - // on the period of the provided clock. - if (reset_time_out == 1'b1) - begin - time_out_counter <= `DLY 0; - time_out_2ms <= `DLY 1'b0; - time_tlock_max <= `DLY 1'b0; - time_out_500us <= `DLY 1'b0; - end - else - begin - if (time_out_counter == WAIT_TIMEOUT_2ms) - time_out_2ms <= `DLY 1'b1; - else - time_out_counter <= `DLY time_out_counter + 1; - - if (time_out_counter == WAIT_TLOCK_MAX) - time_tlock_max <= `DLY 1'b1; - - if (time_out_counter == WAIT_TIMEOUT_500us) - time_out_500us <= `DLY 1'b1; - end - end - - always @(posedge TXUSERCLK) - begin - if (MMCM_LOCK == 1'b0) - begin - mmcm_lock_count <= `DLY 0; - mmcm_lock_int <= `DLY 1'b0; - end - else - begin - if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1) - mmcm_lock_count <= `DLY mmcm_lock_count + 1; - else - mmcm_lock_int <= `DLY 1'b1; - end - end - - always @(posedge STABLE_CLOCK) - //Reclocking onto the FSM-clock. - begin - if (MMCM_LOCK == 1'b0) - //The reset-signal is here on purpose. This avoids - //getting the shift-register targetted to an SRL. - //The reason for this is that an SRL will not help - //on the cross-clock domain but "real" Flip-flops will. - - mmcm_lock_reclocked <= `DLY 4'b0000; - else - begin - mmcm_lock_reclocked[3] <= `DLY mmcm_lock_int; - mmcm_lock_reclocked[2:0] <= `DLY mmcm_lock_reclocked[3:1]; - end - end - - gige_sfp_sync_block sync_block_run_phase_alignment - ( - .clk (TXUSERCLK), - .data_in (run_phase_alignment_int), - .data_out (run_phase_alignment_sync) - ); - - gige_sfp_sync_block sync_block_tx_fsm_reset_done - ( - .clk (TXUSERCLK), - .data_in (tx_fsm_reset_done_int), - .data_out (tx_fsm_reset_done_sync) - ); - - - always @(posedge TXUSERCLK) - begin - if (run_phase_alignment_sync == 1'b0) - begin - wait_bypass_count <= `DLY 0; - time_out_wait_bypass <= `DLY 1'b0; - end - else if (run_phase_alignment_sync == 1'b1 && tx_fsm_reset_done_sync == 1'b0) - begin - if (wait_bypass_count == MAX_WAIT_BYPASS - 1) - time_out_wait_bypass <= `DLY 1'b1; - else - wait_bypass_count <= `DLY wait_bypass_count + 1; - end - end - - //FSM for resetting the GTX/GTH/GTP in the 7-series. - //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // - // Following steps are performed: - // 1) Only for GTX - After configuration wait for approximately 500 ns as specified in - // answer-record 43482 - // 2) Assert all resets on the GT and on an MMCM potentially connected. - // After that wait until a reference-clock has been detected. - // 3) Release the reset to the GT and wait until the GT-PLL has locked. - // 4) Release the MMCM-reset and wait until the MMCM has signalled lock. - // Also signal to the RX-side which PLL has been reset. - // 5) Wait for the RESET_DONE-signal from the GTX. - // 6) Signal to start the phase-alignment procedure and wait for it to - // finish. - // 7) Reset-sequence has successfully run through. Signal this to the - // rest of the design by asserting TX_FSM_RESET_DONE. - - always @(posedge STABLE_CLOCK) - begin - if (SOFT_RESET == 1'b1) - begin - tx_state <= `DLY INIT; - TXUSERRDY <= `DLY 1'b0; - GTTXRESET <= `DLY 1'b0; - MMCM_RESET <= `DLY 1'b1; - tx_fsm_reset_done_int <= `DLY 1'b0; - QPLL_RESET <= `DLY 1'b0; - CPLL_RESET <= `DLY 1'b0; - pll_reset_asserted <= `DLY 1'b0; - reset_time_out <= `DLY 1'b0; - retry_counter_int <= `DLY 0; - run_phase_alignment_int <= `DLY 1'b0; - RESET_PHALIGNMENT <= `DLY 1'b1; - end - else - begin - case (tx_state) - INIT : - begin - //Initial state after configuration. This state will be left after - //approx. 500 ns and not be re-entered. - if (init_wait_done == 1'b1) - tx_state <= `DLY ASSERT_ALL_RESETS; - reset_time_out <= `DLY 1'b1; - end - - ASSERT_ALL_RESETS : - begin - //This is the state into which the FSM will always jump back if any - //time-outs will occur. - //The number of retries is reported on the output RETRY_COUNTER. In - //case the transceiver never comes up for some reason, this machine - //will still continue its best and rerun until the FPGA is turned off - //or the transceivers come up correctly. - if (TX_QPLL_USED == "TRUE") - begin - if (pll_reset_asserted == 1'b0) - begin - QPLL_RESET <= `DLY 1'b1; - pll_reset_asserted <= `DLY 1'b1; - end - else - QPLL_RESET <= `DLY 1'b0; - end - else - begin - if (pll_reset_asserted == 1'b0) - begin - CPLL_RESET <= `DLY 1'b1; - pll_reset_asserted <= `DLY 1'b1; - end - else - CPLL_RESET <= `DLY 1'b0; - end - TXUSERRDY <= `DLY 1'b0; - GTTXRESET <= `DLY 1'b1; - MMCM_RESET <= `DLY 1'b1; - reset_time_out <= `DLY 1'b0; - run_phase_alignment_int <= `DLY 1'b0; - RESET_PHALIGNMENT <= `DLY 1'b1; - - if ((TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b0 && pll_reset_asserted) || - (TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b0 && pll_reset_asserted)) - tx_state <= `DLY RELEASE_PLL_RESET; - - end - - RELEASE_PLL_RESET : - begin - //PLL-Reset of the GTX gets released and the time-out counter - //starts running. - pll_reset_asserted <= `DLY 1'b1; - - if ((TX_QPLL_USED == "TRUE" && QPLLLOCK == 1'b1) || - (TX_QPLL_USED == "FALSE" && CPLLLOCK == 1'b1)) - begin - tx_state <= `DLY RELEASE_MMCM_RESET; - reset_time_out <= `DLY 1'b1; - end - - if (time_out_2ms == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - retry_counter_int <= `DLY retry_counter_int + 1; - tx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - RELEASE_MMCM_RESET : - begin - GTTXRESET <= `DLY 1'b0; - reset_time_out <= `DLY 1'b0; - //Release of the MMCM-reset. Waiting for the MMCM to lock. - MMCM_RESET <= `DLY 1'b0; - if (mmcm_lock_reclocked[0] == 1'b1) - begin - tx_state <= `DLY WAIT_RESET_DONE; - reset_time_out <= `DLY 1'b1; - end - - if (time_tlock_max == 1'b1 && mmcm_lock_reclocked[0] == 1'b0) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - retry_counter_int <= `DLY retry_counter_int + 1; - tx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - WAIT_RESET_DONE : - begin - TXUSERRDY <= `DLY 1'b1; - reset_time_out <= `DLY 1'b0; - if (TXRESETDONE == 1'b1) - begin - tx_state <= `DLY DO_PHASE_ALIGNMENT; - reset_time_out <= `DLY 1'b1; - end - - if (time_out_500us == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - retry_counter_int <= `DLY retry_counter_int + 1; - tx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - DO_PHASE_ALIGNMENT : - begin - //The direct handling of the signals for the Phase Alignment is done outside - //this state-machine. - RESET_PHALIGNMENT <= `DLY 1'b0; - run_phase_alignment_int <= `DLY 1'b1; - reset_time_out <= `DLY 1'b0; - - if (PHALIGNMENT_DONE == 1'b1) - tx_state <= `DLY RESET_FSM_DONE; - - if (time_out_wait_bypass == 1'b1) - begin - if (retry_counter_int == MAX_RETRIES) - // If too many retries are performed compared to what is specified in - // the generic, the counter simply wraps around. - retry_counter_int <= `DLY 0; - else - retry_counter_int <= `DLY retry_counter_int + 1; - tx_state <= `DLY ASSERT_ALL_RESETS; - end - end - - RESET_FSM_DONE : - begin - reset_time_out <= `DLY 1'b1; - tx_fsm_reset_done_int <= `DLY 1'b1; - end - - endcase - end - end - -endmodule - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/gig_eth_pcs_pma_readme.txt b/fpga/usrp3/top/x300/coregen/gige_sfp/gig_eth_pcs_pma_readme.txt deleted file mode 100644 index 37e63a577..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/gig_eth_pcs_pma_readme.txt +++ /dev/null @@ -1,276 +0,0 @@ - -CHANGE LOG for Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v11.4 - -Release Date: July 25, 2012 --------------------------------------------------------------------------------- - - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - -1. INTRODUCTION - - This file contains the change log for all released versions of the Xilinx - LogiCORE IP core Ethernet 1000BASE-X PCS/PMA or SGMII. - - For the latest core updates, see the product page at: - - http://www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm - - For installation instructions for this release, please go to: - - www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - - For system requirements, see: - - www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - - -2. DEVICE SUPPORT - - 2.1. ISE - - The following device families are supported by the core for this release: - - Virtex-7 devices - Virtex-7 - Virtex-7 HT/XT - - Kintex-7 devices - Kintex-7 - - Artix-7 devices - Artix-7 - - Zynq-7000 devices - Zynq-7000 - - Virtex-6 devices - Virtex-6 CXT/LXT/SXT/HXT - Virtex-6 Lower Power (-1L) LXT/SXT - Defense Grade Virtex-6Q (XQ) LXT/SXT - - Spartan-6 devices - Spartan-6 LX/LXT - Defense Grade Spartan-6Q LX/LXT - - All Virtex-5 devices - - Virtex-4 devices - Virtex-4 LX/SX/FX - - Spartan-3 device families - Spartan-3 - Spartan-3A and Spartan-3AN - - Spartan-3A DSP - - Spartan-3E - - - 2.2. VIVADO - - - The following device families are supported by the core for this release: - - Virtex-7 devices - Virtex-7 - Virtex-7 HT/XT - - Kintex-7 devices - Kintex-7 - - Artix-7 devices - Artix-7 - - Zynq-7000 devices - Zynq-7000 - - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - v11.4 - - - ISE 14.2 software support - - Support for Zynq Devices - - - v11.3 - - - ISE 14.1 software support - - Support for Artix7 Devices - - Support for Virtex-7 HT Devices - - v11.2 - - - ISE 13.4 software support - - Added programability through configuration vector - - - v11.1 - - - ISE 13.1 software support - - Updated status vector - - SGMII PHY mode - - Support for Kintex7 Devices - - Support for Virtex7 Devices - - - 3.2 Vivado - - v11.4 - - Vivado 2012.2 software support - - Initial public release - - Block level user editable logic delivered as part of the core - - - -4. RESOLVED ISSUES - - 4.1 ISE - - The following issues are resolved in the indicated IP versions: - - v11.4 - - None - - v11.3 - - AR: 45676 - - AR: 46123 - - v11.2 - - AR: 42672 - - AR: 36961 - - AR: 42842 - - AR: 43421 - - AR: 43482 - - v11.1 - - AR: 36957 - - AR: 36961 - - AR: 35681 - - - 4.2 Vivado - - v11.4 - - None - - -5. KNOWN ISSUES & LIMITATIONS - - - - For a comprehensive listing of Known Issues for this core, please see the IP - Release Notes Guide, - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - - -6. TECHNICAL SUPPORT & FEEDBACK - - To obtain technical support, create a WebCase at www.xilinx.com/support. - Questions are routed to a team with expertise using this product. - Feedback on this IP core may also be submitted under the "Leave Feedback" - menu item in Vivado/PlanAhead. - - Xilinx provides technical support for use of this product when used - according to the guidelines described in the core documentation, and - cannot guarantee timing, functionality, or support of this product for - designs that do not follow specified guidelines. - - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -07/25/2012 Xilinx, Inc. 11.4 ISE 14.2 and Vivado 2012.2. - Support for Zynq Devices. Sync LVDS Solution -04/24/2012 Xilinx, Inc. 11.3 ISE 14.1, Artix-7 and Vivado 2012.1 support -01/18/2012 Xilinx, Inc. 11.2 ISE 13.4 Support -09/06/2011 Xilinx, Inc. 11.1 Rev 1 Patch release for ISE 13.1 -03/01/2011 Xilinx, Inc. 11.1 ISE 13.1 and Virtex-7 / Kintex-7 support -07/30/2010 Xilinx, Inc. 10.5 Rev 1 Patch release for ISE 12.2 -07/23/2010 Xilinx, Inc. 10.5 ISE 12.2 support and Virtex-6 LVDS I/O -04/19/2010 Xilinx, Inc. 10.4 Release for ISE 12.1 -03/09/2010 Xilinx, Inc. 10.3 Rev 1 Patch release for ISE 11.5 -09/16/2009 Xilinx, Inc. 10.3 11.3, Virtex-6 HXT and Lower Power support -06/24/2009 Xilinx, Inc. 10.2 Release for ISE 11.2 and Spartan-6 support -04/27/2009 Xilinx, Inc. 10.1 Release for ISE 11.1 -03/24/2008 Xilinx, Inc. 9.1 Release for ISE 10.1 -08/15/2007 Xilinx, Inc. 9.0 Release for 9.2i -04/02/2007 Xilinx, Inc. 8.1 Rev 1 Spartan-3A DSP support -03/05/2007 Xilinx, Inc. 8.1 Release for ISE 9.1i -10/26/2006 Xilinx, Inc. 8.0 Release for Virtex-5 and Spartan-3A -07/19/2006 Xilinx, Inc. 7.1 Release for ISE 8.2i -05/22/2006 Xilinx, Inc. 7.0 Rev 1 Virtex-4 FX CES4 update -01/18/2006 Xilinx, Inc. 7.0 Release for ISE 8.1i -06/24/2005 Xilinx, Inc. 6.0 patch1 Patch release -05/12/2005 Xilinx, Inc. 6.0 Release for ISE 7.1i -09/30/2004 Xilinx, Inc. 5.0 Release for ISE 6.3i -================================================================================ - - -8. LEGAL DISCLAIMER - - (c) Copyright 2004 - 2012 Xilinx, Inc. All rights reserved. - - This file contains confidential and proprietary information - of Xilinx, Inc. and is protected under U.S. and - international copyright and other intellectual property - laws. - - DISCLAIMER - This disclaimer is not a license and does not grant any - rights to the materials distributed herewith. Except as - otherwise provided in a valid license issued to you by - Xilinx, and to the maximum extent permitted by applicable - law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - (2) Xilinx shall not be liable (whether in contract or tort, - including negligence, or under any other theory of - liability) for any loss or damage of any kind or nature - related to, arising under or in connection with these - materials, including for any direct, or any indirect, - special, incidental, or consequential loss or damage - (including loss of data, profits, goodwill, or any type of - loss or damage suffered as a result of any action brought - by a third party) even if such damage or loss was - reasonably foreseeable or Xilinx had been advised of the - possibility of the same. - - CRITICAL APPLICATIONS - Xilinx products are not designed or intended to be fail- - safe, or for use in any application requiring fail-safe - performance, such as life-support or safety devices or - systems, Class III medical devices, nuclear facilities, - applications related to the deployment of airbags, or any - other applications that could lead to death, personal - injury, or severe property or environmental damage - (individually and collectively, "Critical - Applications"). Customer assumes the sole risk and - liability of any use of Xilinx products in Critical - Applications, subject only to applicable laws and - regulations governing limitations on product liability. - - THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - PART OF THIS FILE AT ALL TIMES. - - - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/example_design_xst.xcf b/fpga/usrp3/top/x300/coregen/gige_sfp/implement/example_design_xst.xcf deleted file mode 100755 index 2f5065d45..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/example_design_xst.xcf +++ /dev/null @@ -1,14 +0,0 @@ -# RLOCs for reset_sync / sync_block logic -#------------------------------------------------------ -# To keep the FF pairs in the same slice to minimise routing delay between them - -BEGIN MODEL sync_block - INST "data_sync" rloc = X0Y0; - INST "data_sync_reg" rloc = X0Y0; -END; - -BEGIN MODEL reset_sync - INST "reset_sync1" rloc = X0Y0; - INST "reset_sync2" rloc = X0Y0; -END; - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/implement.bat b/fpga/usrp3/top/x300/coregen/gige_sfp/implement/implement.bat deleted file mode 100755 index 5c98b2df2..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/implement.bat +++ /dev/null @@ -1,37 +0,0 @@ - -REM Clean up the results directory -rmdir /S /Q results -mkdir results - -REM Synthesize the Example Design -rem Synthesize the VHDL Wrapper Files -echo 'Synthesizing the example design with XST'; -xst -ifn xst.scr -copy gige_sfp_example_design.ngc .\results\ - -REM Copy the netlist generated by Coregen -echo 'Copy files from the netlist directory to the results directory' -copy ..\..\gige_sfp.ngc results - -REM Copy the constraints files generated by Coregen -echo 'Copy files from constraints directory to results directory' -copy ..\example_design\gige_sfp_example_design.ucf results\ - -cd results -echo 'Running ngdbuild' -ngdbuild gige_sfp_example_design - -echo 'Running map' -map -ol high -timing gige_sfp_example_design -o mapped.ncd - -echo 'Running par' -par -ol high -w mapped.ncd routed.ncd mapped.pcf - -echo 'Running trce' -trce -u -e 10 routed -o routed mapped.pcf - -echo 'Running design through bitgen' -bitgen -w routed.ncd routed mapped.pcf -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gige_sfp_example_design -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/implement.sh b/fpga/usrp3/top/x300/coregen/gige_sfp/implement/implement.sh deleted file mode 100755 index add195269..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/implement.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh - -# Clean up the results directory -rm -rf results -mkdir results - -# Synthesize the Example Design -echo 'Synthesizing the example design with XST'; -xst -ifn xst.scr -cp gige_sfp_example_design.ngc ./results/ - -# Copy the netlist generated by Coregen -echo 'Copying files from the netlist directory to the results directory' -cp ../../gige_sfp.ngc results/ - -# Copy the constraints files generated by Coregen -echo 'Copying files from constraints directory to results directory' -cp ../example_design/gige_sfp_example_design.ucf results/ - -cd results -echo 'Running ngdbuild' -ngdbuild gige_sfp_example_design - -echo 'Running map' -map -ol high -timing gige_sfp_example_design -o mapped.ncd - -echo 'Running par' -par -ol high -w mapped.ncd routed.ncd mapped.pcf - -echo 'Running trce' -trce -u -e 10 routed -o routed mapped.pcf - -echo 'Running design through bitgen' -bitgen -w routed.ncd routed mapped.pcf -g UnconstrainedPins:Allow - -echo 'Running netgen to create gate level Verilog model' -netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gige_sfp_example_design -w -sdf_anno false routed.ncd routed.v - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/xst.prj b/fpga/usrp3/top/x300/coregen/gige_sfp/implement/xst.prj deleted file mode 100755 index 92455f282..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/xst.prj +++ /dev/null @@ -1,13 +0,0 @@ -verilog work ../example_design/gige_sfp_sync_block.v -verilog work ../example_design/gige_sfp_reset_sync.v -verilog work ../example_design/transceiver/gige_sfp_gtwizard_gt.v -verilog work ../example_design/transceiver/gige_sfp_gtwizard.v -verilog work ../example_design/transceiver/gige_sfp_tx_startup_fsm.v -verilog work ../example_design/transceiver/gige_sfp_rx_startup_fsm.v -verilog work ../example_design/transceiver/gige_sfp_gtwizard_init.v -verilog work ../example_design/transceiver/gige_sfp_transceiver.v -verilog work ../example_design/gige_sfp_tx_elastic_buffer.v -verilog work ../example_design/gige_sfp_mod.v -verilog work ../example_design/gige_sfp_block.v -verilog work ../example_design/gige_sfp_example_design.v - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/xst.scr b/fpga/usrp3/top/x300/coregen/gige_sfp/implement/xst.scr deleted file mode 100755 index 7cd61c93a..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/implement/xst.scr +++ /dev/null @@ -1,12 +0,0 @@ -# XST synthesis script for GPCS_PMA core. -set -tmpdir . -set -xsthdpdir ./xst -run --ifmt mixed --top gige_sfp_example_design --ofn gige_sfp_example_design --p kintex7 --uc example_design_xst.xcf --ifn xst.prj --iobuf YES - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/demo_tb.v b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/demo_tb.v deleted file mode 100755 index 26feda23c..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/demo_tb.v +++ /dev/null @@ -1,332 +0,0 @@ -//------------------------------------------------------------------------------ -// File : demo_tb.v -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// Description: This testbench will exercise the ports of the Ethernet -// 1000BASE-X PCS/PMA core's example design to perform the following -// operations: -// -//---------------- -// Configuration -//---------------- -// The core will be reset, then Auto-Negotiation (if present) will -// be disabled and and the core will be taken out of the Isolate -// state. -// -//---------------- -// Transmitter -//---------------- -// Four frames are generated by the Tx Stimulus and pushed into the -// GMII transmitter. -// -// The PHY side transmitter interface data is captured, 8B10B decoded -// and the Tx Monitor checks that the captured data matches that -// injected. -// -//---------------- -// Receiver -//---------------- -// Four frames are generated by the Rx Stimulus, 8B10B encoded and -// pushed into the PHY side receiver interface. -// -// The GMII side receiver interface data is captured and the -// Rx Monitor checks that the captured data matches that injected. -// -// -//---------------------------------------------------------------------- -// Demonstration Test Fixture | -// | -// | -// -------------------------- | -// | Example Design | | -// | (DUT) | | -// | | | -// | | | -// | | | -// Tx | | 8B10B decode, Tx | -// Generate -------> --------> Monitor | -// Frames | | Frames | -// |GMII PHY | | -// | I/F I/F | | -// | | | -// | | | -// | | | -// Rx | | 8B10B encode, Rx | -// Monitor <-------- <-------- Generate | -// Frames | | Frames | -// | | | -// ------------^------------- | -// | | -// | | -// Stimulate | -// MDIO I/F | -// (if present) | -// | -//---------------------------------------------------------------------- - -`timescale 1 ps/1 ps - - - -// This module is the demonstration testbench -module demo_tb; - - - //---------------------------------------------------------------------------- - // testbench signals - //---------------------------------------------------------------------------- - - // testbench control semaphores - reg configuration_finished; - wire tx_monitor_finished; - wire rx_monitor_finished; - wire simulation_finished; - - - //---------------------------------------------------------------------------- - // DUT signals - //---------------------------------------------------------------------------- - - // An independent clock source used as the reference clock for an - // IDELAYCTRL (if present) and for the main GT transceiver reset logic. - // This example design assumes that this is of frequency 200MHz. - reg independent_clock; - - // System Reset - reg reset; - - // Transceiver Interface - //---------------------- - reg gtrefclk_p; - reg gtrefclk_n; - wire txp; - wire txn; - wire rxp; - wire rxn; - - // GMII Interface - //--------------- - wire gmii_tx_clk; - wire gmii_rx_clk; - wire [7:0] gmii_txd; - wire gmii_tx_en; - wire gmii_tx_er; - wire [7:0] gmii_rxd; - wire gmii_rx_dv; - wire gmii_rx_er; - - // Management: Alternative to MDIO Interface - //------------------------------------------ - reg [4:0] configuration_vector; - - wire signal_detect; - wire [15:0] status_vector; - - - - //---------------------------------------------------------------------------- - // Create clock sources - //---------------------------------------------------------------------------- - - // An independent clock source used as the reference clock for an - // IDELAYCTRL (if present) and for the main GT transceiver reset logic. - // This testbench uses the frequency of 200MHz. - initial - begin - independent_clock <= 1'b0; - forever - begin - independent_clock <= 1'b0; - #2500; - independent_clock <= 1'b1; - #2500; - end - end - - - - // Create the transceiver Reference clock (125 MHz) - initial - begin - gtrefclk_p <= 1'b0; - gtrefclk_n <= 1'b1; - forever - begin - gtrefclk_p <= 1'b0; - gtrefclk_n <= 1'b1; - #4000; - gtrefclk_p <= 1'b1; - gtrefclk_n <= 1'b0; - #4000; - end - end - - - - //---------------------------------------------------------------------------- - // Wire up Device Under Test - //---------------------------------------------------------------------------- - gige_sfp_example_design dut - ( - .independent_clock (independent_clock), - .gtrefclk_p (gtrefclk_p), - .gtrefclk_n (gtrefclk_n), - .txp (txp), - .txn (txn), - .rxp (rxp), - .rxn (rxn), - .gmii_tx_clk (gmii_tx_clk), - .gmii_rx_clk (gmii_rx_clk), - .gmii_txd (gmii_txd), - .gmii_tx_en (gmii_tx_en), - .gmii_tx_er (gmii_tx_er), - .gmii_rxd (gmii_rxd), - .gmii_rx_dv (gmii_rx_dv), - .gmii_rx_er (gmii_rx_er), - .configuration_vector (configuration_vector), - .status_vector (status_vector), - .reset (reset), - .signal_detect (signal_detect) - ); - - - - //---------------------------------------------------------------------------- - // Instantiate a Stimulus module for the core - //---------------------------------------------------------------------------- - stimulus_tb stimulus - ( - .txp (txp), - .txn (txn), - .rxp (rxp), - .rxn (rxn), - - .gmii_tx_clk (gmii_tx_clk), - .gmii_rx_clk (gmii_rx_clk), - .gmii_txd (gmii_txd), - .gmii_tx_en (gmii_tx_en), - .gmii_tx_er (gmii_tx_er), - .gmii_rxd (gmii_rxd), - .gmii_rx_dv (gmii_rx_dv), - .gmii_rx_er (gmii_rx_er), - - .configuration_finished (configuration_finished), - .tx_monitor_finished (tx_monitor_finished), - .rx_monitor_finished (rx_monitor_finished) - ); - - - - //---------------------------------------------------------------------------- - // Simulate that PMD sublayer has detected and optical input. - //---------------------------------------------------------------------------- - assign signal_detect = 1'b1; - - - - - //---------------------------------------------------------------------------- - // Set the configuration for the core. Any of the bits within - // "configuration_vector" can be changed dynamically. - // The core is then reset - //---------------------------------------------------------------------------- - initial - begin : p_configuration - $display("** Note: Timing checks are not valid"); - - configuration_finished <= 0; - - configuration_vector[1:0] <= 2'h0; // Disable Loopback - configuration_vector[2] <= 1'b0; // Disable POWERDOWN - configuration_vector[3] <= 1'b0; // Disable ISOLATE - configuration_vector[4] <= 1'b0; // Enable Auto-Neg - - // reset the core - $display("Resetting core..."); - reset <= 1'b1; - #1000000 - reset <= 1'b0; - - // wait for core to obtain synchronisation - wait (status_vector[1] == 1); - #20000000 - - @(posedge gtrefclk_p) - - configuration_finished <= 1; - end // p_configuration - - - - //---------------------------------------------------------------------------- - // End the simulation. - //---------------------------------------------------------------------------- - - assign simulation_finished = tx_monitor_finished & rx_monitor_finished; - - initial - begin : p_end_simulation - fork: sim_in_progress - @(posedge simulation_finished) disable sim_in_progress; - #200000000 disable sim_in_progress; - join - if (simulation_finished) - #1000000 - $display("Simulation Complete."); - else - $display("** Error: Testbench timed out"); - $stop; - end // p_end_simulation - - - -endmodule - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_mti.do b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_mti.do deleted file mode 100755 index f6279f796..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,28 +0,0 @@ -vlib work -vmap work work - -echo "Compiling Core Simulation Models" -vlog -work work ../../../gige_sfp.v - -echo "Compiling Example Design" -vlog -work work \ -../../example_design/gige_sfp_sync_block.v \ -../../example_design/gige_sfp_reset_sync.v \ -../../example_design/transceiver/gige_sfp_gtwizard_gt.v \ -../../example_design/transceiver/gige_sfp_gtwizard.v \ -../../example_design/transceiver/gige_sfp_tx_startup_fsm.v \ -../../example_design/transceiver/gige_sfp_rx_startup_fsm.v \ -../../example_design/transceiver/gige_sfp_gtwizard_init.v \ -../../example_design/transceiver/gige_sfp_transceiver.v \ -../../example_design/gige_sfp_tx_elastic_buffer.v \ -../../example_design/gige_sfp_block.v \ -../../example_design/gige_sfp_example_design.v - -echo "Compiling Test Bench" -vlog -work work -novopt ../stimulus_tb.v ../demo_tb.v - -echo "Starting simulation" -vsim -voptargs="+acc" -L unisims_ver -L secureip -t ps work.demo_tb work.glbl -do wave_mti.do -run -all - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_ncsim.sh deleted file mode 100755 index 27bc85f42..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh -mkdir work - -echo "Compiling Core Simulation Models" -ncvlog -work work ../../../gige_sfp.v - -echo "Compiling Example Design" -ncvlog -work work \ -../../example_design/gige_sfp_sync_block.v \ -../../example_design/gige_sfp_reset_sync.v \ -../../example_design/transceiver/gige_sfp_gtwizard_gt.v \ -../../example_design/transceiver/gige_sfp_gtwizard.v \ -../../example_design/transceiver/gige_sfp_tx_startup_fsm.v \ -../../example_design/transceiver/gige_sfp_rx_startup_fsm.v \ -../../example_design/transceiver/gige_sfp_gtwizard_init.v \ -../../example_design/transceiver/gige_sfp_transceiver.v \ -../../example_design/gige_sfp_tx_elastic_buffer.v \ -../../example_design/gige_sfp_block.v \ -../../example_design/gige_sfp_example_design.v - -echo "Compiling Test Bench" -ncvlog -work work ../stimulus_tb.v ../demo_tb.v - -echo "Elaborating design" -ncelab -access +rw work.demo_tb glbl - -echo "Starting simulation" -ncsim -gui work.demo_tb -input @"simvision -input wave_ncsim.sv" diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_vcs.sh deleted file mode 100755 index 2e3d2407d..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -rm -rf simv* csrc DVEfiles AN.DB - -echo "Compiling Core Simulation Models" -vlogan +v2k \ -../../../gige_sfp.v \ -../../example_design/gige_sfp_sync_block.v \ -../../example_design/gige_sfp_reset_sync.v \ -../../example_design/transceiver/gige_sfp_gtwizard_gt.v \ -../../example_design/transceiver/gige_sfp_gtwizard.v \ -../../example_design/transceiver/gige_sfp_tx_startup_fsm.v \ -../../example_design/transceiver/gige_sfp_rx_startup_fsm.v \ -../../example_design/transceiver/gige_sfp_gtwizard_init.v \ -../../example_design/transceiver/gige_sfp_transceiver.v \ -../../example_design/gige_sfp_tx_elastic_buffer.v \ -../../example_design/gige_sfp_block.v \ -../../example_design/gige_sfp_example_design.v \ -../stimulus_tb.v \ -../demo_tb.v - -echo "Elaborating design" -vcs +vcs+lic+wait \ - -debug \ - demo_tb glbl - -echo "Starting simulation" -./simv -ucli -i ucli_commands.key - -dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/ucli_commands.key b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/ucli_commands.key deleted file mode 100755 index 7bf393aa6..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,4 +0,0 @@ -call {$vcdpluson} -run -call {$vcdplusclose} -quit diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/vcs_session.tcl deleted file mode 100755 index 3588fc66c..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,27 +0,0 @@ -gui_open_window Wave -gui_list_select -id Hier.1 { glbl demo_tb } -gui_sg_create PCS_PMA_group -gui_list_add_group -id Wave.1 {PCS_PMA_group} - -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Test_semaphores } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Rx_Stimulus } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Tx_Monitor } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Transceiver_Rx_Signals } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Transceiver_Tx_Signals } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Rx_GMII_Signals } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Tx_GMII_Signals } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { Management_Signals } -gui_list_add_divider -id Wave.1 -after PCS_PMA_group { System_Signals } -gui_list_add -id Wave.1 -after System_Signals {{demo_tb.gtrefclk_p} {demo_tb.gtrefclk_n}} -gui_list_add -id Wave.1 -after System_Signals {demo_tb.signal_detect} -gui_list_add -id Wave.1 -after Management_Signals {{demo_tb.status_vector}} -gui_list_add -id Wave.1 -after Tx_GMII_Signals {{demo_tb.gmii_txd} {demo_tb.gmii_tx_en} {demo_tb.gmii_tx_er}} -gui_list_add -id Wave.1 -after Rx_GMII_Signals {{demo_tb.gmii_rxd} {demo_tb.gmii_rx_dv} {demo_tb.gmii_rx_er}} -gui_list_add -id Wave.1 -after Transceiver_Tx_Signals {{demo_tb.txp} {demo_tb.txn}} -gui_list_add -id Wave.1 -after Transceiver_Rx_Signals {{demo_tb.rxp} {demo_tb.rxn}} -gui_list_add -id Wave.1 -after Tx_Monitor {{demo_tb.stimulus.mon_tx_clk} {demo_tb.stimulus.tx_pdata} {demo_tb.stimulus.tx_is_k}} -gui_list_add -id Wave.1 -after Tx_Monitor {{demo_tb.stimulus.bitclock}} -gui_list_add -id Wave.1 -after Rx_Stimulus {{demo_tb.stimulus.stim_rx_clk} {demo_tb.stimulus.rx_even} {demo_tb.stimulus.rx_pdata} {demo_tb.stimulus.rx_is_k} {demo_tb.stimulus.rx_rundisp_pos}} -gui_list_add -id Wave.1 -after Test_semaphores {{demo_tb.configuration_finished} {demo_tb.tx_monitor_finished} {demo_tb.rx_monitor_finished} {demo_tb.simulation_finished}} -gui_zoom -window Wave.1 -full - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/wave_mti.do b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/wave_mti.do deleted file mode 100755 index 21e9c6b0d..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/wave_mti.do +++ /dev/null @@ -1,44 +0,0 @@ -view structure -view signals -view wave - -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {System Signals} -add wave -noupdate -format logic /demo_tb/reset -add wave -noupdate -format logic /demo_tb/gtrefclk_p -add wave -noupdate -format logic /demo_tb/gtrefclk_n -add wave -noupdate -format logic /demo_tb/signal_detect -add wave -noupdate -divider {Management I/F} -add wave -noupdate -format logic -binary /demo_tb/status_vector -add wave -noupdate -divider {Tx GMII} -add wave -noupdate -format logic -hex /demo_tb/gmii_txd -add wave -noupdate -format logic /demo_tb/gmii_tx_en -add wave -noupdate -format logic /demo_tb/gmii_tx_er -add wave -noupdate -divider {Rx GMII} -add wave -noupdate -format logic -hex /demo_tb/gmii_rxd -add wave -noupdate -format logic /demo_tb/gmii_rx_dv -add wave -noupdate -format logic /demo_tb/gmii_rx_er -add wave -noupdate -divider {Transceiver Tx} -add wave -noupdate -format logic /demo_tb/txp -add wave -noupdate -format logic /demo_tb/txn -add wave -noupdate -divider {Transceiver Rx} -add wave -noupdate -format logic /demo_tb/rxp -add wave -noupdate -format logic /demo_tb/rxn -add wave -noupdate -divider {Tx Monitor} -add wave -noupdate -format logic /demo_tb/stimulus/mon_tx_clk -add wave -noupdate -format logic -hex /demo_tb/stimulus/tx_pdata -add wave -noupdate -format logic /demo_tb/stimulus/tx_is_k -add wave -noupdate -format logic /demo_tb/stimulus/bitclock -add wave -noupdate -divider {Rx Stimulus} -add wave -noupdate -format logic /demo_tb/stimulus/stim_rx_clk -add wave -noupdate -format logic /demo_tb/stimulus/rx_even -add wave -noupdate -format logic -hex /demo_tb/stimulus/rx_pdata -add wave -noupdate -format logic /demo_tb/stimulus/rx_is_k -add wave -noupdate -format logic /demo_tb/stimulus/rx_rundisp_pos -add wave -noupdate -divider {Test semaphores} -add wave -noupdate -format logic /demo_tb/configuration_finished -add wave -noupdate -format logic /demo_tb/tx_monitor_finished -add wave -noupdate -format logic /demo_tb/rx_monitor_finished -add wave -noupdate -format logic /demo_tb/simulation_finished -TreeUpdate [SetDefaultTree] diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/wave_ncsim.sv deleted file mode 100755 index c5f10d3a5..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/functional/wave_ncsim.sv +++ /dev/null @@ -1,148 +0,0 @@ -# SimVision Command Script - -# -# groups -# - -if {[catch {group new -name {System Signals} -overlay 0}] != ""} { - group using {System Signals} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.reset \ - demo_tb.gtrefclk_p \ - demo_tb.gtrefclk_n - demo_tb.signal_detect \ - -if {[catch {group new -name {Management I/F} -overlay 0}] != ""} { - group using {Management I/F} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.status_vector - -if {[catch {group new -name {Tx GMII} -overlay 0}] != ""} { - group using {Tx GMII} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - {demo_tb.gmii_txd[7:0]} \ - demo_tb.gmii_tx_en \ - demo_tb.gmii_tx_er - -if {[catch {group new -name {Rx GMII} -overlay 0}] != ""} { - group using {Rx GMII} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - {demo_tb.gmii_rxd[7:0]} \ - demo_tb.gmii_rx_dv \ - demo_tb.gmii_rx_er - -if {[catch {group new -name {Transceiver Tx} -overlay 0}] != ""} { - group using {Transceiver Tx} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.txp \ - demo_tb.txn - -if {[catch {group new -name {Transceiver Rx} -overlay 0}] != ""} { - group using {Transceiver Rx} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.rxp \ - demo_tb.rxn - -if {[catch {group new -name {Tx Monitor} -overlay 0}] != ""} { - group using {Tx Monitor} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.stimulus.mon_tx_clk \ - {demo_tb.stimulus.tx_pdata[7:0]} \ - demo_tb.stimulus.tx_is_k \ - demo_tb.stimulus.bitclock -if {[catch {group new -name {Rx Stimulus} -overlay 0}] != ""} { - group using {Rx Stimulus} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.stimulus.stim_rx_clk \ - demo_tb.stimulus.rx_even \ - {demo_tb.stimulus.rx_pdata[7:0]} \ - demo_tb.stimulus.rx_is_k \ - demo_tb.stimulus.rx_rundisp_pos - -if {[catch {group new -name {Test semaphores} -overlay 0}] != ""} { - group using {Test semaphores} - group set -overlay 0 - group set -comment {} - group clear 0 end -} -group insert \ - demo_tb.configuration_finished \ - demo_tb.tx_monitor_finished \ - demo_tb.rx_monitor_finished \ - demo_tb.simulation_finished - -# -# Waveform windows -# -if {[window find -match exact -name "Waveform 1"] == {}} { - window new WaveWindow -name "Waveform 1" -geometry 906x585+25+55 -} else { - window geometry "Waveform 1" 906x585+25+55 -} -window target "Waveform 1" on -waveform using {Waveform 1} -waveform sidebar visibility partial -waveform set \ - -primarycursor TimeA \ - -signalnames name \ - -signalwidth 175 \ - -units fs \ - -valuewidth 75 -cursor set -using TimeA -time 50,000,000,000fs -cursor set -using TimeA -marching 1 -waveform baseline set -time 0 - -set groupId [waveform add -groups {{System Signals}}] - -set groupId [waveform add -groups {{Management I/F}}] - -set groupId [waveform add -groups {{Tx GMII}}] - -set groupId [waveform add -groups {{Rx GMII}}] - -set groupId [waveform add -groups {{Transceiver Tx}}] - -set groupId [waveform add -groups {{Transceiver Rx}}] - - -set groupId [waveform add -groups {{Tx Monitor}}] - -set groupId [waveform add -groups {{Rx Stimulus}}] - -set groupId [waveform add -groups {{Test semaphores}}] - -waveform xview limits 0fs 10us - -simcontrol run -time 200us diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/stimulus_tb.v b/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/stimulus_tb.v deleted file mode 100755 index 92ba4e25e..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp/simulation/stimulus_tb.v +++ /dev/null @@ -1,1649 +0,0 @@ -//------------------------------------------------------------------------------ -// File : stimulus_tb.v -// Author : Xilinx Inc. -//------------------------------------------------------------------------------ -// (c) Copyright 2002-2008 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// -//------------------------------------------------------------------------------ -// -// Description: This testbench will exercise the ports of the Ethernet -// 1000BASE-X PCS/PMA core's example design to perform the following -// operations: -// -//---------------- -// Transmitter -//---------------- -// Four frames are generated by the Tx Stimulus and pushed into the -// GMII transmitter. -// -// The PHY side transmitter interface data is captured, 8B10B decoded -// and the Tx Monitor checks that the captured data matches that -// injected. -// -//---------------- -// Receiver -//---------------- -// Four frames are generated by the Rx Stimulus, 8B10B encoded and -// pushed into the PHY side receiver interface. -// -// The GMII side receiver interface data is captured and the -// Rx Monitor checks that the captured data matches that injected. -// -// -//---------------------------------------------------------------------- -// Demonstration Test Fixture | -// | -// | -// -------------------------- | -// | Example Design | | -// | (DUT) | | -// | | | -// | | | -// | | | -// Tx | | 8B10B decode, Tx | -// Generate -------> --------> Monitor | -// Frames | | Frames | -// |GMII PHY | | -// | I/F I/F | | -// | | | -// | | | -// | | | -// Rx | | 8B10B encode, Rx | -// Monitor <-------- <-------- Generate | -// Frames | | Frames | -// | | | -// -------------------------- | -// | -// | -//---------------------------------------------------------------------- - - -`timescale 1 ps/1 ps - - - -// This module abstracts the frame data for simpler manipulation -module frame_typ; - reg [7:0] data [0:73]; - reg valid [0:73]; - reg error [0:73]; - -`define FRAME_TYP [8*74+74+74:1] - - reg `FRAME_TYP bits; - - function `FRAME_TYP tobits; - input dummy; - begin - bits = {data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], - data[ 5], data[ 6], data[ 7], data[ 8], data[ 9], - data[10], data[11], data[12], data[13], data[14], - data[15], data[16], data[17], data[18], data[19], - data[20], data[21], data[22], data[23], data[24], - data[25], data[26], data[27], data[28], data[29], - data[30], data[31], data[32], data[33], data[34], - data[35], data[36], data[37], data[38], data[39], - data[40], data[41], data[42], data[43], data[44], - data[45], data[46], data[47], data[48], data[49], - data[50], data[51], data[52], data[53], data[54], - data[55], data[56], data[57], data[58], data[59], - data[60], data[61], data[62], data[63], data[64], - data[65], data[66], data[67], data[68], data[69], - data[70], data[71], data[72], data[73], - - valid[ 0], valid[ 1], valid[ 2], valid[ 3], valid[ 4], - valid[ 5], valid[ 6], valid[ 7], valid[ 8], valid[ 9], - valid[10], valid[11], valid[12], valid[13], valid[14], - valid[15], valid[16], valid[17], valid[18], valid[19], - valid[20], valid[21], valid[22], valid[23], valid[24], - valid[25], valid[26], valid[27], valid[28], valid[29], - valid[30], valid[31], valid[32], valid[33], valid[34], - valid[35], valid[36], valid[37], valid[38], valid[39], - valid[40], valid[41], valid[42], valid[43], valid[44], - valid[45], valid[46], valid[47], valid[48], valid[49], - valid[50], valid[51], valid[52], valid[53], valid[54], - valid[55], valid[56], valid[57], valid[58], valid[59], - valid[60], valid[61], valid[62], valid[63], valid[64], - valid[65], valid[66], valid[67], valid[68], valid[69], - valid[70], valid[71], valid[72], valid[73], - - error[ 0], error[ 1], error[ 2], error[ 3], error[ 4], - error[ 5], error[ 6], error[ 7], error[ 8], error[ 9], - error[10], error[11], error[12], error[13], error[14], - error[15], error[16], error[17], error[18], error[19], - error[20], error[21], error[22], error[23], error[24], - error[25], error[26], error[27], error[28], error[29], - error[30], error[31], error[32], error[33], error[34], - error[35], error[36], error[37], error[38], error[39], - error[40], error[41], error[42], error[43], error[44], - error[45], error[46], error[47], error[48], error[49], - error[50], error[51], error[52], error[53], error[54], - error[55], error[56], error[57], error[58], error[59], - error[60], error[61], error[62], error[63], error[64], - error[65], error[66], error[67], error[68], error[69], - error[70], error[71], error[72], error[73]}; - tobits = bits; - end - endfunction // tobits - - task frombits; - input `FRAME_TYP frame; - begin - bits = frame; - {data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], - data[ 5], data[ 6], data[ 7], data[ 8], data[ 9], - data[10], data[11], data[12], data[13], data[14], - data[15], data[16], data[17], data[18], data[19], - data[20], data[21], data[22], data[23], data[24], - data[25], data[26], data[27], data[28], data[29], - data[30], data[31], data[32], data[33], data[34], - data[35], data[36], data[37], data[38], data[39], - data[40], data[41], data[42], data[43], data[44], - data[45], data[46], data[47], data[48], data[49], - data[50], data[51], data[52], data[53], data[54], - data[55], data[56], data[57], data[58], data[59], - data[60], data[61], data[62], data[63], data[64], - data[65], data[66], data[67], data[68], data[69], - data[70], data[71], data[72], data[73], - - valid[ 0], valid[ 1], valid[ 2], valid[ 3], valid[ 4], - valid[ 5], valid[ 6], valid[ 7], valid[ 8], valid[ 9], - valid[10], valid[11], valid[12], valid[13], valid[14], - valid[15], valid[16], valid[17], valid[18], valid[19], - valid[20], valid[21], valid[22], valid[23], valid[24], - valid[25], valid[26], valid[27], valid[28], valid[29], - valid[30], valid[31], valid[32], valid[33], valid[34], - valid[35], valid[36], valid[37], valid[38], valid[39], - valid[40], valid[41], valid[42], valid[43], valid[44], - valid[45], valid[46], valid[47], valid[48], valid[49], - valid[50], valid[51], valid[52], valid[53], valid[54], - valid[55], valid[56], valid[57], valid[58], valid[59], - valid[60], valid[61], valid[62], valid[63], valid[64], - valid[65], valid[66], valid[67], valid[68], valid[69], - valid[70], valid[71], valid[72], valid[73], - - error[ 0], error[ 1], error[ 2], error[ 3], error[ 4], - error[ 5], error[ 6], error[ 7], error[ 8], error[ 9], - error[10], error[11], error[12], error[13], error[14], - error[15], error[16], error[17], error[18], error[19], - error[20], error[21], error[22], error[23], error[24], - error[25], error[26], error[27], error[28], error[29], - error[30], error[31], error[32], error[33], error[34], - error[35], error[36], error[37], error[38], error[39], - error[40], error[41], error[42], error[43], error[44], - error[45], error[46], error[47], error[48], error[49], - error[50], error[51], error[52], error[53], error[54], - error[55], error[56], error[57], error[58], error[59], - error[60], error[61], error[62], error[63], error[64], - error[65], error[66], error[67], error[68], error[69], - error[70], error[71], error[72], error[73]} = bits; - end - endtask // frombits - -endmodule // frame_typ - - - - -//------------------------------------------------------------------------------ -// This module is the ethernet frame stimulus testbench -//------------------------------------------------------------------------------ - -module stimulus_tb # - ( - parameter INSTANCE_NUMBER = 0 - ) - - ( - - // Physical Interface (Transceiver) - //------------------------------ - input txp, - input txn, - output reg rxp, - output reg rxn, - - // GMII Interface - //--------------- - output gmii_tx_clk, - input gmii_rx_clk, - output reg [7:0] gmii_txd, - output reg gmii_tx_en, - output reg gmii_tx_er, - input [7:0] gmii_rxd, - input gmii_rx_dv, - input gmii_rx_er, - - // Test Bench Semaphores - //---------------------- - input configuration_finished, - output reg tx_monitor_finished, - output reg rx_monitor_finished - ); - - - // Unit Interval for Gigabit Ethernet - parameter UI = 800; // 800 ps - - - //---------------------------------------------------------------------------- - // Procedure to perform 8B10B decoding - //---------------------------------------------------------------------------- - - // Decode the 8B10B code. No disparity verification is performed, just - // a simple table lookup. - task decode_8b10b; - input [0:9] d10; - output [7:0] q8; - output is_k; - reg k28; - reg [9:0] d10_rev; - integer I; - begin - // reverse the 10B codeword - for (I = 0; I < 10; I = I + 1) - d10_rev[I] = d10[I]; - case (d10_rev[5:0]) - 6'b000110 : q8[4:0] = 5'b00000; //D.0 - 6'b111001 : q8[4:0] = 5'b00000; //D.0 - 6'b010001 : q8[4:0] = 5'b00001; //D.1 - 6'b101110 : q8[4:0] = 5'b00001; //D.1 - 6'b010010 : q8[4:0] = 5'b00010; //D.2 - 6'b101101 : q8[4:0] = 5'b00010; //D.2 - 6'b100011 : q8[4:0] = 5'b00011; //D.3 - 6'b010100 : q8[4:0] = 5'b00100; //D.4 - 6'b101011 : q8[4:0] = 5'b00100; //D.4 - 6'b100101 : q8[4:0] = 5'b00101; //D.5 - 6'b100110 : q8[4:0] = 5'b00110; //D.6 - 6'b000111 : q8[4:0] = 5'b00111; //D.7 - 6'b111000 : q8[4:0] = 5'b00111; //D.7 - 6'b011000 : q8[4:0] = 5'b01000; //D.8 - 6'b100111 : q8[4:0] = 5'b01000; //D.8 - 6'b101001 : q8[4:0] = 5'b01001; //D.9 - 6'b101010 : q8[4:0] = 5'b01010; //D.10 - 6'b001011 : q8[4:0] = 5'b01011; //D.11 - 6'b101100 : q8[4:0] = 5'b01100; //D.12 - 6'b001101 : q8[4:0] = 5'b01101; //D.13 - 6'b001110 : q8[4:0] = 5'b01110; //D.14 - 6'b000101 : q8[4:0] = 5'b01111; //D.15 - 6'b111010 : q8[4:0] = 5'b01111; //D.15 - 6'b110110 : q8[4:0] = 5'b10000; //D.16 - 6'b001001 : q8[4:0] = 5'b10000; //D.16 - 6'b110001 : q8[4:0] = 5'b10001; //D.17 - 6'b110010 : q8[4:0] = 5'b10010; //D.18 - 6'b010011 : q8[4:0] = 5'b10011; //D.19 - 6'b110100 : q8[4:0] = 5'b10100; //D.20 - 6'b010101 : q8[4:0] = 5'b10101; //D.21 - 6'b010110 : q8[4:0] = 5'b10110; //D.22 - 6'b010111 : q8[4:0] = 5'b10111; //D/K.23 - 6'b101000 : q8[4:0] = 5'b10111; //D/K.23 - 6'b001100 : q8[4:0] = 5'b11000; //D.24 - 6'b110011 : q8[4:0] = 5'b11000; //D.24 - 6'b011001 : q8[4:0] = 5'b11001; //D.25 - 6'b011010 : q8[4:0] = 5'b11010; //D.26 - 6'b011011 : q8[4:0] = 5'b11011; //D/K.27 - 6'b100100 : q8[4:0] = 5'b11011; //D/K.27 - 6'b011100 : q8[4:0] = 5'b11100; //D.28 - 6'b111100 : q8[4:0] = 5'b11100; //K.28 - 6'b000011 : q8[4:0] = 5'b11100; //K.28 - 6'b011101 : q8[4:0] = 5'b11101; //D/K.29 - 6'b100010 : q8[4:0] = 5'b11101; //D/K.29 - 6'b011110 : q8[4:0] = 5'b11110; //D.30 - 6'b100001 : q8[4:0] = 5'b11110; //D.30 - 6'b110101 : q8[4:0] = 5'b11111; //D.31 - 6'b001010 : q8[4:0] = 5'b11111; //D.31 - default : q8[4:0] = 5'b11110; //CODE VIOLATION - return /E/ - endcase - - k28 = ~((d10[2] | d10[3] | d10[4] | d10[5] | ~(d10[8] ^ d10[9]))); - - case (d10_rev[9:6]) - 4'b0010 : q8[7:5] = 3'b000; //D/K.x.0 - 4'b1101 : q8[7:5] = 3'b000; //D/K.x.0 - 4'b1001 : - if (!k28) - q8[7:5] = 3'b001; //D/K.x.1 - else - q8[7:5] = 3'b110; //K28.6 - 4'b0110 : - if (k28) - q8[7:5] = 3'b001; //K.28.1 - else - q8[7:5] = 3'b110; //D/K.x.6 - 4'b1010 : - if (!k28) - q8[7:5] = 3'b010; //D/K.x.2 - else - q8[7:5] = 3'b101; //K28.5 - 4'b0101 : - if (k28) - q8[7:5] = 3'b010; //K28.2 - else - q8[7:5] = 3'b101; //D/K.x.5 - 4'b0011 : q8[7:5] = 3'b011; //D/K.x.3 - 4'b1100 : q8[7:5] = 3'b011; //D/K.x.3 - 4'b0100 : q8[7:5] = 3'b100; //D/K.x.4 - 4'b1011 : q8[7:5] = 3'b100; //D/K.x.4 - 4'b0111 : q8[7:5] = 3'b111; //D.x.7 - 4'b1000 : q8[7:5] = 3'b111; //D.x.7 - 4'b1110 : q8[7:5] = 3'b111; //D/K.x.7 - 4'b0001 : q8[7:5] = 3'b111; //D/K.x.7 - default : q8[7:5] = 3'b111; //CODE VIOLATION - return /E/ - endcase - is_k = ((d10[2] & d10[3] & d10[4] & d10[5]) - | ~(d10[2] | d10[3] | d10[4] | d10[5]) - | ((d10[4] ^ d10[5]) & ((d10[5] & d10[7] & d10[8] & d10[9]) - | ~(d10[5] | d10[7] | d10[8] | d10[9])))); - - end - endtask // decode_8b10b - - - - //---------------------------------------------------------------------------- - // Procedure to perform comma detection - //---------------------------------------------------------------------------- - - function is_comma; - input [0:9] codegroup; - begin - case (codegroup[0:6]) - 7'b0011111 : is_comma = 1; - 7'b1100000 : is_comma = 1; - default : is_comma = 0; - endcase // case(codegroup[0:6]) - end - endfunction // is_comma - - - //---------------------------------------------------------------------------- - // Procedure to perform 8B10B encoding - //---------------------------------------------------------------------------- - - task encode_8b10b; - input [7:0] d8; - input is_k; - output [0:9] q10; - input disparity_pos_in; - output disparity_pos_out; - reg [5:0] b6; - reg [3:0] b4; - reg k28, pdes6, a7, l13, l31, a, b, c, d, e; - integer I; - - begin // encode_8b10b - // precalculate some common terms - a = d8[0]; - b = d8[1]; - c = d8[2]; - d = d8[3]; - e = d8[4]; - - k28 = is_k && d8[4:0] === 5'b11100; - - l13 = (((a ^ b) & !(c | d)) - | ((c ^ d) & !(a | b))); - - l31 = (((a ^ b) & (c & d)) - | ((c ^ d) & (a & b))); - - a7 = is_k | ((l31 & d & !e & disparity_pos_in) - | (l13 & !d & e & !disparity_pos_in)); - - // calculate the running disparity after the 5B6B block encode - if (k28) //K.28 - if (!disparity_pos_in) - b6 = 6'b111100; - else - b6 = 6'b000011; - - else - case (d8[4:0]) - 5'b00000 : //D.0 - if (disparity_pos_in) - b6 = 6'b000110; - else - b6 = 6'b111001; - 5'b00001 : //D.1 - if (disparity_pos_in) - b6 = 6'b010001; - else - b6 = 6'b101110; - 5'b00010 : //D.2 - if (disparity_pos_in) - b6 = 6'b010010; - else - b6 = 6'b101101; - 5'b00011 : - b6 = 6'b100011; //D.3 - 5'b00100 : //-D.4 - if (disparity_pos_in) - b6 = 6'b010100; - else - b6 = 6'b101011; - 5'b00101 : - b6 = 6'b100101; //D.5 - 5'b00110 : - b6 = 6'b100110; //D.6 - 5'b00111 : //D.7 - if (!disparity_pos_in) - b6 = 6'b000111; - else - b6 = 6'b111000; - 5'b01000 : //D.8 - if (disparity_pos_in) - b6 = 6'b011000; - else - b6 = 6'b100111; - 5'b01001 : - b6 = 6'b101001; //D.9 - 5'b01010 : - b6 = 6'b101010; //D.10 - 5'b01011 : - b6 = 6'b001011; //D.11 - 5'b01100 : - b6 = 6'b101100; //D.12 - 5'b01101 : - b6 = 6'b001101; //D.13 - 5'b01110 : - b6 = 6'b001110; //D.14 - 5'b01111 : //D.15 - if (disparity_pos_in) - b6 = 6'b000101; - else - b6 = 6'b111010; - - 5'b10000 : //D.16 - if (!disparity_pos_in) - b6 = 6'b110110; - else - b6 = 6'b001001; - - 5'b10001 : - b6 = 6'b110001; //D.17 - 5'b10010 : - b6 = 6'b110010; //D.18 - 5'b10011 : - b6 = 6'b010011; //D.19 - 5'b10100 : - b6 = 6'b110100; //D.20 - 5'b10101 : - b6 = 6'b010101; //D.21 - 5'b10110 : - b6 = 6'b010110; //D.22 - 5'b10111 : //D/K.23 - if (!disparity_pos_in) - b6 = 6'b010111; - else - b6 = 6'b101000; - 5'b11000 : //D.24 - if (disparity_pos_in) - b6 = 6'b001100; - else - b6 = 6'b110011; - 5'b11001 : - b6 = 6'b011001; //D.25 - 5'b11010 : - b6 = 6'b011010; //D.26 - 5'b11011 : //D/K.27 - if (!disparity_pos_in) - b6 = 6'b011011; - else - b6 = 6'b100100; - 5'b11100 : - b6 = 6'b011100; //D.28 - 5'b11101 : //D/K.29 - if (!disparity_pos_in) - b6 = 6'b011101; - else - b6 = 6'b100010; - 5'b11110 : //D/K.30 - if (!disparity_pos_in) - b6 = 6'b011110; - else - b6 = 6'b100001; - 5'b11111 : //D.31 - if (!disparity_pos_in) - b6 = 6'b110101; - else - b6 = 6'b001010; - default : - b6 = 6'bXXXXXX; - endcase // case(d8[4:0]) - - - // reverse the bits - for (I = 0; I < 6; I = I + 1) - q10[I] = b6[I]; - - - // calculate the running disparity after the 5B6B block encode - if (k28) - pdes6 = !disparity_pos_in; - else - case (d8[4:0]) - 5'b00000 : pdes6 = !disparity_pos_in; - 5'b00001 : pdes6 = !disparity_pos_in; - 5'b00010 : pdes6 = !disparity_pos_in; - 5'b00011 : pdes6 = disparity_pos_in; - 5'b00100 : pdes6 = !disparity_pos_in; - 5'b00101 : pdes6 = disparity_pos_in; - 5'b00110 : pdes6 = disparity_pos_in; - 5'b00111 : pdes6 = disparity_pos_in; - 5'b01000 : pdes6 = !disparity_pos_in; - 5'b01001 : pdes6 = disparity_pos_in; - 5'b01010 : pdes6 = disparity_pos_in; - 5'b01011 : pdes6 = disparity_pos_in; - 5'b01100 : pdes6 = disparity_pos_in; - 5'b01101 : pdes6 = disparity_pos_in; - 5'b01110 : pdes6 = disparity_pos_in; - 5'b01111 : pdes6 = !disparity_pos_in; - 5'b10000 : pdes6 = !disparity_pos_in; - 5'b10001 : pdes6 = disparity_pos_in; - 5'b10010 : pdes6 = disparity_pos_in; - 5'b10011 : pdes6 = disparity_pos_in; - 5'b10100 : pdes6 = disparity_pos_in; - 5'b10101 : pdes6 = disparity_pos_in; - 5'b10110 : pdes6 = disparity_pos_in; - 5'b10111 : pdes6 = !disparity_pos_in; - 5'b11000 : pdes6 = !disparity_pos_in; - 5'b11001 : pdes6 = disparity_pos_in; - 5'b11010 : pdes6 = disparity_pos_in; - 5'b11011 : pdes6 = !disparity_pos_in; - 5'b11100 : pdes6 = disparity_pos_in; - 5'b11101 : pdes6 = !disparity_pos_in; - 5'b11110 : pdes6 = !disparity_pos_in; - 5'b11111 : pdes6 = !disparity_pos_in; - default : pdes6 = disparity_pos_in; - endcase // case(d8[4:0]) - - case (d8[7:5]) - 3'b000 : //D/K.x.0 - if (pdes6) - b4 = 4'b0010; - else - b4 = 4'b1101; - 3'b001 : //D/K.x.1 - if (k28 && !pdes6) - b4 = 4'b0110; - else - b4 = 4'b1001; - 3'b010 : //D/K.x.2 - if (k28 && !pdes6) - b4 = 4'b0101; - else - b4 = 4'b1010; - 3'b011 : //D/K.x.3 - if (!pdes6) - b4 = 4'b0011; - else - b4 = 4'b1100; - 3'b100 : //D/K.x.4 - if (pdes6) - b4 = 4'b0100; - else - b4 = 4'b1011; - 3'b101 : //D/K.x.5 - if (k28 && !pdes6) - b4 = 4'b1010; - else - b4 = 4'b0101; - 3'b110 : //D/K.x.6 - if (k28 && !pdes6) - b4 = 4'b1001; - else - b4 = 4'b0110; - 3'b111 : //D.x.P7 - if (!a7) - if (!pdes6) - b4 = 4'b0111; - else - b4 = 4'b1000; - else //D/K.y.A7 - if (!pdes6) - b4 = 4'b1110; - else - b4 = 4'b0001; - default : - b4 = 4'bXXXX; - endcase - - // Reverse the bits - for (I = 0; I < 4; I = I + 1) - q10[I+6] = b4[I]; - - // Calculate the running disparity after the 4B group - case (d8[7:5]) - 3'b000 : disparity_pos_out = ~pdes6; - 3'b001 : disparity_pos_out = pdes6; - 3'b010 : disparity_pos_out = pdes6; - 3'b011 : disparity_pos_out = pdes6; - 3'b100 : disparity_pos_out = ~pdes6; - 3'b101 : disparity_pos_out = pdes6; - 3'b110 : disparity_pos_out = pdes6; - 3'b111 : disparity_pos_out = ~pdes6; - default : disparity_pos_out = pdes6; - endcase - end - endtask // encode_8b10b - - - - //---------------------------------------------------------------------------- - // types to support frame data - //---------------------------------------------------------------------------- - - frame_typ frame0(); - frame_typ frame1(); - frame_typ frame2(); - frame_typ frame3(); - - frame_typ tx_stimulus_working_frame(); - frame_typ tx_monitor_working_frame(); - frame_typ rx_stimulus_working_frame(); - frame_typ rx_monitor_working_frame(); - - //---------------------------------------------------------------------------- - // Stimulus - Frame data - //---------------------------------------------------------------------------- - // The following constant holds the stimulus for the testbench. It is - // an ordered array of frames, with frame 0 the first to be injected - // into the core by the testbench. - // - // This stimulus is used for both transmitter and receiver paths. - //---------------------------------------------------------------------------- - initial - begin - // Frame 0... - frame0.data[0] = 8'h55; frame0.valid[0] = 1'b1; frame0.error[0] = 1'b0; // Preamble - frame0.data[1] = 8'h55; frame0.valid[1] = 1'b1; frame0.error[1] = 1'b0; - frame0.data[2] = 8'h55; frame0.valid[2] = 1'b1; frame0.error[2] = 1'b0; - frame0.data[3] = 8'h55; frame0.valid[3] = 1'b1; frame0.error[3] = 1'b0; - frame0.data[4] = 8'h55; frame0.valid[4] = 1'b1; frame0.error[4] = 1'b0; - frame0.data[5] = 8'h55; frame0.valid[5] = 1'b1; frame0.error[5] = 1'b0; - frame0.data[6] = 8'h55; frame0.valid[6] = 1'b1; frame0.error[6] = 1'b0; - frame0.data[7] = 8'hd5; frame0.valid[7] = 1'b1; frame0.error[7] = 1'b0; // SFD - frame0.data[8] = 8'hda; frame0.valid[8] = 1'b1; frame0.error[8] = 1'b0; // Destination Address (DA) - frame0.data[9] = 8'h02; frame0.valid[9] = 1'b1; frame0.error[9] = 1'b0; - frame0.data[10] = 8'h03; frame0.valid[10] = 1'b1; frame0.error[10] = 1'b0; - frame0.data[11] = 8'h04; frame0.valid[11] = 1'b1; frame0.error[11] = 1'b0; - frame0.data[12] = 8'h05; frame0.valid[12] = 1'b1; frame0.error[12] = 1'b0; - frame0.data[13] = 8'h06; frame0.valid[13] = 1'b1; frame0.error[13] = 1'b0; - frame0.data[14] = 8'h5a; frame0.valid[14] = 1'b1; frame0.error[14] = 1'b0; // Source Address (5A) - frame0.data[15] = 8'h02; frame0.valid[15] = 1'b1; frame0.error[15] = 1'b0; - frame0.data[16] = 8'h03; frame0.valid[16] = 1'b1; frame0.error[16] = 1'b0; - frame0.data[17] = 8'h04; frame0.valid[17] = 1'b1; frame0.error[17] = 1'b0; - frame0.data[18] = 8'h05; frame0.valid[18] = 1'b1; frame0.error[18] = 1'b0; - frame0.data[19] = 8'h06; frame0.valid[19] = 1'b1; frame0.error[19] = 1'b0; - frame0.data[20] = 8'h00; frame0.valid[20] = 1'b1; frame0.error[20] = 1'b0; - frame0.data[21] = 8'h2e; frame0.valid[21] = 1'b1; frame0.error[21] = 1'b0; // Length/Type = Length = 46 - frame0.data[22] = 8'h01; frame0.valid[22] = 1'b1; frame0.error[22] = 1'b0; - frame0.data[23] = 8'h02; frame0.valid[23] = 1'b1; frame0.error[23] = 1'b0; // Data - frame0.data[24] = 8'h03; frame0.valid[24] = 1'b1; frame0.error[24] = 1'b0; - frame0.data[25] = 8'h04; frame0.valid[25] = 1'b1; frame0.error[25] = 1'b0; - frame0.data[26] = 8'h05; frame0.valid[26] = 1'b1; frame0.error[26] = 1'b0; - frame0.data[27] = 8'h06; frame0.valid[27] = 1'b1; frame0.error[27] = 1'b0; - frame0.data[28] = 8'h07; frame0.valid[28] = 1'b1; frame0.error[28] = 1'b0; - frame0.data[29] = 8'h08; frame0.valid[29] = 1'b1; frame0.error[29] = 1'b0; - frame0.data[30] = 8'h09; frame0.valid[30] = 1'b1; frame0.error[30] = 1'b0; - frame0.data[31] = 8'h0a; frame0.valid[31] = 1'b1; frame0.error[31] = 1'b0; - frame0.data[32] = 8'h0b; frame0.valid[32] = 1'b1; frame0.error[32] = 1'b0; - frame0.data[33] = 8'h0c; frame0.valid[33] = 1'b1; frame0.error[33] = 1'b0; - frame0.data[34] = 8'h0d; frame0.valid[34] = 1'b1; frame0.error[34] = 1'b0; - frame0.data[35] = 8'h0e; frame0.valid[35] = 1'b1; frame0.error[35] = 1'b0; - frame0.data[36] = 8'h0f; frame0.valid[36] = 1'b1; frame0.error[36] = 1'b0; - frame0.data[37] = 8'h10; frame0.valid[37] = 1'b1; frame0.error[37] = 1'b0; - frame0.data[38] = 8'h11; frame0.valid[38] = 1'b1; frame0.error[38] = 1'b0; - frame0.data[39] = 8'h12; frame0.valid[39] = 1'b1; frame0.error[39] = 1'b0; - frame0.data[40] = 8'h13; frame0.valid[40] = 1'b1; frame0.error[40] = 1'b0; - frame0.data[41] = 8'h14; frame0.valid[41] = 1'b1; frame0.error[41] = 1'b0; - frame0.data[42] = 8'h15; frame0.valid[42] = 1'b1; frame0.error[42] = 1'b0; - frame0.data[43] = 8'h16; frame0.valid[43] = 1'b1; frame0.error[43] = 1'b0; - frame0.data[44] = 8'h17; frame0.valid[44] = 1'b1; frame0.error[44] = 1'b0; - frame0.data[45] = 8'h18; frame0.valid[45] = 1'b1; frame0.error[45] = 1'b0; - frame0.data[46] = 8'h19; frame0.valid[46] = 1'b1; frame0.error[46] = 1'b0; - frame0.data[47] = 8'h1a; frame0.valid[47] = 1'b1; frame0.error[47] = 1'b0; - frame0.data[48] = 8'h1b; frame0.valid[48] = 1'b1; frame0.error[48] = 1'b0; - frame0.data[49] = 8'h1c; frame0.valid[49] = 1'b1; frame0.error[49] = 1'b0; - frame0.data[50] = 8'h1d; frame0.valid[50] = 1'b1; frame0.error[50] = 1'b0; - frame0.data[51] = 8'h1e; frame0.valid[51] = 1'b1; frame0.error[51] = 1'b0; - frame0.data[52] = 8'h1f; frame0.valid[52] = 1'b1; frame0.error[52] = 1'b0; - frame0.data[53] = 8'h20; frame0.valid[53] = 1'b1; frame0.error[53] = 1'b0; - frame0.data[54] = 8'h21; frame0.valid[54] = 1'b1; frame0.error[54] = 1'b0; - frame0.data[55] = 8'h22; frame0.valid[55] = 1'b1; frame0.error[55] = 1'b0; - frame0.data[56] = 8'h23; frame0.valid[56] = 1'b1; frame0.error[56] = 1'b0; - frame0.data[57] = 8'h24; frame0.valid[57] = 1'b1; frame0.error[57] = 1'b0; - frame0.data[58] = 8'h25; frame0.valid[58] = 1'b1; frame0.error[58] = 1'b0; - frame0.data[59] = 8'h26; frame0.valid[59] = 1'b1; frame0.error[59] = 1'b0; - frame0.data[60] = 8'h27; frame0.valid[60] = 1'b1; frame0.error[60] = 1'b0; - frame0.data[61] = 8'h28; frame0.valid[61] = 1'b1; frame0.error[61] = 1'b0; - frame0.data[62] = 8'h29; frame0.valid[62] = 1'b1; frame0.error[62] = 1'b0; - frame0.data[63] = 8'h2a; frame0.valid[63] = 1'b1; frame0.error[63] = 1'b0; - frame0.data[64] = 8'h2b; frame0.valid[64] = 1'b1; frame0.error[64] = 1'b0; - frame0.data[65] = 8'h2c; frame0.valid[65] = 1'b1; frame0.error[65] = 1'b0; - frame0.data[66] = 8'h2d; frame0.valid[66] = 1'b1; frame0.error[66] = 1'b0; - frame0.data[67] = 8'h2e; frame0.valid[67] = 1'b1; frame0.error[67] = 1'b0; - frame0.data[68] = 8'h14; frame0.valid[68] = 1'b1; frame0.error[68] = 1'b0; // FCS field - frame0.data[69] = 8'h19; frame0.valid[69] = 1'b1; frame0.error[69] = 1'b0; - frame0.data[70] = 8'hd1; frame0.valid[70] = 1'b1; frame0.error[70] = 1'b0; - frame0.data[71] = 8'hdd; frame0.valid[71] = 1'b1; frame0.error[71] = 1'b0; - frame0.data[72] = 8'h00; frame0.valid[72] = 1'b0; frame0.error[72] = 1'b0; - frame0.data[73] = 8'h00; frame0.valid[73] = 1'b0; frame0.error[73] = 1'b0; - - // frame 1... - frame1.data[0] = 8'h55; frame1.valid[0] = 1'b1; frame1.error[0] = 1'b0; // Preamble - frame1.data[1] = 8'h55; frame1.valid[1] = 1'b1; frame1.error[1] = 1'b0; - frame1.data[2] = 8'h55; frame1.valid[2] = 1'b1; frame1.error[2] = 1'b0; - frame1.data[3] = 8'h55; frame1.valid[3] = 1'b1; frame1.error[3] = 1'b0; - frame1.data[4] = 8'h55; frame1.valid[4] = 1'b1; frame1.error[4] = 1'b0; - frame1.data[5] = 8'h55; frame1.valid[5] = 1'b1; frame1.error[5] = 1'b0; - frame1.data[6] = 8'h55; frame1.valid[6] = 1'b1; frame1.error[6] = 1'b0; - frame1.data[7] = 8'hd5; frame1.valid[7] = 1'b1; frame1.error[7] = 1'b0; // SFD - frame1.data[8] = 8'hda; frame1.valid[8] = 1'b1; frame1.error[8] = 1'b0; // Destination Address (DA) - frame1.data[9] = 8'h02; frame1.valid[9] = 1'b1; frame1.error[9] = 1'b0; - frame1.data[10] = 8'h03; frame1.valid[10] = 1'b1; frame1.error[10] = 1'b0; - frame1.data[11] = 8'h04; frame1.valid[11] = 1'b1; frame1.error[11] = 1'b0; - frame1.data[12] = 8'h05; frame1.valid[12] = 1'b1; frame1.error[12] = 1'b0; - frame1.data[13] = 8'h06; frame1.valid[13] = 1'b1; frame1.error[13] = 1'b0; - frame1.data[14] = 8'h5a; frame1.valid[14] = 1'b1; frame1.error[14] = 1'b0; // Source Address (5A) - frame1.data[15] = 8'h02; frame1.valid[15] = 1'b1; frame1.error[15] = 1'b0; - frame1.data[16] = 8'h03; frame1.valid[16] = 1'b1; frame1.error[16] = 1'b0; - frame1.data[17] = 8'h04; frame1.valid[17] = 1'b1; frame1.error[17] = 1'b0; - frame1.data[18] = 8'h05; frame1.valid[18] = 1'b1; frame1.error[18] = 1'b0; - frame1.data[19] = 8'h06; frame1.valid[19] = 1'b1; frame1.error[19] = 1'b0; - frame1.data[20] = 8'h80; frame1.valid[20] = 1'b1; frame1.error[20] = 1'b0; - frame1.data[21] = 8'h00; frame1.valid[21] = 1'b1; frame1.error[21] = 1'b0; // Length/Type = Length = 8000 - frame1.data[22] = 8'h01; frame1.valid[22] = 1'b1; frame1.error[22] = 1'b0; - frame1.data[23] = 8'h02; frame1.valid[23] = 1'b1; frame1.error[23] = 1'b0; // Data - frame1.data[24] = 8'h03; frame1.valid[24] = 1'b1; frame1.error[24] = 1'b0; - frame1.data[25] = 8'h04; frame1.valid[25] = 1'b1; frame1.error[25] = 1'b0; - frame1.data[26] = 8'h05; frame1.valid[26] = 1'b1; frame1.error[26] = 1'b0; - frame1.data[27] = 8'h06; frame1.valid[27] = 1'b1; frame1.error[27] = 1'b0; - frame1.data[28] = 8'h07; frame1.valid[28] = 1'b1; frame1.error[28] = 1'b0; - frame1.data[29] = 8'h08; frame1.valid[29] = 1'b1; frame1.error[29] = 1'b0; - frame1.data[30] = 8'h09; frame1.valid[30] = 1'b1; frame1.error[30] = 1'b0; - frame1.data[31] = 8'h0a; frame1.valid[31] = 1'b1; frame1.error[31] = 1'b0; - frame1.data[32] = 8'h0b; frame1.valid[32] = 1'b1; frame1.error[32] = 1'b0; - frame1.data[33] = 8'h0c; frame1.valid[33] = 1'b1; frame1.error[33] = 1'b0; - frame1.data[34] = 8'h0d; frame1.valid[34] = 1'b1; frame1.error[34] = 1'b0; - frame1.data[35] = 8'h0e; frame1.valid[35] = 1'b1; frame1.error[35] = 1'b0; - frame1.data[36] = 8'h0f; frame1.valid[36] = 1'b1; frame1.error[36] = 1'b0; - frame1.data[37] = 8'h10; frame1.valid[37] = 1'b1; frame1.error[37] = 1'b0; - frame1.data[38] = 8'h11; frame1.valid[38] = 1'b1; frame1.error[38] = 1'b0; - frame1.data[39] = 8'h12; frame1.valid[39] = 1'b1; frame1.error[39] = 1'b0; - frame1.data[40] = 8'h13; frame1.valid[40] = 1'b1; frame1.error[40] = 1'b0; - frame1.data[41] = 8'h14; frame1.valid[41] = 1'b1; frame1.error[41] = 1'b0; - frame1.data[42] = 8'h15; frame1.valid[42] = 1'b1; frame1.error[42] = 1'b0; - frame1.data[43] = 8'h16; frame1.valid[43] = 1'b1; frame1.error[43] = 1'b0; - frame1.data[44] = 8'h17; frame1.valid[44] = 1'b1; frame1.error[44] = 1'b0; - frame1.data[45] = 8'h18; frame1.valid[45] = 1'b1; frame1.error[45] = 1'b0; - frame1.data[46] = 8'h19; frame1.valid[46] = 1'b1; frame1.error[46] = 1'b0; - frame1.data[47] = 8'h1a; frame1.valid[47] = 1'b1; frame1.error[47] = 1'b0; - frame1.data[48] = 8'h1b; frame1.valid[48] = 1'b1; frame1.error[48] = 1'b0; - frame1.data[49] = 8'h1c; frame1.valid[49] = 1'b1; frame1.error[49] = 1'b0; - frame1.data[50] = 8'h1d; frame1.valid[50] = 1'b1; frame1.error[50] = 1'b0; - frame1.data[51] = 8'h1e; frame1.valid[51] = 1'b1; frame1.error[51] = 1'b0; - frame1.data[52] = 8'h1f; frame1.valid[52] = 1'b1; frame1.error[52] = 1'b0; - frame1.data[53] = 8'h20; frame1.valid[53] = 1'b1; frame1.error[53] = 1'b0; - frame1.data[54] = 8'h21; frame1.valid[54] = 1'b1; frame1.error[54] = 1'b0; - frame1.data[55] = 8'h22; frame1.valid[55] = 1'b1; frame1.error[55] = 1'b0; - frame1.data[56] = 8'h23; frame1.valid[56] = 1'b1; frame1.error[56] = 1'b0; - frame1.data[57] = 8'h24; frame1.valid[57] = 1'b1; frame1.error[57] = 1'b0; - frame1.data[58] = 8'h25; frame1.valid[58] = 1'b1; frame1.error[58] = 1'b0; - frame1.data[59] = 8'h26; frame1.valid[59] = 1'b1; frame1.error[59] = 1'b0; - frame1.data[60] = 8'h27; frame1.valid[60] = 1'b1; frame1.error[60] = 1'b0; - frame1.data[61] = 8'h28; frame1.valid[61] = 1'b1; frame1.error[61] = 1'b0; - frame1.data[62] = 8'h29; frame1.valid[62] = 1'b1; frame1.error[62] = 1'b0; - frame1.data[63] = 8'h2a; frame1.valid[63] = 1'b1; frame1.error[63] = 1'b0; - frame1.data[64] = 8'h2b; frame1.valid[64] = 1'b1; frame1.error[64] = 1'b0; - frame1.data[65] = 8'h2c; frame1.valid[65] = 1'b1; frame1.error[65] = 1'b0; - frame1.data[66] = 8'h2d; frame1.valid[66] = 1'b1; frame1.error[66] = 1'b0; - frame1.data[67] = 8'h2e; frame1.valid[67] = 1'b1; frame1.error[67] = 1'b0; - frame1.data[68] = 8'h2f; frame1.valid[68] = 1'b1; frame1.error[68] = 1'b0; - frame1.data[69] = 8'h33; frame1.valid[69] = 1'b1; frame1.error[69] = 1'b0; // FCS field - frame1.data[70] = 8'ha9; frame1.valid[70] = 1'b1; frame1.error[70] = 1'b0; - frame1.data[71] = 8'haf; frame1.valid[71] = 1'b1; frame1.error[71] = 1'b0; - frame1.data[72] = 8'h1d; frame1.valid[72] = 1'b1; frame1.error[72] = 1'b0; - frame1.data[73] = 8'h00; frame1.valid[73] = 1'b0; frame1.error[73] = 1'b0; - - // frame 2... - frame2.data[0] = 8'h55; frame2.valid[0] = 1'b1; frame2.error[0] = 1'b0; // Preamble - frame2.data[1] = 8'h55; frame2.valid[1] = 1'b1; frame2.error[1] = 1'b0; - frame2.data[2] = 8'h55; frame2.valid[2] = 1'b1; frame2.error[2] = 1'b0; - frame2.data[3] = 8'h55; frame2.valid[3] = 1'b1; frame2.error[3] = 1'b0; - frame2.data[4] = 8'h55; frame2.valid[4] = 1'b1; frame2.error[4] = 1'b0; - frame2.data[5] = 8'h55; frame2.valid[5] = 1'b1; frame2.error[5] = 1'b0; - frame2.data[6] = 8'h55; frame2.valid[6] = 1'b1; frame2.error[6] = 1'b0; - frame2.data[7] = 8'hd5; frame2.valid[7] = 1'b1; frame2.error[7] = 1'b0; // SFD - frame2.data[8] = 8'hda; frame2.valid[8] = 1'b1; frame2.error[8] = 1'b0; // Destination Address (DA) - frame2.data[9] = 8'h02; frame2.valid[9] = 1'b1; frame2.error[9] = 1'b0; - frame2.data[10] = 8'h03; frame2.valid[10] = 1'b1; frame2.error[10] = 1'b0; - frame2.data[11] = 8'h04; frame2.valid[11] = 1'b1; frame2.error[11] = 1'b0; - frame2.data[12] = 8'h05; frame2.valid[12] = 1'b1; frame2.error[12] = 1'b0; - frame2.data[13] = 8'h06; frame2.valid[13] = 1'b1; frame2.error[13] = 1'b0; - frame2.data[14] = 8'h5a; frame2.valid[14] = 1'b1; frame2.error[14] = 1'b0; // Source Address (5A) - frame2.data[15] = 8'h02; frame2.valid[15] = 1'b1; frame2.error[15] = 1'b0; - frame2.data[16] = 8'h03; frame2.valid[16] = 1'b1; frame2.error[16] = 1'b0; - frame2.data[17] = 8'h04; frame2.valid[17] = 1'b1; frame2.error[17] = 1'b0; - frame2.data[18] = 8'h05; frame2.valid[18] = 1'b1; frame2.error[18] = 1'b0; - frame2.data[19] = 8'h06; frame2.valid[19] = 1'b1; frame2.error[19] = 1'b0; - frame2.data[20] = 8'h00; frame2.valid[20] = 1'b1; frame2.error[20] = 1'b0; - frame2.data[21] = 8'h2e; frame2.valid[21] = 1'b1; frame2.error[21] = 1'b0; // Length/Type = Length = 46 - frame2.data[22] = 8'h01; frame2.valid[22] = 1'b1; frame2.error[22] = 1'b0; - frame2.data[23] = 8'h02; frame2.valid[23] = 1'b1; frame2.error[23] = 1'b0; // Data - frame2.data[24] = 8'h03; frame2.valid[24] = 1'b1; frame2.error[24] = 1'b0; - frame2.data[25] = 8'h04; frame2.valid[25] = 1'b1; frame2.error[25] = 1'b0; - frame2.data[26] = 8'h05; frame2.valid[26] = 1'b1; frame2.error[26] = 1'b0; - frame2.data[27] = 8'h06; frame2.valid[27] = 1'b1; frame2.error[27] = 1'b0; - frame2.data[28] = 8'h07; frame2.valid[28] = 1'b1; frame2.error[28] = 1'b0; - frame2.data[29] = 8'h08; frame2.valid[29] = 1'b1; frame2.error[29] = 1'b0; - frame2.data[30] = 8'h09; frame2.valid[30] = 1'b1; frame2.error[30] = 1'b0; - frame2.data[31] = 8'h0a; frame2.valid[31] = 1'b1; frame2.error[31] = 1'b0; - frame2.data[32] = 8'h0b; frame2.valid[32] = 1'b1; frame2.error[32] = 1'b0; - frame2.data[33] = 8'h0c; frame2.valid[33] = 1'b1; frame2.error[33] = 1'b0; - frame2.data[34] = 8'h0d; frame2.valid[34] = 1'b1; frame2.error[34] = 1'b0; - frame2.data[35] = 8'h0e; frame2.valid[35] = 1'b1; frame2.error[35] = 1'b0; - frame2.data[36] = 8'h0f; frame2.valid[36] = 1'b1; frame2.error[36] = 1'b0; - frame2.data[37] = 8'h10; frame2.valid[37] = 1'b1; frame2.error[37] = 1'b0; - frame2.data[38] = 8'h11; frame2.valid[38] = 1'b1; frame2.error[38] = 1'b0; - frame2.data[39] = 8'h12; frame2.valid[39] = 1'b1; frame2.error[39] = 1'b0; - frame2.data[40] = 8'h13; frame2.valid[40] = 1'b1; frame2.error[40] = 1'b0; - frame2.data[41] = 8'h14; frame2.valid[41] = 1'b1; frame2.error[41] = 1'b0; - frame2.data[42] = 8'h15; frame2.valid[42] = 1'b1; frame2.error[42] = 1'b0; - frame2.data[43] = 8'h16; frame2.valid[43] = 1'b1; frame2.error[43] = 1'b0; - frame2.data[44] = 8'h17; frame2.valid[44] = 1'b1; frame2.error[44] = 1'b0; - frame2.data[45] = 8'h18; frame2.valid[45] = 1'b1; frame2.error[45] = 1'b0; - frame2.data[46] = 8'h19; frame2.valid[46] = 1'b1; frame2.error[46] = 1'b0; - frame2.data[47] = 8'h1a; frame2.valid[47] = 1'b1; frame2.error[47] = 1'b1; // Signal an Error - frame2.data[48] = 8'h1b; frame2.valid[48] = 1'b1; frame2.error[48] = 1'b0; - frame2.data[49] = 8'h1c; frame2.valid[49] = 1'b1; frame2.error[49] = 1'b0; - frame2.data[50] = 8'h1d; frame2.valid[50] = 1'b1; frame2.error[50] = 1'b0; - frame2.data[51] = 8'h1e; frame2.valid[51] = 1'b1; frame2.error[51] = 1'b0; - frame2.data[52] = 8'h1f; frame2.valid[52] = 1'b1; frame2.error[52] = 1'b0; - frame2.data[53] = 8'h20; frame2.valid[53] = 1'b1; frame2.error[53] = 1'b0; - frame2.data[54] = 8'h21; frame2.valid[54] = 1'b1; frame2.error[54] = 1'b0; - frame2.data[55] = 8'h22; frame2.valid[55] = 1'b1; frame2.error[55] = 1'b0; - frame2.data[56] = 8'h23; frame2.valid[56] = 1'b1; frame2.error[56] = 1'b0; - frame2.data[57] = 8'h24; frame2.valid[57] = 1'b1; frame2.error[57] = 1'b0; - frame2.data[58] = 8'h25; frame2.valid[58] = 1'b1; frame2.error[58] = 1'b0; - frame2.data[59] = 8'h26; frame2.valid[59] = 1'b1; frame2.error[59] = 1'b0; - frame2.data[60] = 8'h27; frame2.valid[60] = 1'b1; frame2.error[60] = 1'b0; - frame2.data[61] = 8'h28; frame2.valid[61] = 1'b1; frame2.error[61] = 1'b0; - frame2.data[62] = 8'h29; frame2.valid[62] = 1'b1; frame2.error[62] = 1'b0; - frame2.data[63] = 8'h2a; frame2.valid[63] = 1'b1; frame2.error[63] = 1'b0; - frame2.data[64] = 8'h2b; frame2.valid[64] = 1'b1; frame2.error[64] = 1'b0; - frame2.data[65] = 8'h2c; frame2.valid[65] = 1'b1; frame2.error[65] = 1'b0; - frame2.data[66] = 8'h2d; frame2.valid[66] = 1'b1; frame2.error[66] = 1'b0; - frame2.data[67] = 8'h2e; frame2.valid[67] = 1'b1; frame2.error[67] = 1'b0; - frame2.data[68] = 8'h14; frame2.valid[68] = 1'b1; frame2.error[68] = 1'b0; // FCS field - frame2.data[69] = 8'h19; frame2.valid[69] = 1'b1; frame2.error[69] = 1'b0; - frame2.data[70] = 8'hd1; frame2.valid[70] = 1'b1; frame2.error[70] = 1'b0; - frame2.data[71] = 8'hdd; frame2.valid[71] = 1'b1; frame2.error[71] = 1'b0; - frame2.data[72] = 8'h00; frame2.valid[72] = 1'b0; frame2.error[72] = 1'b0; - frame2.data[73] = 8'h00; frame2.valid[73] = 1'b0; frame2.error[73] = 1'b0; - - // frame 3... - frame3.data[0] = 8'h55; frame3.valid[0] = 1'b1; frame3.error[0] = 1'b0; // Preamble - frame3.data[1] = 8'h55; frame3.valid[1] = 1'b1; frame3.error[1] = 1'b0; - frame3.data[2] = 8'h55; frame3.valid[2] = 1'b1; frame3.error[2] = 1'b0; - frame3.data[3] = 8'h55; frame3.valid[3] = 1'b1; frame3.error[3] = 1'b0; - frame3.data[4] = 8'h55; frame3.valid[4] = 1'b1; frame3.error[4] = 1'b0; - frame3.data[5] = 8'h55; frame3.valid[5] = 1'b1; frame3.error[5] = 1'b0; - frame3.data[6] = 8'h55; frame3.valid[6] = 1'b1; frame3.error[6] = 1'b0; - frame3.data[7] = 8'hd5; frame3.valid[7] = 1'b1; frame3.error[7] = 1'b0; // SFD - frame3.data[8] = 8'hda; frame3.valid[8] = 1'b1; frame3.error[8] = 1'b0; // Destination Address (DA) - frame3.data[9] = 8'h02; frame3.valid[9] = 1'b1; frame3.error[9] = 1'b0; - frame3.data[10] = 8'h03; frame3.valid[10] = 1'b1; frame3.error[10] = 1'b0; - frame3.data[11] = 8'h04; frame3.valid[11] = 1'b1; frame3.error[11] = 1'b0; - frame3.data[12] = 8'h05; frame3.valid[12] = 1'b1; frame3.error[12] = 1'b0; - frame3.data[13] = 8'h06; frame3.valid[13] = 1'b1; frame3.error[13] = 1'b0; - frame3.data[14] = 8'h5a; frame3.valid[14] = 1'b1; frame3.error[14] = 1'b0; // Source Address (5A) - frame3.data[15] = 8'h02; frame3.valid[15] = 1'b1; frame3.error[15] = 1'b0; - frame3.data[16] = 8'h03; frame3.valid[16] = 1'b1; frame3.error[16] = 1'b0; - frame3.data[17] = 8'h04; frame3.valid[17] = 1'b1; frame3.error[17] = 1'b0; - frame3.data[18] = 8'h05; frame3.valid[18] = 1'b1; frame3.error[18] = 1'b0; - frame3.data[19] = 8'h06; frame3.valid[19] = 1'b1; frame3.error[19] = 1'b0; - frame3.data[20] = 8'h00; frame3.valid[20] = 1'b1; frame3.error[20] = 1'b0; - frame3.data[21] = 8'h03; frame3.valid[21] = 1'b1; frame3.error[21] = 1'b0; // Length/Type = Length = 3 - frame3.data[22] = 8'h01; frame3.valid[22] = 1'b1; frame3.error[22] = 1'b0; // Therefore padding is required - frame3.data[23] = 8'h02; frame3.valid[23] = 1'b1; frame3.error[23] = 1'b0; - frame3.data[24] = 8'h03; frame3.valid[24] = 1'b1; frame3.error[24] = 1'b0; - frame3.data[25] = 8'h00; frame3.valid[25] = 1'b1; frame3.error[25] = 1'b0; // Padding (uses zero value bytes) - frame3.data[26] = 8'h00; frame3.valid[26] = 1'b1; frame3.error[26] = 1'b0; - frame3.data[27] = 8'h00; frame3.valid[27] = 1'b1; frame3.error[27] = 1'b0; - frame3.data[28] = 8'h00; frame3.valid[28] = 1'b1; frame3.error[28] = 1'b0; - frame3.data[29] = 8'h00; frame3.valid[29] = 1'b1; frame3.error[29] = 1'b0; - frame3.data[30] = 8'h00; frame3.valid[30] = 1'b1; frame3.error[30] = 1'b0; - frame3.data[31] = 8'h00; frame3.valid[31] = 1'b1; frame3.error[31] = 1'b0; - frame3.data[32] = 8'h00; frame3.valid[32] = 1'b1; frame3.error[32] = 1'b0; - frame3.data[33] = 8'h00; frame3.valid[33] = 1'b1; frame3.error[33] = 1'b0; - frame3.data[34] = 8'h00; frame3.valid[34] = 1'b1; frame3.error[34] = 1'b0; - frame3.data[35] = 8'h00; frame3.valid[35] = 1'b1; frame3.error[35] = 1'b0; - frame3.data[36] = 8'h00; frame3.valid[36] = 1'b1; frame3.error[36] = 1'b0; - frame3.data[37] = 8'h00; frame3.valid[37] = 1'b1; frame3.error[37] = 1'b0; - frame3.data[38] = 8'h00; frame3.valid[38] = 1'b1; frame3.error[38] = 1'b0; - frame3.data[39] = 8'h00; frame3.valid[39] = 1'b1; frame3.error[39] = 1'b0; - frame3.data[40] = 8'h00; frame3.valid[40] = 1'b1; frame3.error[40] = 1'b0; - frame3.data[41] = 8'h00; frame3.valid[41] = 1'b1; frame3.error[41] = 1'b0; - frame3.data[42] = 8'h00; frame3.valid[42] = 1'b1; frame3.error[42] = 1'b0; - frame3.data[43] = 8'h00; frame3.valid[43] = 1'b1; frame3.error[43] = 1'b0; - frame3.data[44] = 8'h00; frame3.valid[44] = 1'b1; frame3.error[44] = 1'b0; - frame3.data[45] = 8'h00; frame3.valid[45] = 1'b1; frame3.error[45] = 1'b0; - frame3.data[46] = 8'h00; frame3.valid[46] = 1'b1; frame3.error[46] = 1'b0; - frame3.data[47] = 8'h00; frame3.valid[47] = 1'b1; frame3.error[47] = 1'b0; - frame3.data[48] = 8'h00; frame3.valid[48] = 1'b1; frame3.error[48] = 1'b0; - frame3.data[49] = 8'h00; frame3.valid[49] = 1'b1; frame3.error[49] = 1'b0; - frame3.data[50] = 8'h00; frame3.valid[50] = 1'b1; frame3.error[50] = 1'b0; - frame3.data[51] = 8'h00; frame3.valid[51] = 1'b1; frame3.error[51] = 1'b0; - frame3.data[52] = 8'h00; frame3.valid[52] = 1'b1; frame3.error[52] = 1'b0; - frame3.data[53] = 8'h00; frame3.valid[53] = 1'b1; frame3.error[53] = 1'b0; - frame3.data[54] = 8'h00; frame3.valid[54] = 1'b1; frame3.error[54] = 1'b0; - frame3.data[55] = 8'h00; frame3.valid[55] = 1'b1; frame3.error[55] = 1'b0; - frame3.data[56] = 8'h00; frame3.valid[56] = 1'b1; frame3.error[56] = 1'b0; - frame3.data[57] = 8'h00; frame3.valid[57] = 1'b1; frame3.error[57] = 1'b0; - frame3.data[58] = 8'h00; frame3.valid[58] = 1'b1; frame3.error[58] = 1'b0; - frame3.data[59] = 8'h00; frame3.valid[59] = 1'b1; frame3.error[59] = 1'b0; - frame3.data[60] = 8'h00; frame3.valid[60] = 1'b1; frame3.error[60] = 1'b0; - frame3.data[61] = 8'h00; frame3.valid[61] = 1'b1; frame3.error[61] = 1'b0; - frame3.data[62] = 8'h00; frame3.valid[62] = 1'b1; frame3.error[62] = 1'b0; - frame3.data[63] = 8'h00; frame3.valid[63] = 1'b1; frame3.error[63] = 1'b0; - frame3.data[64] = 8'h00; frame3.valid[64] = 1'b1; frame3.error[64] = 1'b0; - frame3.data[65] = 8'h00; frame3.valid[65] = 1'b1; frame3.error[65] = 1'b0; - frame3.data[66] = 8'h00; frame3.valid[66] = 1'b1; frame3.error[66] = 1'b0; - frame3.data[67] = 8'h00; frame3.valid[67] = 1'b1; frame3.error[67] = 1'b0; - frame3.data[68] = 8'h73; frame3.valid[68] = 1'b1; frame3.error[68] = 1'b0; // FCS field - frame3.data[69] = 8'h00; frame3.valid[69] = 1'b1; frame3.error[69] = 1'b0; - frame3.data[70] = 8'h75; frame3.valid[70] = 1'b1; frame3.error[70] = 1'b0; - frame3.data[71] = 8'h22; frame3.valid[71] = 1'b1; frame3.error[71] = 1'b0; - frame3.data[72] = 8'h00; frame3.valid[72] = 1'b0; frame3.error[72] = 1'b0; - frame3.data[73] = 8'h00; frame3.valid[73] = 1'b0; frame3.error[73] = 1'b0; - - end - - //---------------------------------------------------------------------------- - // testbench signals - //---------------------------------------------------------------------------- - - // signals for the Tx monitor following 8B10B decode - reg [7:0] tx_pdata; - reg tx_is_k; - wire clock_enable; // SGMII mode only: Used to create data at different rates - reg stim_tx_clk; // Transmitter clock (stimulus process). - wire mon_tx_clk; // Transmitter clock (monitor process). - - // signals for the Rx stimulus prior to 8B10B encode - reg [7:0] rx_pdata; - reg rx_is_k; - reg rx_even; // Keep track of the even/odd position - reg rx_rundisp_pos; // Indicates +ve running disparity - reg stim_rx_clk; // Receiver clock (stimulus process). - wire mon_rx_clk; // Receiver clock (monitor process). - reg bitclock; // clock running at Transceiver serial frequency - - - //---------------------------------------------------------------------------- - // Clock drivers - //---------------------------------------------------------------------------- - - initial // drives Rx stimulus clock at 125 MHz - begin - stim_rx_clk <= 1'b0; - forever - begin - stim_rx_clk <= 1'b0; - #4000; - stim_rx_clk <= 1'b1; - #4000; - end - end - - initial // drives stim_tx_clk at 125 MH - begin - stim_tx_clk <= 1'b0; - forever - begin - stim_tx_clk <= 1'b0; - #4000; - stim_tx_clk <= 1'b1; - #4000; - end - end - - assign gmii_tx_clk = stim_tx_clk; - - initial // drives bitclock at 1.25GHz - begin - bitclock <= 1'b0; - forever - begin - bitclock <= 1'b0; - #(UI/2); - bitclock <= 1'b1; - #(UI/2); - end - end - - - - // monitor clock for the GMII receiver. - assign mon_rx_clk = gmii_rx_clk; - - - - //---------------------------------------------------------------------------- - // Tx stimulus process. This process will push frames of data into the - // GMII transmitter side of the PCS/PMA core. - //---------------------------------------------------------------------------- - - // A task to inject the current frame - task tx_stimulus_send_frame; - input `FRAME_TYP frame; - integer column_index; - integer I; - begin - // import the frame into scratch space - tx_stimulus_working_frame.frombits(frame); - - column_index = 0; - gmii_txd <= 8'h0; - gmii_tx_en <= 1'b0; - gmii_tx_er <= 1'b0; - - // loop over columns in frame. - while (tx_stimulus_working_frame.valid[column_index] != 1'b0) - begin - gmii_txd <= tx_stimulus_working_frame.data[column_index]; - gmii_tx_en <= tx_stimulus_working_frame.valid[column_index]; - gmii_tx_er <= tx_stimulus_working_frame.error[column_index]; - @(negedge stim_tx_clk); // wait for next clock tick - column_index = column_index + 1; - end - - // Clear the data lines. - gmii_txd <= 8'h0; - gmii_tx_en <= 1'b0; - gmii_tx_er <= 1'b0; - - for (I = 0; I < 12; I = I + 1) // delay to create Inter Packet Gap. - @(negedge stim_tx_clk); - - end - endtask // tx_stimulus_send_frame - - - - // loop over all the frames in the stimulus vector - initial - begin : p_tx_stimulus - - gmii_txd <= 8'h00; - gmii_tx_en <= 1'b0; - gmii_tx_er <= 1'b0; - - // Wait for the configuration process to finish - wait (configuration_finished == 1); - - $display("Tx Stimulus %d: sending 4 frames ... ", INSTANCE_NUMBER); - - // Transmit four frames through the GMII transmit interface. - // -- frame 0 = standard frame - // -- frame 1 = type frame - // -- frame 2 = frame containing an error - // -- frame 3 = standard frame with padding - - @(negedge stim_tx_clk) - tx_stimulus_send_frame(frame0.tobits(0)); - tx_stimulus_send_frame(frame1.tobits(0)); - tx_stimulus_send_frame(frame2.tobits(0)); - tx_stimulus_send_frame(frame3.tobits(0)); - - end // p_tx_stimulus - - - - //---------------------------------------------------------------------------- - // The Phy side serial transmitter output from the core is captured, - // converted to 10-bit parallel and 8B10B decoded. Correct Parallel - // alignment is achieved using comma detection. - //---------------------------------------------------------------------------- - - // The transmitter monitor clock will be the same frequency as the - // receiver monitor clock due to the Transceiver Rx Elastic Buffer. - assign mon_tx_clk = gmii_rx_clk; - - initial - begin : p_tx_decode - - reg [0:9] code_buffer; - reg [7:0] decoded_data; - integer bit_count; - reg is_k_var; - reg initial_sync; - - bit_count = 0; - initial_sync = 0; - - forever - begin - @(posedge bitclock); - code_buffer = {code_buffer[1:9], txp}; - // comma detection - if (is_comma(code_buffer)) - begin - bit_count = 0; - initial_sync = 1; - end - - if (bit_count == 0 && initial_sync) - begin - // Perform 8B10B decoding of the data stream - decode_8b10b(code_buffer, - decoded_data, - is_k_var); - - // drive the output signals with the results - tx_pdata <= decoded_data; - - if (is_k_var) - tx_is_k <= 1'b1; - else - tx_is_k <= 1'b0; - end - - if (initial_sync) - begin - bit_count = bit_count + 1; - if (bit_count == 10) - bit_count = 0; - end - - end // forever - end // p_tx_decode - - - - - //---------------------------------------------------------------------------- - // Tx Monitor process. This process checks the frames coming out - // of the transmitter PHY side interface to make sure that they match - // those injected into the transmitter GMII. - //---------------------------------------------------------------------------- - - // A procedure to compare the current frame being transmitted with the injected frame - task tx_monitor_check_frame; - input `FRAME_TYP frame; - input integer frame_number; - integer column_index; - begin - $timeformat(-9, 0, "ns", 7); - - tx_monitor_working_frame.frombits(frame); - column_index = 0; - - // Detect the Start of Frame - while (tx_pdata !== 8'hFB) - @(posedge mon_tx_clk); - - // Move past the Start of Frame code to the 1st byte of preamble - while (!clock_enable) - @(posedge mon_tx_clk); - @(posedge mon_tx_clk); - - // wait until the SFD code is detected. - // NOTE: It is neccessary to resynchronise on the SFD as the preamble field - // may have shrunk. - while (tx_pdata !== 8'hD5) begin - if (tx_pdata !== tx_monitor_working_frame.data[column_index]) - $display("** Error: Tx Monitor %d: data incorrect during the preamble of frame at %t", INSTANCE_NUMBER, $realtime); - - // wait for next column of data - column_index = column_index + 1; - while (!clock_enable) - @(posedge mon_tx_clk); - @(posedge mon_tx_clk); - end - - // tx_pdata should now hold the SFD. We need to move to the SFD of the injected frame. - while (tx_monitor_working_frame.data[column_index] !== 8'hD5) - column_index = column_index + 1; - - // Start comparing transmitted frame data to the injected frame data - $display("Tx Monitor %d: Comparing transmitted frame with injected frame %d", INSTANCE_NUMBER, frame_number); - - // frame has started, loop over columns of frame until the frame termination is detected - while (tx_pdata !== 8'hFD | tx_is_k != 1'b1) // /K29.7/ character - begin - if (tx_pdata !== 8'hFE && tx_is_k != 1'b1) begin // Do not check the data if an error code has been inserted (/K30.7 character). - if (clock_enable) begin - if (tx_pdata !== tx_monitor_working_frame.data[column_index]) begin - $display("** Error: Tx Monitor %d: data incorrect during frame at %t", INSTANCE_NUMBER, $realtime); - end - end - end - - // wait for next column of data - @(posedge mon_tx_clk); - if (clock_enable) begin - column_index = column_index + 1; - end - end - end - endtask // tx_monitor_check_frame - - - - // loop over all the frames in the stimulus vector - initial - begin : p_tx_monitor - tx_monitor_finished <= 0; - - // Compare the transmitted frames to the injected frames - // -- frame 0 = standard frame - // -- frame 1 = type frame - // -- frame 2 = frame containing an error - // -- frame 3 = standard frame with padding - - #1000000 - - // then get synced up with the clock - @(posedge mon_tx_clk) - - // parse all the frames in the stimulus vector - tx_monitor_check_frame(frame0.tobits(0), 0); - tx_monitor_check_frame(frame1.tobits(0), 1); - tx_monitor_check_frame(frame2.tobits(0), 2); - tx_monitor_check_frame(frame3.tobits(0), 3); - - #200000 - tx_monitor_finished <= 1; - - end // p_tx_monitor - - - - //---------------------------------------------------------------------------- - // Rx stimulus process. This process will create frames of data to be - // pushed into the receiver PHY side of the PCS/PMA core. - //---------------------------------------------------------------------------- - - // For 1000BASE-X, this demo_tb will only generate traffic at 1Gb/s - assign clock_enable = 1'b1; - - // A task to create an Idle /I1/ code group - task send_I1; - begin - rx_pdata <= 8'hBC; // /K28.5/ - rx_is_k <= 1'b1; - @(posedge stim_rx_clk); - rx_pdata <= 8'hC5; // /D5.6/ - rx_is_k <= 1'b0; - @(posedge stim_rx_clk); - end - endtask // send_I1; - - // A task to create an Idle /I2/ code group - task send_I2; - begin - rx_pdata <= 8'hBC; // /K28.5/ - rx_is_k <= 1'b1; - @(posedge stim_rx_clk); - rx_pdata <= 8'h50; // /D16.2/ - rx_is_k <= 1'b0; - @(posedge stim_rx_clk); - end - endtask // send_I2; - - // A task to create a Start of Packet /S/ code group - task send_S; - begin - rx_pdata <= 8'hFB; // /K27.7/ - rx_is_k <= 1'b1; - @(posedge stim_rx_clk); - end - endtask // send_S; - - // A task to create a Terminate /T/ code group - task send_T; - begin - rx_pdata <= 8'hFD; // /K29.7/ - rx_is_k <= 1'b1; - @(posedge stim_rx_clk); - end - endtask // send_T; - - // A task to create a Carrier Extend /R/ code group - task send_R; - begin - rx_pdata <= 8'hF7; // /K23.7/ - rx_is_k <= 1'b1; - @(posedge stim_rx_clk); - end - endtask // send_R; - - // A task to create an Error Propogation /V/ code group - task send_V; - begin - rx_pdata <= 8'hFE; // /K30.7/ - rx_is_k <= 1'b1; - while (!clock_enable) - @(posedge stim_rx_clk); - @(posedge stim_rx_clk); - end - endtask // send_V; - - - - // A task to inject the current frame - task rx_stimulus_send_frame; - input `FRAME_TYP frame; - integer column_index; - integer I; - begin - // import the frame into scratch space - rx_stimulus_working_frame.frombits(frame); - - //---------------------------------- - // Send a Start of Packet code group - //---------------------------------- - send_S; - - //---------------------------------- - // Send frame data - //---------------------------------- - column_index = 1; - - // loop over columns in frame - while (rx_stimulus_working_frame.valid[column_index] != 1'b0) begin - if (rx_stimulus_working_frame.error[column_index] == 1'b1) - send_V; // insert an error propogation code group - else - begin - rx_pdata <= rx_stimulus_working_frame.data[column_index]; - rx_is_k <= 1'b0; - while (!clock_enable) - @(posedge stim_rx_clk); - @(posedge stim_rx_clk); - end - column_index = column_index + 1; - end // while - - //---------------------------------- - // Send a frame termination sequence - //---------------------------------- - send_T; // Terminate code group - send_R; // Carrier Extend code group - - // An extra Carrier Extend code group should be sent to end the frame - // on an even boundary. - if (rx_even == 1'b1) - send_R; // Carrier Extend code group - - //---------------------------------- - // Send an Inter Packet Gap. - //---------------------------------- - // The initial Idle following a frame should be chosen to ensure - // that the running disparity is returned to -ve. - if (rx_rundisp_pos == 1'b1) - send_I1; // /I1/ will flip the running disparity - else - send_I2; // /I2/ will maintain the running disparity - - // The remainder of the IPG is made up of /I2/ 's. - for (I = 0; I < 4; I = I + 1) - send_I2; - - end - endtask // rx_stimulus_send_frame; - - - - //---------------------------------------------------------------------------- - // loop over all the frames in the stimulus vector - //---------------------------------------------------------------------------- - initial - begin : p_rx_stimulus - - // Initialise stimulus - rx_rundisp_pos <= 0; // Initialise running disparity - rx_pdata <= 8'hBC; // /K28.5/ - rx_is_k <= 1'b1; - - // Wait for the Management MDIO transaction to finish. - while (configuration_finished !== 1) - send_I2; - - // Inject four frames into the receiver PHY interface - // -- frame 0 = standard frame - // -- frame 1 = type frame - // -- frame 2 = frame containing an error - // -- frame 3 = standard frame with padding - $display("Rx Stimulus %d: sending 4 frames ...", INSTANCE_NUMBER); - - rx_stimulus_send_frame(frame0.tobits(0)); - rx_stimulus_send_frame(frame1.tobits(0)); - rx_stimulus_send_frame(frame2.tobits(0)); - rx_stimulus_send_frame(frame3.tobits(0)); - - forever - send_I2; - - end // p_rx_stimulus - - - - //---------------------------------------------------------------------------- - // A process to keep track of the even/odd code group position for the - // injected receiver code groups. - //---------------------------------------------------------------------------- - - initial - begin : p_rx_even_odd - rx_even <= 1'b1; - forever - begin - @(posedge stim_rx_clk) - rx_even <= ! rx_even; - end - end // p_rx_even_odd - - - //---------------------------------------------------------------------------- - // Data from the Rx Stimulus is 8B10B encoded and serialised so that - // it can be injected into the Transceiver receiver port. - //---------------------------------------------------------------------------- - - // A task to serialise a single 10-bit code group - task rx_stimulus_send_10b_column; - input [0:9] d; - integer I; - begin - for (I = 0; I < 10; I = I + 1) - begin - @(posedge bitclock) - rxp <= d[I]; - rxn <= ~d[I]; - end // I - end - endtask // rx_stimulus_send_10b_column - - - // 8B10B encode the Rx stimulus - initial - begin : p_rx_encode - reg [0:9] encoded_data; - - // Get synced up with the Rx clock - @(posedge stim_rx_clk) - - // Perform 8B10B encoding of the data stream - forever - begin - encode_8b10b( - rx_pdata, - rx_is_k, - encoded_data, - rx_rundisp_pos, - rx_rundisp_pos); - - rx_stimulus_send_10b_column(encoded_data); - end // forever - end // p_rx_encode - - - - //---------------------------------------------------------------------------- - // Rx monitor process. This process checks the data coming out of the - // receiver GMII to make sure that it matches that injected into the - // PHY. - //---------------------------------------------------------------------------- - - - // A task to compare the current frame being received with the injected frame - task rx_monitor_check_frame; - input `FRAME_TYP frame; - input integer frame_number; - integer column_index; - - begin - $timeformat(-9, 0, "ns", 7); - - // import the frame into scratch space - rx_monitor_working_frame.frombits(frame); - - column_index = 0; - - // Wait until GMII_RX_DV has a real value, i.e. not 'X'/'Z' - while (gmii_rx_dv !== 1'b0) - @(posedge mon_rx_clk); - - // wait for the first real column of data to come out of Rx GMII - while (gmii_rx_dv === 1'b0) - @(posedge mon_rx_clk); - - $display("Rx Monitor %d: Comparing received frame with injected frame %d", INSTANCE_NUMBER, frame_number); - - // wait until the SFD code is detected on GMII_RXD(7 downto 0). - // NOTE: It is neccessary to resynchronise on the SFD as the preamble field - // may have shrunk. - while (gmii_rxd !== 8'hd5) begin - if (gmii_rx_dv !== rx_monitor_working_frame.valid[column_index]) - $display("** Error: Rx Monitor %d: gmii_rx_dv incorrect during preamble at %t", INSTANCE_NUMBER, $realtime); - - if (gmii_rx_er !== rx_monitor_working_frame.error[column_index]) - $display("** Error: Rx Monitor %d: gmii_rx_er incorrect during preamble at %t", INSTANCE_NUMBER, $realtime); - - if (gmii_rxd !== rx_monitor_working_frame.data[column_index]) - $display("** Error: Rx Monitor %d: gmii_rxd incorrect during preamble at %t", INSTANCE_NUMBER, $realtime); - - column_index = column_index + 1; - - // wait for next column of data - @(posedge mon_rx_clk); - end - - // gmii_rxd should now hold the SFD. We need to move to the SFD of the injected frame. - while (rx_monitor_working_frame.data[column_index] !== 8'hD5) - column_index = column_index + 1; - - // Start comparing received data to injected data - while (gmii_rx_dv !== 1'b0) - begin - if (gmii_rx_dv !== rx_monitor_working_frame.valid[column_index]) - $display("** Error: Rx Monitor %d: gmii_rx_dv incorrect at %t", INSTANCE_NUMBER, $realtime); - - if (gmii_rx_er !== rx_monitor_working_frame.error[column_index]) - $display("** Error: Rx Monitor %d: gmii_rx_er incorrect at %t", INSTANCE_NUMBER, $realtime); - - if (gmii_rxd !== rx_monitor_working_frame.data[column_index]) - begin - if (gmii_rx_er == 1'b0) // do not check the data if an error code has been inserted. - $display("** Error: Rx Monitor %d: gmii_rxd incorrect at %t", INSTANCE_NUMBER, $realtime); - end - - column_index = column_index + 1; - - // wait for next column of data - @(posedge mon_rx_clk); - end - end - endtask // rx_monitor_check_frame - - - - //---------------------------------------------------------------------------- - // loop over all the frames in the stimulus vector - //---------------------------------------------------------------------------- - initial - begin : p_rx_monitor - rx_monitor_finished <= 0; - - // Compare the received frames to the injected frames - // -- frame 0 = standard frame - // -- frame 1 = type frame - // -- frame 2 = frame containing an error - // -- frame 3 = standard frame with padding - - #1000000 - - // then get synced up with the RX clock - @(posedge mon_rx_clk) - - // parse all the frames in the stimulus vector - rx_monitor_check_frame(frame0.tobits(0), 0); - rx_monitor_check_frame(frame1.tobits(0), 1); - rx_monitor_check_frame(frame2.tobits(0), 2); - rx_monitor_check_frame(frame3.tobits(0), 3); - - #200000 - rx_monitor_finished <= 1; - end // p_rx_monitor - - - -endmodule - diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp_flist.txt b/fpga/usrp3/top/x300/coregen/gige_sfp_flist.txt deleted file mode 100644 index 68ff0028f..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp_flist.txt +++ /dev/null @@ -1,43 +0,0 @@ -# Output products list for -_xmsgs/pn_parser.xmsgs -gige_sfp/doc/gig_eth_pcs_pma_v11_4_vinfo.html -gige_sfp/doc/pg047-gig-eth-pcs-pma.pdf -gige_sfp/example_design/gige_sfp_block.v -gige_sfp/example_design/gige_sfp_example_design.ucf -gige_sfp/example_design/gige_sfp_example_design.v -gige_sfp/example_design/gige_sfp_example_design.xdc -gige_sfp/example_design/gige_sfp_mod.v -gige_sfp/example_design/gige_sfp_reset_sync.v -gige_sfp/example_design/gige_sfp_sync_block.v -gige_sfp/example_design/gige_sfp_tx_elastic_buffer.v -gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v -gige_sfp/example_design/transceiver/gige_sfp_gtwizard.xco -gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v -gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v -gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v -gige_sfp/example_design/transceiver/gige_sfp_transceiver.v -gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v -gige_sfp/gig_eth_pcs_pma_readme.txt -gige_sfp/implement/example_design_xst.xcf -gige_sfp/implement/implement.bat -gige_sfp/implement/implement.sh -gige_sfp/implement/xst.prj -gige_sfp/implement/xst.scr -gige_sfp/simulation/demo_tb.v -gige_sfp/simulation/functional/simulate_mti.do -gige_sfp/simulation/functional/simulate_ncsim.sh -gige_sfp/simulation/functional/simulate_vcs.sh -gige_sfp/simulation/functional/ucli_commands.key -gige_sfp/simulation/functional/vcs_session.tcl -gige_sfp/simulation/functional/wave_mti.do -gige_sfp/simulation/functional/wave_ncsim.sv -gige_sfp/simulation/stimulus_tb.v -gige_sfp.asy -gige_sfp.gise -gige_sfp.ngc -gige_sfp.v -gige_sfp.veo -gige_sfp.xco -gige_sfp.xise -gige_sfp_flist.txt -gige_sfp_xmdf.tcl diff --git a/fpga/usrp3/top/x300/coregen/gige_sfp_xmdf.tcl b/fpga/usrp3/top/x300/coregen/gige_sfp_xmdf.tcl deleted file mode 100644 index 5491dccf8..000000000 --- a/fpga/usrp3/top/x300/coregen/gige_sfp_xmdf.tcl +++ /dev/null @@ -1,195 +0,0 @@ -# The package naming convention is _xmdf -package provide gige_sfp_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::gige_sfp_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::gige_sfp_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name gige_sfp -} -# ::gige_sfp_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::gige_sfp_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/doc/gig_eth_pcs_pma_v11_4_vinfo.html -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/doc/pg047-gig-eth-pcs-pma.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_block.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_example_design.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_example_design.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_example_design.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_mod.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_reset_sync.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_sync_block.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/gige_sfp_tx_elastic_buffer.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_gtwizard.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_transceiver.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/gig_eth_pcs_pma_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/implement/example_design_xst.xcf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/demo_tb.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/simulate_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/simulate_ncsim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/simulate_vcs.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/ucli_commands.key -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/vcs_session.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/wave_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/functional/wave_ncsim.sv -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp/simulation/stimulus_tb.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gige_sfp_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module gige_sfp -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.gise b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.gise index c7bad44d8..63c0a4abe 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.gise +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.ngc b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.ngc index 3bbc7f92c..32373a76d 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.ngc +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e -$3dff~753-Xnzd}foo8#5+421).97 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6`728l<7E5;h3b5;n1f1?6=3th:h4?50;694?6|,:l;6d8294?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`=`=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l8o1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:hd0a94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`4d=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l8k1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h<750;694?6|,:l;6d0:94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`=0=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l1?1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h5:50;694?6|,:l;6d9194?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`=4=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l1;1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h5>50;694?6|,:l;6d6d94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`46=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l9l1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h=k50;694?6|,:l;6d1f94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`5e=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l9h1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h=o50;694?6|,:l;6d1094?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`57=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l9:1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:okh50;694?6|,:l;6cgg94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2gcb=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6koi1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h;850;694?6|,:l;6d7794?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`32=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l?91<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h;<50;694?6|,:l;6d7394?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`36=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l5;h3b5;n1f1?6=3th:h:850;694?6|,:l;6d6794?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`22=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l>91<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:h:<50;694?6|,:l;6d6394?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2`26=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6l?l1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:j:=50;194?6|,:l;681<7=50;2x 6`728l>7E5;h3`4?6=3f9n97>5;|`2b27=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>f6294?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:j;h50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2b3b=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>f7a94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i5850;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a=2=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e9194?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i5<50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a2`=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e6g94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i:j50;194?6|,:l;6i1<7=50;2x 6`728l>7E5;h3`4?6=3f9n97>5;|`2a2d=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e6c94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i:750;194?6|,:l;621<7=50;2x 6`728l>7E5;h3`4?6=3f9n97>5;|`2a21=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e6494?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i::50;194?6|,:l;691<7=50;2x 6`728l>7E5;h3`4?6=3f9n97>5;|`2a24=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e6394?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i:>50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a3c=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e7f94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i;m50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a3?=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e7:94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i;950;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a33=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e7694?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i;=50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a37=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e7294?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i8k50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a0e=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e4`94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i8o50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a0>=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e4594?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i8850;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a05=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e4094?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i8?50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a1`=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e5g94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i9j50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a1d=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e5c94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i5750;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a=1=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e9294?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i:;50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a0`=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>e4694?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:i9750;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2a`7=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>ed294?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:iih50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2aab=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>eea94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:iil50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`144>=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=00594?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<<850;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`1445=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=00094?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<7E5;h3`4?6=3f9n97>5;|`145`=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=01g94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<=j50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`145d=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=01c94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<=650;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`1450=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=01794?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<=:50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`1454=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=01394?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<=>50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2bcb=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fga94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jkl50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2bc?=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fg:94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jk950;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2bc3=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fg694?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jk<50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2bc6=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fdd94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jhk50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2b`e=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fd`94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jho50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2b`1=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fd494?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jh;50;194?6|,:l;61<7=50;2x 6`728l>7E5;h3`4?6=3f9n97>5;|`2b`5=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fd094?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jh?50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2ba`=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>feg94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<7E5;h3`4?6=3f9n97>5;|`144?=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=00694?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<=750;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`2bc5=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl>fd:94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th:jij50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14d>=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=0`594?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th97E5;h3`4?6=3f9n97>5;|`14d5=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=0`094?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th97E5;h3`4?6=3f9n97>5;|`14<`=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=08g94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<4j50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=08c94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<4650;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14<0=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=08794?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<4:50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14<4=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=08394?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<4>50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14=b=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=09a94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<5l50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14=?=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=09:94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<5950;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14=3=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=09694?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<5<50;194?6|,:l;67E5;h3`4?6=3f9n97>5;|`14=6=8391<7>t$2d3>4`23A8n8?5G2d1a?l7f<3:17d?l0;29?j5b=3:17pl=06d94?5=83:p(>h?:0d6?M4b<;1C>h=m;h3b0?6=3`;h<7>5;n1f1?6=3th9<:k50;194?6|,:l;6n1<7=50;2x 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6`728l<7E5;h3b5;n1f1?6=3th:::k50;694?6|,:l;666f94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`222d=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6>>k1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:::750;694?6|,:l;666:94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2221=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6>><1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:::;50;694?6|,:l;666694?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`2225=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6>>81<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th::lh50;694?6|,:l;66`g94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`22db=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6>h21<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th::4j50;694?6|,:l;668094?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`22=1=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6>>i1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:::?50;694?6|,:l;666294?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21a1=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=m<1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9i;50;694?6|,:l;65cd94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21gc=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=kn1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9om50;694?6|,:l;65c`94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21gg=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=k31<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9o650;694?6|,:l;65c594?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21g0=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=k?1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9o:50;694?6|,:l;65c194?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21g4=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=k;1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9o>50;694?6|,:l;65`d94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21dc=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=hn1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9lm50;694?6|,:l;65``94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21dg=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=h31<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9l650;694?6|,:l;65`594?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21d0=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=h?1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9l:50;694?6|,:l;65`194?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21d4=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=h;1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:9l>50;694?6|,:l;658d94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`211<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=0n1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:94m50;694?6|,:l;658`94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`211<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=031<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:94650;694?6|,:l;658594?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21<0=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=0?1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:94:50;694?6|,:l;658194?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21<4=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=0;1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:94>50;694?6|,:l;659d94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21=c=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=1n1<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:95m50;694?6|,:l;659`94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21=g=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=131<7:50;2x 6`728l<7E5;h3b5;n1f1?6=3th:95650;694?6|,:l;65dd94?3=83:p(>h?:0da?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3`9n;7>5;n1f1?6=3th:9hk50;794?6|,:l;65;h3b5;h1f3?6=3f9n97>5;|`21`e=83?1<7>t$2d3>4`e3A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17d=j7;29?j5b=3:17pl>5d`94?3=83:p(>h?:0da?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3`9n;7>5;n1f1?6=3th:9ho50;794?6|,:l;65;h3b5;h1f3?6=3f9n97>5;|`21`>=83?1<7>t$2d3>4`e3A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17d=j7;29?j5b=3:17pl>5bg94?2=83:p(>h?:0d4?M4b<;1C>h=m;h3b0?6=3`;j47>5;h3`4?6=3f9n97>5;|`21fb=83>1<7>t$2d3>4`03A8n8?5G2d1a?l7f<3:17d?n8;29?l7d83:17b=j5;29?xd6=ji1<7:50;2x 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.v index e1a3c52c1..5adc5bbd8 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.v +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.v @@ -1,23 +1,23 @@ //////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx -// \ \ \/ Version: P.49d +// \ \ \/ Version: P.20131013 // \ \ Application: netgen // / / Filename: ten_gig_eth_pcs_pma.v -// /___/ /\ Timestamp: Mon Jan 28 16:53:26 2013 +// /___/ /\ Timestamp: Thu Sep 4 14:45:14 2014 // \ \ / \ // \___\/\___\ // -// Command : -w -sim -ofmt verilog /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.ngc /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.v +// Command : -w -sim -ofmt verilog /home/ashish/git/fpgadev/eth_fix/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.ngc /home/ashish/git/fpgadev/eth_fix/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.v // Device : 7k410tffg900-2 -// Input file : /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.ngc -// Output file : /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.v +// Input file : /home/ashish/git/fpgadev/eth_fix/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.ngc +// Output file : /home/ashish/git/fpgadev/eth_fix/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.v // # of Modules : 1 // Design Name : ten_gig_eth_pcs_pma -// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/ // // Purpose: // This verilog netlist is a verification model and uses simulation @@ -88,141 +88,140 @@ loopback_ctrl wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ; wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 ; wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_259 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_260 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_261 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_262 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_263 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_292 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_293 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_294 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_298 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_299 ; wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_265 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_301 ; wire N0; - wire NlwRenamedSig_OI_drp_dwe; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_292 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_293 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_308 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_311 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_314 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_317 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_320 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_811_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_328 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_329 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_385_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_502 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_545 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_546 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_547 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_548 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_555 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_694 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_695 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_696 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_535 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_538 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_539 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_540 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_575 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_576 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_581 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_582 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_583 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_584 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_585 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_586 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_587 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_591 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_730 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_731 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_732 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_699 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_700 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_701 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_702 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_703 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_704 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_705 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_706 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_707 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_708 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_709 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_710 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_711 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_712 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_713 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_714 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_715 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_716 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_717 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_718 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_719 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_720 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_721 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_722 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_723 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_724 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_725 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_726 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_727 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_728 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_729 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_730 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_731 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_732 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_733 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_734 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_735 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_736 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_737 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_738 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_739 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_740 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_741 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_742 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_743 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_744 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_745 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_746 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_747 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_748 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_749 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_750 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_751 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_752 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_753 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_754 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_755 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_756 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_757 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_758 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_759 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_760 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_761 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_762 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_763 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_764 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_735 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_736 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_737 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_738 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_739 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_740 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_741 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_742 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_743 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_744 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_745 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_746 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_747 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_748 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_749 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_750 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_751 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_752 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_753 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_754 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_755 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_756 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_757 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_758 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_759 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_760 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_761 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_762 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_763 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_764 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_765 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_766 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_767 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_768 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_769 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_770 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_771 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_772 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_773 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_774 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_775 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_776 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_777 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_778 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_779 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_780 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_781 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_782 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_783 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_784 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_785 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_786 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_787 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_788 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_789 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_790 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_791 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_792 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_793 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_794 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_795 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_796 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_797 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_798 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_799 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_800 ; wire NlwRenamedSig_OI_pcs_resetout; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_int ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_int ; @@ -244,138 +243,105 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<13> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<14> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1250 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1251 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1280 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1286 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1287 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_766_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_765_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1336 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1337 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1338 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1340 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1342 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1343 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_770_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_769_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1372 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1373 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1374 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1375 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1376 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1378 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1379 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1380 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1398 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_1441 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_1457 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_1473 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1489 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_1477 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_1478 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_1479 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_1480 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_1481 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_1482 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_1483 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_1484 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_1485 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_1486 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_1487 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_1488 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_1489 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_1490 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<0>_1491 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_lut<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_1493 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_1494 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_1495 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_1496 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_1497 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_1498 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_1499 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_1500 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_1501 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_1502 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_1503 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_1504 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_1505 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_1506 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<0>_1507 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_lut<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_1509 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_1510 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_1511 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_1512 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_1513 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_1514 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_1515 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_1516 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_1517 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_1518 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_1519 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_1520 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_1521 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_1522 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<0>_1523 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_lut<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1525 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_0 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1499 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1535 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1502 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1538 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_529_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> ; @@ -392,116 +358,149 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1645 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1646 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_371_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_356_o_1666 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1679 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1680 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1681 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_88_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_377_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1676 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1711 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<9> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<8> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<7> ; @@ -522,15 +521,15 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<2> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1753 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1754 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1789 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1790 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1756 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1757 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_691_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_691_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_691_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_691_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1792 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1793 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_695_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_695_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_695_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_695_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<15> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<14> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<13> ; @@ -663,7 +662,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_519_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we ; @@ -679,8 +678,8 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_we ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1962 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1963 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ; @@ -695,25 +694,25 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_311_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1959 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1988 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1989 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1990 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1991 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1992 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1993 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1995 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1996 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_2034 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<2> ; @@ -729,7 +728,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<6> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<7> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2014 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2050 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<2> ; @@ -763,20 +762,58 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<13> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<14> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1-In ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2-In ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_reg_2107 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_317_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<6> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<7> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<8> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<9> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<10> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<11> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<12> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<13> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<14> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<15> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<16> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<17> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<18> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<19> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<20> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<21> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<22> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<23> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<24> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<25> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<26> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<27> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<28> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<29> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<30> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<31> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<32> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<33> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ; @@ -813,15 +850,15 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2493 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ; @@ -830,7 +867,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<3>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<2>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2577 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<0>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emptyg ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fullg ; @@ -840,7 +877,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3]_wr_addr[2]_XOR_5_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<2> ; @@ -856,7 +893,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In ; @@ -970,11 +1007,11 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<29> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<30> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<31> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_3014 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_3015 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<2> ; @@ -1050,17 +1087,14 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<3>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<2>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_3238 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<0>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emptyg ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fullg ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_510_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_509_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<3> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<1> ; @@ -1089,7 +1123,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<2> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<3> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<1> ; @@ -1202,83 +1236,83 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<29> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<30> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<31> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156_3376 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2_3377 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1_3378 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3379 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3381 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156_3620 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2_3621 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1_3622 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3623 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3624 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3625 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3383 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3385 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3627 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3628 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3629 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3387 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3389 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3631 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3632 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3633 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3399 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3401 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3636 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3637 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3639 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3640 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3641 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3642 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3643 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3644 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3645 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3403 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3405 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3647 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3648 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3649 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3407 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3409 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3651 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3652 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3653 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3419 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3421 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3656 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3657 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3659 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3660 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3661 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3662 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3663 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3664 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3665 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3423 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3425 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3667 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3668 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3669 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3427 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3429 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3671 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3672 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3673 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/out_comb ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3676 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3677 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3679 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3680 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3681 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3682 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11322 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3687 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11121 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111112 ; @@ -1309,20 +1343,20 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3730 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ; @@ -1341,7 +1375,7 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o_mmx_out ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out ; @@ -1381,8 +1415,8 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[6] ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ; @@ -1537,12 +1571,12 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4087 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4331 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<0> ; @@ -1611,90 +1645,89 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<63> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<64> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<65> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4465 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4466 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Madd_sh_cnt[5]_GND_26_o_add_37_OUT_cy<3> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_4395 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_394_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_399_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[2]_GND_26_o_Mux_27_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<0> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<1> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<2> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<3> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<4> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<5> ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0139 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4660 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4661 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_PWR_27_o_Mux_51_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In11 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4666 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT17 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4428 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4669 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4671 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4673 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4675 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4677 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4679 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4681 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4683 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4685 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4687 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4689 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4691 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4693 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4695 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4697 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt4 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4465 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4706 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<0> ; @@ -1713,12 +1746,12 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<13> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<14> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4726 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_27_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_25_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<2> ; @@ -1736,81 +1769,81 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<14> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<15> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<3>11 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4586 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4587 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4588 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4589 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4590 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4591 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4592 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4593 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4594 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4595 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4596 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4597 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4598 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4599 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4600 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4601 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4602 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4603 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4604 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4605 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4827 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4828 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4829 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4830 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4831 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4832 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4833 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4834 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4835 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4836 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4837 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4838 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4839 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4840 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4841 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4842 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4843 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4844 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4845 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4846 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4607 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4848 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4616 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4857 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<20> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4618 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4859 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<19> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4620 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4861 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<18> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4622 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4863 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<17> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4624 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4865 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<16> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4626 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4867 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4628 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4869 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<14> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4630 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4871 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<13> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4632 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4873 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<12> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4634 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4875 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<11> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4636 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4877 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<10> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4638 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4879 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<9> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4640 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4881 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<8> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4642 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4883 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<7> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4644 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4885 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<6> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4646 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4887 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<5> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4648 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4889 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<4> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4650 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4891 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<3> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4652 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4893 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<2> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4654 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4895 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<1> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4656 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4897 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<0> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4665 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4906 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_424_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_434_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4912 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2721 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4915 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ; @@ -1835,21 +1868,21 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o1_4941 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o31 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o2_4950 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o21 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ; @@ -1927,11 +1960,11 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_5044 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ; @@ -2068,71 +2101,71 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<1> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<2> ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_4941 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_4942 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_4943 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_4944 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_4945 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_4946 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_4947 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_4948 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_4949 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_4950 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_4951 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_4952 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_4953 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_4954 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_4955 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_4956 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_4957 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_4958 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_4959 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_4960 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_4961 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_4962 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_4963 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_4964 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_4965 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_4966 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_4967 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_4968 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_4969 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_4970 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_4971 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_4972 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_4973 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_4974 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_4975 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_4976 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_4977 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_4978 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_4979 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_4980 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_4981 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_4982 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_4983 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_4984 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_4985 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_4986 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_4987 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_4988 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_4989 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_4990 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_4991 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_4992 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_4993 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_4994 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_4995 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_4996 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_5182 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_5183 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_5184 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_5185 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_5186 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_5187 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_5188 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_5189 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_5190 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_5191 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_5192 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_5193 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_5194 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_5195 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_5196 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_5197 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_5198 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_5199 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_5200 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_5201 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_5202 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_5203 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_5204 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_5205 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_5206 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_5207 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_5208 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_5209 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_5210 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_5211 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_5212 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_5213 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_5214 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_5215 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_5216 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_5217 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_5218 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_5219 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_5220 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_5221 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_5222 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_5223 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_5224 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_5225 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_5226 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_5227 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_5228 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_5229 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_5230 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_5231 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_5232 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_5233 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_5234 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_5235 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_5236 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_5237 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5070 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5071 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5311 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5312 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<0> ; @@ -2211,15 +2244,15 @@ loopback_ctrl wire N4; wire N6; wire N8; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5153 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5154 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5394 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5395 ; wire N10; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1_5156 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2_5157 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1_5158 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2_5159 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1_5160 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2_5161 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o1_5397 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o2_5398 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o1_5399 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o2_5400 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o1_5401 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o2_5402 ; wire N12; wire N14; wire N16; @@ -2237,188 +2270,187 @@ loopback_ctrl wire N40; wire N42; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15> ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5179 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5420 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT91 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5181 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5182 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5183 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5422 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5423 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5424 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT96 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5185 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5186 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5187 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5426 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5427 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5428 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5430 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5431 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5432 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5433 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5434 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5435 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT57_5436 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5189 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5190 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5191 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5192 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5193 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5194 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37_5195 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38_5196 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5197 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5198 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5199 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5200 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5201 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5202 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5203 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5204 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5438 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5439 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5440 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5441 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5442 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5443 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5445 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5446 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5447 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5448 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5449 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5450 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5451 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5452 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5453 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5454 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5455 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5456 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5457 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5458 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5459 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5460 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5206 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5207 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5208 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5209 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5210 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5211 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5212 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5213 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5462 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5463 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5464 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5465 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5466 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5467 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5468 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5469 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT111 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5215 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5216 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5217 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5218 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5219 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5471 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5472 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5473 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5474 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5475 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT10 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5221 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5222 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5223 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5224 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5477 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5478 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5479 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5480 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT106 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5226 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5227 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5228 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5482 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5483 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5484 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT122 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5230 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5231 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5232 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5233 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5234 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5486 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5487 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5488 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5489 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5490 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21_5492 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5493 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5494 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5495 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5496 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5236 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5237 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5238 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5239 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5240 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5241 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5242 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5243 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5244 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5245 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5246 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5247 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5498 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5499 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5500 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5501 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5502 ; wire N44; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41_5249 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5250 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5251 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5252 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5253 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5254 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5255 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5256 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5257 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5258 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5259 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5260 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5261 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5262 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5264 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5265 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5266 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5267 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5268 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5269 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5505 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5506 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5507 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5508 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5509 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5510 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5511 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5512 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5513 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5514 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5515 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5516 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT157_5517 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT7 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5271 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5272 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5273 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5274 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5275 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5276 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5279 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5280 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5281 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5282 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26_5283 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5519 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5520 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5521 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5522 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5523 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5524 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5285 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5286 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5287 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5288 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5289 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5290 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5291 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5292 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5293 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5526 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5527 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5528 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5529 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5530 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5531 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5532 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5533 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5534 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT8 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5296 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5297 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5298 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5299 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5300 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5301 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5536 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5537 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5538 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5539 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5540 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5541 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT89_5542 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ; wire N46; wire N48; wire N50; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1_5307 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2_5308 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3_5309 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o1_5548 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o2_5549 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o3_5550 ; wire N52; wire N54; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5312 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5313 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5314 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5315 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5316 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5317 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5318 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5319 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5320 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5321 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5553 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5554 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5555 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5556 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5557 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5558 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5559 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5560 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5561 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5562 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT8 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5323 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5324 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5325 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5564 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5565 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5566 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT17 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5568 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT173 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT175 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT14 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5331 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5332 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5333 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5572 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5573 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5574 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1111 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5576 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5577 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114 ; - wire N58; wire N60; wire N62; wire N64; wire N66; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5343 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5344 ; wire N68; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5346 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5347 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5584 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5585 ; wire N70; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5349 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5350 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5587 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5588 ; wire N72; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5352 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5353 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5590 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5591 ; wire N74; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5355 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5356 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5593 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5594 ; wire N76; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5358 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5359 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5596 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5597 ; wire N78; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5599 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5600 ; wire N80; wire N82; wire N84; @@ -2430,26 +2462,26 @@ loopback_ctrl wire N96; wire N98; wire N100; + wire N102; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT48 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5373 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5614 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT53 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5375 ; - wire N102; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5616 ; wire N104; wire N106; wire N108; wire N110; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5381 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5382 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5383 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5384 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5385 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code12 ; wire N112; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code5 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5389 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5622 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5623 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5624 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5625 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5626 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code12 ; wire N114; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code5 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5630 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5631 ; wire N116; wire N118; wire N120; @@ -2462,94 +2494,94 @@ loopback_ctrl wire N134; wire N136; wire N138; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5404 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 ; wire N140; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5409 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5410 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5411 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5412 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5645 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 ; wire N142; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5650 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5651 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5652 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5653 ; wire N144; + wire N146; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code8 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5416 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5657 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5658 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 ; - wire N148; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code4 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5421 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ; wire N150; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code3 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5425 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5426 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code4 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5662 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5663 ; wire N152; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code3 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5666 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5667 ; + wire N154; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code2 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5429 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5430 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5431 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5432 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5433 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5434 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5435 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5436 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5437 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5438 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5439 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5440 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5441 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5442 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5443 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5444 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5445 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5446 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5447 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5448 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5449 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5450 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5451 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5452 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5453 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5454 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5455 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5456 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5457 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5458 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5459 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5460 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5461 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5462 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5463 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5464 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5465 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5466 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5467 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5670 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5671 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5672 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5673 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5674 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5675 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5676 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5677 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5678 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5679 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5680 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5681 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5682 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5683 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5684 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5685 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5686 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5687 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5688 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5689 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5690 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5691 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5692 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5693 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5694 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5695 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5696 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5697 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5698 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5699 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5700 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5701 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5702 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5703 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5704 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5705 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5706 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5707 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5708 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5469 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5710 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5711 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1173 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5473 ; - wire N154; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5714 ; wire N156; wire N158; wire N160; - wire N166; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5479 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5480 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5481 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5482 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5483 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT202 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5485 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5486 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5487 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5488 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5489 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5490 ; + wire N162; wire N168; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5720 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5721 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5722 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5723 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5724 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT202 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5726 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5727 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5728 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5729 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5730 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5731 ; wire N170; wire N172; wire N174; @@ -2564,15 +2596,16 @@ loopback_ctrl wire N192; wire N194; wire N196; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5507 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5508 ; wire N198; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5748 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5749 ; wire N200; wire N202; wire N204; wire N206; - wire N214; + wire N208; + wire N216; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT9 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT8 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT7 ; @@ -2586,8 +2619,8 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT45 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT4 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT34 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5528 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5529 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5769 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5770 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT30 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT29 ; @@ -2597,8 +2630,8 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT25 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT24 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT23 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5539 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5540 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5780 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5781 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT20 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT19 ; @@ -2608,74 +2641,68 @@ loopback_ctrl wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT15 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT14 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT13 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5550 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5551 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5791 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5792 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT10 ; - wire N216; wire N218; wire N220; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5557 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3_5558 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4_5559 ; - wire N222; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1_5561 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2_5562 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5797 ; wire N224; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5799 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5800 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5801 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5802 ; wire N226; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5565 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5566 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5567 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5568 ; - wire N228; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5570 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5804 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5572 ; - wire N230; - wire N234; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5575 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5806 ; + wire N228; + wire N232; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5809 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT41 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT40 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT39 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT38 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT35 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT36 ; + wire N236; wire N238; - wire N240; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5584 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5585 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5818 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5819 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT27 ; - wire N246; + wire N244; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT32 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5589 ; - wire N248; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5823 ; + wire N246; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT8 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT16 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT15 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT14 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT13 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT11 ; + wire N248; wire N250; wire N252; wire N254; wire N256; - wire N258; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT51 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT50 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT49 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT48 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT47 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT43 ; + wire N260; wire N262; - wire N264; - wire N268; - wire N272; + wire N266; + wire N270; + wire N274; wire N276; wire N278; wire N280; wire N282; wire N284; - wire N286; + wire N288; wire N290; wire N292; wire N294; @@ -2685,197 +2712,198 @@ loopback_ctrl wire N302; wire N304; wire N306; - wire N308; + wire N310; wire N312; - wire N314; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT611 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5631 ; - wire N320; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5865 ; + wire N318; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT621 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5634 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5868 ; + wire N322; wire N324; wire N326; wire N328; wire N330; - wire N332; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT4 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5641 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5875 ; + wire N332; wire N334; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5878 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o1_5879 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o2_5880 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o3_5881 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o4_5882 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o5_5883 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o6_5884 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o7_5885 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o8_5886 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o9_5887 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o10_5888 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o11_5889 ; wire N336; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1_5645 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2_5646 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3_5647 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4_5648 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6_5650 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7_5651 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8_5652 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9_5653 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ; wire N338; - wire N340; + wire N342; wire N344; - wire N346; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT9 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT44 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT18 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT17 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o2_5898 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o3_5899 ; + wire N360; wire N362; - wire N364; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5668 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5669 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5902 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5903 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT163 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5672 ; - wire N366; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5674 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5675 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5676 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5677 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5678 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5679 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5680 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5681 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5682 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5683 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5684 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5685 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5686 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5687 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5688 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5689 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5690 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5691 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5692 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5693 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt_5757 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt_5758 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt_5759 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5760 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5761 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5762 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5763 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5764 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5765 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_5766 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_5767 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_5768 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_5769 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_5770 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_5771 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_5772 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_5773 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_5774 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_5775 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_5776 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_5777 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_5778 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_5779 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_5780 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_5781 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_5782 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_5783 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_5784 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_5785 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_5786 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_5787 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_5788 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_5789 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_5790 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_5791 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_5792 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_5793 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_5794 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_5795 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_5796 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_5797 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_5798 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_5799 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_5800 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5906 ; + wire N364; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5908 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5909 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5910 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5911 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5912 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5913 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5914 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5915 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5916 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5917 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5918 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5919 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5920 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5921 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5922 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5923 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5924 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5925 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5926 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5927 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_rt_5928 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_rt_5929 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_rt_5930 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_rt_5931 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_rt_5932 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_rt_5933 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_rt_5934 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_rt_5935 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_rt_5936 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_rt_5937 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_rt_5938 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_rt_5939 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_rt_5940 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_rt_5941 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_rt_5942 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_rt_5943 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_rt_5944 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_rt_5945 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_rt_5946 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_rt_5947 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_rt_5948 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_rt_5949 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_rt_5950 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_rt_5951 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_rt_5952 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_rt_5953 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_rt_5954 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_rt_5955 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_rt_5956 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_rt_5957 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_rt_5958 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_rt_5959 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_rt_5960 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_rt_5961 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_rt_5962 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_rt_5963 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_rt_5964 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_rt_5965 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_rt_5966 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_rt_5967 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_rt_5968 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_rt_5969 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5970 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5971 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5972 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5973 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5974 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5975 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5976 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5977 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5978 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5979 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5980 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5981 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5982 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5983 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5984 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5985 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5986 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5987 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5988 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5989 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5990 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<15>_rt_5991 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<15>_rt_5992 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<15>_rt_5993 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5994 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5995 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5996 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5997 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5998 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5999 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_6000 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_6001 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3_rstpot_6002 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_6003 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_6004 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_6005 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_6006 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_6007 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_6008 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_6009 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_6010 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_6011 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_6012 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_6013 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_6014 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_6015 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_6016 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_6017 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_6018 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_6019 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_6020 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_6021 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_6022 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_6023 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_6024 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_6025 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_6026 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_6027 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_6028 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_6029 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_6030 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_6031 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_6032 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_6033 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_6034 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_6035 ; + wire N368; wire N370; wire N372; wire N374; - wire N376; - wire N381; + wire N379; + wire N380; wire N382; - wire N384; + wire N386; wire N388; wire N390; wire N392; - wire N394; + wire N398; wire N400; wire N402; wire N404; wire N406; wire N408; - wire N410; + wire N412; wire N414; wire N416; wire N418; @@ -2917,25 +2945,25 @@ loopback_ctrl wire N490; wire N492; wire N494; - wire N496; - wire N500; + wire N498; + wire N499; wire N501; - wire N503; + wire N502; wire N504; - wire N506; - wire N507; - wire N513; + wire N505; + wire N511; + wire N512; wire N514; wire N516; wire N518; wire N520; - wire N522; + wire N521; wire N523; wire N525; wire N527; - wire N529; + wire N528; wire N530; - wire N532; + wire N531; wire N533; wire N535; wire N537; @@ -2943,11 +2971,11 @@ loopback_ctrl wire N541; wire N543; wire N545; - wire N547; + wire N546; wire N548; - wire N550; + wire N549; wire N551; - wire N553; + wire N552; wire N554; wire N556; wire N558; @@ -2962,17 +2990,16 @@ loopback_ctrl wire N576; wire N578; wire N580; - wire N582; + wire N584; wire N586; + wire N587; wire N588; - wire N589; wire N590; wire N592; - wire N594; + wire N596; wire N598; wire N600; wire N602; - wire N604; wire N606; wire N612; wire N614; @@ -3005,9 +3032,7 @@ loopback_ctrl wire N668; wire N670; wire N672; - wire N673; wire N674; - wire N675; wire N676; wire N677; wire N678; @@ -3020,14 +3045,20 @@ loopback_ctrl wire N685; wire N686; wire N687; + wire N688; + wire N689; + wire N690; + wire N691; + wire N692; + wire N693; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ; wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_5968 ; - wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_5969 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_6207 ; + wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_6208 ; wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i_SPO_UNCONNECTED ; wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i_SPO_UNCONNECTED ; wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i_SPO_UNCONNECTED ; @@ -3170,6 +3201,7 @@ loopback_ctrl wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_Q15_UNCONNECTED ; wire [31 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd ; wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc ; + wire [0 : 0] NlwRenamedSig_OI_loopback_ctrl; wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data ; wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type ; wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out ; @@ -3225,13 +3257,14 @@ loopback_ctrl wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q ; wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q ; wire [5 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q ; - wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q ; + wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk ; + wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q ; wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk ; wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 ; - wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 ; - wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 ; - wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 ; - wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 ; + wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 ; + wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 ; + wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 ; + wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 ; wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 ; wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 ; wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 ; @@ -3261,7 +3294,7 @@ loopback_ctrl wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk ; wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 ; wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg ; - wire [3 : 2] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status ; + wire [3 : 3] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status ; wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr ; wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr ; wire [71 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data ; @@ -3286,7 +3319,6 @@ loopback_ctrl wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result ; wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo ; wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo ; - wire [2 : 1] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync ; wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp ; wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp ; wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray ; @@ -3360,8 +3392,8 @@ loopback_ctrl wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg ; wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg ; wire [65 : 2] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc ; - wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt ; - wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt ; + wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt ; + wire [5 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt ; wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt ; wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt ; wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us ; @@ -3374,13 +3406,13 @@ loopback_ctrl wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state ; assign \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d = signal_detect, - core_status[7] = NlwRenamedSig_OI_drp_dwe, - core_status[6] = NlwRenamedSig_OI_drp_dwe, - core_status[5] = NlwRenamedSig_OI_drp_dwe, - core_status[4] = NlwRenamedSig_OI_drp_dwe, - core_status[3] = NlwRenamedSig_OI_drp_dwe, - core_status[2] = NlwRenamedSig_OI_drp_dwe, - core_status[1] = NlwRenamedSig_OI_drp_dwe, + core_status[7] = NlwRenamedSig_OI_loopback_ctrl[0], + core_status[6] = NlwRenamedSig_OI_loopback_ctrl[0], + core_status[5] = NlwRenamedSig_OI_loopback_ctrl[0], + core_status[4] = NlwRenamedSig_OI_loopback_ctrl[0], + core_status[3] = NlwRenamedSig_OI_loopback_ctrl[0], + core_status[2] = NlwRenamedSig_OI_loopback_ctrl[0], + core_status[1] = NlwRenamedSig_OI_loopback_ctrl[0], core_status[0] = \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q , gt_txd[31] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [31], @@ -3423,252 +3455,218 @@ loopback_ctrl gt_txc[2] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [2], gt_txc[1] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [1], gt_txc[0] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [0], - drp_daddr[15] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[14] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[13] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[12] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[11] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[10] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[9] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[8] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[7] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[6] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[5] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[4] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[3] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[2] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[1] = NlwRenamedSig_OI_drp_dwe, - drp_daddr[0] = NlwRenamedSig_OI_drp_dwe, - drp_di[15] = NlwRenamedSig_OI_drp_dwe, - drp_di[14] = NlwRenamedSig_OI_drp_dwe, - drp_di[13] = NlwRenamedSig_OI_drp_dwe, - drp_di[12] = NlwRenamedSig_OI_drp_dwe, - drp_di[11] = NlwRenamedSig_OI_drp_dwe, - drp_di[10] = NlwRenamedSig_OI_drp_dwe, - drp_di[9] = NlwRenamedSig_OI_drp_dwe, - drp_di[8] = NlwRenamedSig_OI_drp_dwe, - drp_di[7] = NlwRenamedSig_OI_drp_dwe, - drp_di[6] = NlwRenamedSig_OI_drp_dwe, - drp_di[5] = NlwRenamedSig_OI_drp_dwe, - drp_di[4] = NlwRenamedSig_OI_drp_dwe, - drp_di[3] = NlwRenamedSig_OI_drp_dwe, - drp_di[2] = NlwRenamedSig_OI_drp_dwe, - drp_di[1] = NlwRenamedSig_OI_drp_dwe, - drp_di[0] = NlwRenamedSig_OI_drp_dwe, - loopback_ctrl[2] = NlwRenamedSig_OI_drp_dwe, + loopback_ctrl[2] = NlwRenamedSig_OI_loopback_ctrl[0], loopback_ctrl[1] = \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 , - loopback_ctrl[0] = NlwRenamedSig_OI_drp_dwe, + loopback_ctrl[0] = NlwRenamedSig_OI_loopback_ctrl[0], pma_resetout = \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 , pcs_resetout = NlwRenamedSig_OI_pcs_resetout, - mdio_out = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_259 , - mdio_tri = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_260 , - gt_slip = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_261 , - drp_den = NlwRenamedSig_OI_drp_dwe, - drp_dwe = NlwRenamedSig_OI_drp_dwe, - tx_disable = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_262 , - tx_prbs31_en = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_263 , + mdio_out = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_292 , + mdio_tri = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_293 , + gt_slip = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_294 , + tx_disable = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_298 , + tx_prbs31_en = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_299 , rx_prbs31_en = \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q , - clear_rx_prbs_err_count = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_265 ; + clear_rx_prbs_err_count = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_301 ; VCC XST_VCC ( .P(N0) ); GND XST_GND ( - .G(NlwRenamedSig_OI_drp_dwe) + .G(NlwRenamedSig_OI_loopback_ctrl[0]) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_575 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_807_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_811_o ), .Q(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_308 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_311 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_314 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_317 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_576 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_320 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1 ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_263 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_299 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1 ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ), .Q(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_548 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_584 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_810_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_811_o ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_811_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_585 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_292 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_328 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_292 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_328 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_586 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_293 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_329 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2 ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_293 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_262 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_329 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_298 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local ( .C(clk156), .D(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_7 ( .C(txusrclk2), @@ -3713,626 +3711,626 @@ loopback_ctrl FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_31 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [33]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [31]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_30 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [32]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [30]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_29 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [31]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [29]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_28 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [30]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [28]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_27 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [29]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [27]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_26 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [28]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [26]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_25 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [27]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [25]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_24 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [26]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [24]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_23 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [25]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [23]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_22 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [24]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [22]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_21 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [23]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [21]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_20 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [22]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [20]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_19 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [21]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [19]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_18 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [20]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [18]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_17 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [19]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [17]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_16 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [18]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [16]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_15 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [17]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [15]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_14 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [16]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [14]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_13 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [15]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [13]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_12 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [14]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [12]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_11 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [13]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [11]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_10 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [12]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [10]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_9 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [11]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [9]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_8 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [10]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [8]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_7 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [9]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [7]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_6 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [8]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [6]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_5 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [7]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [5]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_4 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [6]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [4]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_3 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [5]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [3]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_2 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [4]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [2]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_1 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [3]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [1]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_0 ( .C(txusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [2]), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [0]) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_core_reg ( .C(clk156), .D(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_reg ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_int ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_502 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_535 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_538 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_555 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_591 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_535 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_65 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_764 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_800 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_64 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_763 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_799 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_63 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_762 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_798 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [63]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_62 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_761 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_797 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_61 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_760 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_796 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [61]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_60 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_759 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_795 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [60]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_59 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_758 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_794 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [59]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_58 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_757 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_793 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_57 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_756 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_792 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_56 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_755 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_791 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [56]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_55 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_754 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_790 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_54 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_753 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_789 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [54]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_53 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_752 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_788 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_52 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_751 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_787 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [52]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_51 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_750 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_786 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_50 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_749 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_785 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_49 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_748 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_784 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [49]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_48 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_747 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_783 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_47 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_746 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_782 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_46 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_745 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_781 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [46]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_45 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_744 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_780 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [45]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_44 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_743 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_779 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [44]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_43 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_742 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_778 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_42 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_741 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_777 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [42]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_41 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_740 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_776 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [41]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_40 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_739 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_775 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_39 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_738 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_774 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_38 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_737 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_773 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_37 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_736 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_772 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_36 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_735 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_771 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_35 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_734 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_770 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_34 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_733 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_769 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_33 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_732 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_768 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [33]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_32 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_731 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_767 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [32]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_31 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_730 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_766 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [31]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_30 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_729 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_765 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_29 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_728 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_764 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_28 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_727 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_763 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [28]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_27 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_726 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_762 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [27]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_26 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_725 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_761 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_25 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_724 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_760 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_24 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_723 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_759 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [24]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_23 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_722 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_758 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_22 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_721 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_757 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_21 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_720 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_756 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_20 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_719 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_755 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_19 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_718 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_754 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_18 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_717 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_753 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_17 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_716 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_752 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_16 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_715 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_751 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_15 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_714 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_750 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_14 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_713 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_749 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_13 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_712 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_748 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_12 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_711 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_747 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_11 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_710 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_746 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_10 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_709 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_745 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [10]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_9 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_708 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_744 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_8 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_707 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_743 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_706 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_742 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_705 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_741 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_704 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_740 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_703 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_739 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_702 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_738 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_2 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_701 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_737 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_700 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_736 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_699 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_735 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_265 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_385_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_301 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid ( .C(rxusrclk2), .D(gt_rxc[2]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_540 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_33 ( .C(rxusrclk2), @@ -4507,22 +4505,22 @@ loopback_ctrl FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid ( .C(rxusrclk2), .D(gt_rxc[3]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_539 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_int ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_546 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_582 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_545 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_581 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr ( .C(clk156), .D(resetdone), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_547 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_583 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_7 ( .C(clk156), @@ -5374,1221 +5372,1221 @@ loopback_ctrl ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1398 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1340 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1376 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1380 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1342 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1378 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_766_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_770_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1380 ) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1337 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1373 ), .S(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1336 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1372 ) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1338 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1374 ), .S(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1337 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1373 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_765_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1343 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_769_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1379 ) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1 ( .C(clk156), .D(mdio_in), .S(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1338 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1374 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<15> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_1441 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_1477 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt_5757 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<15>_rt_5991 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<15> ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<14> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_1478 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_rt_5928 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<14> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_1478 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_rt_5928 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_1441 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_1477 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<13> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_1479 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_rt_5929 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<13> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_1479 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_rt_5929 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_1478 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<12> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_1480 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_rt_5930 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<12> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_1480 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_rt_5930 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_1479 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<11> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_1481 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_rt_5931 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<11> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_1481 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_rt_5931 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_1480 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<10> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_1482 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_rt_5932 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<10> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_1482 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_rt_5932 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_1481 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<9> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_1483 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_rt_5933 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<9> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_1483 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_rt_5933 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_1482 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<8> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_1484 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_rt_5934 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<8> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_1484 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_rt_5934 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_1483 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<7> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_1485 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_rt_5935 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<7> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_1485 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_rt_5935 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_1484 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<6> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_1486 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_rt_5936 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<6> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_1486 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_rt_5936 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_1485 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<5> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_1487 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_rt_5937 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<5> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_1487 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_rt_5937 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_1486 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<4> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_1488 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_rt_5938 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<4> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_1488 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_rt_5938 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_1487 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<3> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_1489 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_rt_5939 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<3> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_1489 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_rt_5939 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_1488 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<2> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_1490 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_rt_5940 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<2> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_1490 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_rt_5940 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_1489 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<1> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<0>_1491 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_rt_5941 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<1> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<0>_1491 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_rt_5941 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_1490 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<0> ( + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<0> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<0> ( + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<0>_1491 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<15> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_1457 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_1493 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt_5758 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<15>_rt_5992 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<15> ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<14> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_1494 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_rt_5942 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<14> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_1494 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_rt_5942 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_1457 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_1493 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<13> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_1495 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_rt_5943 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<13> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_1495 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_rt_5943 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_1494 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<12> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_1496 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_rt_5944 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<12> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_1496 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_rt_5944 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_1495 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<11> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_1497 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_rt_5945 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<11> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_1497 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_rt_5945 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_1496 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<10> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_1498 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_rt_5946 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<10> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_1498 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_rt_5946 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_1497 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<9> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_1499 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_rt_5947 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<9> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_1499 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_rt_5947 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_1498 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<8> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_1500 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_rt_5948 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<8> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_1500 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_rt_5948 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_1499 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<7> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_1501 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_rt_5949 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<7> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_1501 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_rt_5949 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_1500 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<6> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_1502 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_rt_5950 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<6> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_1502 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_rt_5950 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_1501 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<5> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_1503 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_rt_5951 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<5> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_1503 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_rt_5951 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_1502 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<4> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_1504 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_rt_5952 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<4> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_1504 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_rt_5952 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_1503 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<3> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_1505 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_rt_5953 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<3> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_1505 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_rt_5953 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_1504 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<2> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_1506 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_rt_5954 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<2> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_1506 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_rt_5954 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_1505 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<1> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<0>_1507 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_rt_5955 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<1> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<0>_1507 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_rt_5955 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_1506 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<0> ( + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<0> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<0> ( + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<0>_1507 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<15> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_1473 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_1509 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt_5759 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<15>_rt_5993 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<15> ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<14> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_1510 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_rt_5956 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<14> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_1510 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_rt_5956 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_1473 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_1509 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<13> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_1511 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_rt_5957 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<13> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_1511 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_rt_5957 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_1510 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<12> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_1512 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_rt_5958 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<12> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_1512 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_rt_5958 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_1511 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<11> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_1513 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_rt_5959 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<11> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_1513 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_rt_5959 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_1512 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<10> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_1514 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_rt_5960 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<10> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_1514 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_rt_5960 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_1513 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<9> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_1515 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_rt_5961 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<9> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_1515 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_rt_5961 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_1514 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<8> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_1516 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_rt_5962 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<8> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_1516 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_rt_5962 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_1515 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<7> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_1517 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_rt_5963 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<7> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_1517 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_rt_5963 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_1516 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<6> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_1518 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_rt_5964 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<6> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_1518 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_rt_5964 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_1517 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<5> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_1519 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_rt_5965 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<5> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_1519 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_rt_5965 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_1518 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<4> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_1520 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_rt_5966 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<4> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_1520 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_rt_5966 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_1519 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<3> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_1521 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_rt_5967 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<3> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_1521 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_rt_5967 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_1520 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<2> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_1522 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_rt_5968 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<2> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_1522 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_rt_5968 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_1521 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<1> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<0>_1523 ) , .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_rt_5969 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<1> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1> ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<0>_1523 ) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_rt_5969 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_1522 ) ); XORCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<0> ( + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<0> ) ); MUXCY - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<0> ( + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<0>_1523 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_4 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1489 ) + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1525 ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_3 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_3 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_2 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_2 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_1 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_1 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_0 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_0 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]) ); @@ -6596,30 +6594,30 @@ loopback_ctrl .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1499 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1535 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1502 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1538 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .R(reset), @@ -6628,7 +6626,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .R(reset), @@ -6637,7 +6635,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .R(reset), @@ -6646,7 +6644,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .R(reset), @@ -6655,16 +6653,16 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ) , - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [0]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_356_o_1666 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .R(reset), @@ -6673,7 +6671,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_356_o_1666 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .R(reset), @@ -6681,152 +6679,152 @@ loopback_ctrl ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_15 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<15> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_14 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<14> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_13 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<13> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_12 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<12> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_11 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<11> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_10 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<10> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_9 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<9> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_8 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<8> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_7 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<7> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_6 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<6> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_5 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<5> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_4 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<4> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_3 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<3> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_2 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<2> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_1 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<1> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_0 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<0> ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1646 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1681 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1645 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1680 ) ); FDSE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ), .S(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_260 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_293 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_15 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]) @@ -6834,10 +6832,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_14 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]) @@ -6845,10 +6843,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_13 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]) @@ -6856,10 +6854,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_12 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]) @@ -6867,10 +6865,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_11 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]) @@ -6878,10 +6876,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_10 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]) @@ -6889,10 +6887,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_9 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]) @@ -6900,10 +6898,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_8 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]) @@ -6911,10 +6909,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_7 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]) @@ -6922,10 +6920,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_6 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]) @@ -6933,10 +6931,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]) @@ -6944,10 +6942,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]) @@ -6955,10 +6953,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]) @@ -6966,10 +6964,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]) @@ -6977,10 +6975,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]) @@ -6988,10 +6986,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]) @@ -6999,10 +6997,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_15 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<15> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]) @@ -7010,10 +7008,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_14 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<14> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]) @@ -7021,10 +7019,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_13 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<13> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]) @@ -7032,10 +7030,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_12 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<12> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]) @@ -7043,10 +7041,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_11 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<11> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]) @@ -7054,10 +7052,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_10 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<10> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]) @@ -7065,10 +7063,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_9 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<9> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]) @@ -7076,10 +7074,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_8 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<8> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]) @@ -7087,10 +7085,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_7 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<7> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]) @@ -7098,10 +7096,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_6 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<6> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]) @@ -7109,10 +7107,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<5> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]) @@ -7120,10 +7118,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<4> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]) @@ -7131,10 +7129,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<3> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]) @@ -7142,10 +7140,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<2> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]) @@ -7153,10 +7151,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<1> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]) @@ -7164,10 +7162,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]) @@ -7175,10 +7173,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_15 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]) @@ -7186,10 +7184,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_14 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]) @@ -7197,10 +7195,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_13 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]) @@ -7208,10 +7206,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_12 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]) @@ -7219,10 +7217,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_11 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]) @@ -7230,10 +7228,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_10 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]) @@ -7241,10 +7239,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_9 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]) @@ -7252,10 +7250,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_8 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]) @@ -7263,10 +7261,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_7 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]) @@ -7274,10 +7272,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_6 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]) @@ -7285,10 +7283,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]) @@ -7296,10 +7294,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]) @@ -7307,10 +7305,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]) @@ -7318,10 +7316,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]) @@ -7329,10 +7327,10 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]) @@ -7340,213 +7338,213 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) , .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ) , .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_259 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_292 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1336 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1372 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_529_o ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1679 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd ( .C(clk156), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_371_o ) , .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1646 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1681 ) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_15 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [15]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [15]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_14 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [14]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [14]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_13 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [13]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [13]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_12 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [12]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [12]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_11 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [11]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [11]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_10 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [10]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [10]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_9 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [9]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [9]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_8 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [8]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [8]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_7 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [7]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [7]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_6 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [6]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [6]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_5 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [5]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [5]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_4 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [4]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [4]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_3 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [3]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [3]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_2 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [2]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [2]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_1 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [1]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [1]) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_0 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [0]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [0]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In1 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In1 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_15 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [15]), .R(reset), @@ -7555,7 +7553,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_14 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [14]), .R(reset), @@ -7564,7 +7562,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_13 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [13]), .R(reset), @@ -7573,7 +7571,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_12 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [12]), .R(reset), @@ -7582,7 +7580,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_11 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [11]), .R(reset), @@ -7591,7 +7589,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_10 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [10]), .R(reset), @@ -7600,7 +7598,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_9 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [9]), .R(reset), @@ -7609,7 +7607,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_8 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [8]), .R(reset), @@ -7618,7 +7616,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_7 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [7]), .R(reset), @@ -7627,7 +7625,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_6 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [6]), .R(reset), @@ -7636,7 +7634,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [5]), .R(reset), @@ -7645,7 +7643,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [4]), .R(reset), @@ -7654,7 +7652,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [3]), .R(reset), @@ -7663,7 +7661,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [2]), .R(reset), @@ -7672,7 +7670,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [1]), .R(reset), @@ -7681,7 +7679,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [0]), .R(reset), @@ -8128,18 +8126,18 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0 ( .C(clk156), .CE(N0), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_585 ), .R(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1992 ) ); FDRE #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0 ( .C(clk156), .CE(N0), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_548 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_584 ), .R(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1991 ) ); FDRE #( .INIT ( 1'b0 )) @@ -8148,32 +8146,32 @@ loopback_ctrl .CE(N0), .D(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ), .R(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1990 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1753 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1789 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1754 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1790 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1756 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1792 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1757 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1793 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_2034 ) ); FDRE #( .INIT ( 1'b0 )) @@ -8181,7 +8179,7 @@ loopback_ctrl .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_691_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_695_o ), .R (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .Q @@ -8193,10 +8191,10 @@ loopback_ctrl .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_691_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_695_o ), .R (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1251 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1287 ) ); FDRE #( .INIT ( 1'b0 )) @@ -8204,9 +8202,9 @@ loopback_ctrl .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_691_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_695_o ), .R(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1250 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1286 ) ); FDRE #( .INIT ( 1'b0 )) @@ -8214,9 +8212,9 @@ loopback_ctrl .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_691_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_695_o ), .R(NlwRenamedSig_OI_pcs_resetout), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ) ); FDRE #( .INIT ( 1'b0 )) @@ -9742,15 +9740,15 @@ loopback_ctrl .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_311_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1280 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_519_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ) ); FDR #( .INIT ( 1'b0 )) @@ -10055,7 +10053,7 @@ loopback_ctrl FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2014 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2050 ) ); FDE #( .INIT ( 1'b0 )) @@ -10217,19 +10215,132 @@ loopback_ctrl , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [0]) ); + FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1-In ), + .R(reset), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ) + ); + FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2-In ), + .R(reset), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_15 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [31]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [15]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_14 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [30]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [14]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_13 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [29]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [13]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_12 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [28]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [12]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_11 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [27]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [11]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_10 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [26]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [10]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_9 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [25]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [9]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_8 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [24]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [8]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_7 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [23]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [7]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_6 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [22]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [6]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_5 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [21]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [5]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_4 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [20]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [4]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_3 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [19]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [3]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_2 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [18]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [2]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_1 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [17]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [1]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk_0 ( + .C(dclk), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [16]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [0]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_reg ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_reg_2107 ) + ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_33 ( .C(dclk), @@ -10241,12 +10352,172 @@ loopback_ctrl .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<32> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]) ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_31 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<31> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [31]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_30 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<30> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [30]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_29 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<29> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [29]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_28 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<28> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [28]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_27 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<27> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [27]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_26 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<26> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [26]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_25 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<25> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [25]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_24 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<24> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [24]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_23 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<23> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [23]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_22 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<22> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [22]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_21 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<21> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [21]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_20 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<20> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [20]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_19 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<19> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [19]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_18 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<18> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [18]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_17 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<17> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [17]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_16 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<16> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [16]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_15 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<15> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [15]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_14 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<14> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [14]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_13 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<13> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [13]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_12 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<12> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [12]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_11 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<11> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [11]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_10 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<10> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [10]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_9 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<9> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [9]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_8 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<8> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [8]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_7 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<7> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [7]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_6 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<6> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [6]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_5 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<5> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [5]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_4 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<4> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [4]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_3 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<3> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [3]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_2 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<2> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [2]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_1 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<1> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [1]) + ); + FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_0 ( + .C(dclk), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<0> ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [0]) + ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_317_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_33 ( .C(clk156), @@ -10260,6 +10531,198 @@ loopback_ctrl .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [32]) ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_31 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [31]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_30 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [30]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_29 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [29]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_28 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [28]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_27 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [27]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_26 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [26]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_25 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [25]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_24 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [24]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_23 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [23]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_22 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [22]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_21 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [21]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_20 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [20]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_19 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [19]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_18 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [18]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_17 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [17]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_16 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [16]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_15 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [15]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_14 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [14]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_13 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [13]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_12 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [12]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_11 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [11]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_10 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [10]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_9 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [9]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_8 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [8]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_7 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [7]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_6 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [6]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_5 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [5]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_4 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [4]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_3 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [3]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_2 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [2]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_1 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [1]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_0 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [0]) + ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_33 ( .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), @@ -10272,6 +10735,198 @@ loopback_ctrl .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [32]) ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_31 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [31]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_30 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [30]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_29 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [29]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_28 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [28]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_27 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [27]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_26 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [26]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_25 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [25]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_24 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [24]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_23 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [23]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_22 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [22]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_21 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [21]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_20 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [20]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_19 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [19]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_18 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [18]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_17 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [17]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_16 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [16]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_15 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [15]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_14 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [14]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_13 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [13]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_12 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [12]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_11 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [11]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_10 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [10]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_9 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [9]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_8 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [8]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_7 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [7]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_6 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [6]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_5 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [5]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_4 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [4]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_3 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [3]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_2 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [2]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_1 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [1]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_0 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [0]) + ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_33 ( .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), @@ -10284,6 +10939,198 @@ loopback_ctrl .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [32]) ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_31 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [31]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_30 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [30]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_29 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [29]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_28 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [28]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_27 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [27]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_26 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [26]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_25 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [25]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_24 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [24]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_23 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [23]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_22 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [22]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_21 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [21]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_20 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [20]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_19 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [19]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_18 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [18]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_17 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [17]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_16 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [16]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_15 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [15]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_14 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [14]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_13 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [13]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_12 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [12]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_11 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [11]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_10 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [10]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_9 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [9]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_8 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [8]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_7 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [7]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_6 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [6]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_5 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [5]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_4 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [4]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_3 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [3]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_2 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [2]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_1 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [1]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_0 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [0]) + ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_33 ( .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), @@ -10296,111 +11143,303 @@ loopback_ctrl .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [32]) ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_31 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [31]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_30 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [30]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_29 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [29]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_28 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [28]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_27 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [27]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_26 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [26]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_25 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [25]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_24 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [24]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_23 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [23]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_22 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [22]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_21 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [21]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_20 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [20]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_19 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [19]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_18 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [18]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_17 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [17]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_16 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [16]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_15 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [15]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_14 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [14]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_13 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [13]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_12 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [12]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_11 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [11]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_10 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [10]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_9 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [9]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_8 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [8]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_7 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [7]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_6 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [6]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_5 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [5]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_4 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [4]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_3 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [3]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_2 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [2]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_1 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [1]) + ); + FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_0 ( + .C(clk156), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [0]) + ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_17 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<17> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [17]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_16 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<16> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_15 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<15> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [15]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_14 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<14> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [14]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_13 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<13> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [13]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_12 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<12> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [12]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_11 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<11> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [11]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_10 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<10> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [10]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_9 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<9> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [9]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_8 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<8> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [8]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_7 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<7> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [7]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_6 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<6> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [6]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_5 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<5> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [5]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_4 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<4> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [4]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_3 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<3> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [3]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_2 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<2> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [2]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_1 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<1> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [1]) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_0 ( .C(clk156), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<0> ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [0]) ); @@ -10840,285 +11879,285 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [14]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5760 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5994 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [15]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<14> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [13]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5970 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [14]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [13]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5970 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [14]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<13> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [12]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5971 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [13]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [12]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5971 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [13]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<12> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [11]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5972 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [12]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [11]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5972 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [12]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<11> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [10]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5973 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [11]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [10]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5973 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [11]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<10> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [9]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5974 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [10]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [9]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5974 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [10]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<9> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [8]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5975 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [9]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [8]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5975 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [9]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<8> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [7]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5976 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [8]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [7]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5976 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [8]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<7> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [6]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5977 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [7]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [6]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5977 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [7]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<6> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [5]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5978 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [6]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [5]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5978 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [6]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<5> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [4]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5979 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [4]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5979 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [5]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<4> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [3]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5980 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [3]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5980 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [4]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<3> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [2]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5981 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5981 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [3]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<2> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [1]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5982 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5982 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [2]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<1> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [0]), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5983 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5983 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [1]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [0]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [6]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5761 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5995 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<7>1 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<6> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [5]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5984 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<6>1 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [5]), - .DI(NlwRenamedSig_OI_drp_dwe), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5984 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [6]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<5> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [4]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5985 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>2 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [4]), - .DI(NlwRenamedSig_OI_drp_dwe), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5985 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [5]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<4> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [3]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5986 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>2 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [3]), - .DI(NlwRenamedSig_OI_drp_dwe), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5986 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [4]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<3> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [2]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5987 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>2 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [2]), - .DI(NlwRenamedSig_OI_drp_dwe), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5987 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [3]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<2> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [1]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5988 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>2 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [1]), - .DI(NlwRenamedSig_OI_drp_dwe), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5988 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [2]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<1> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [0]), - .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ), + .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5989 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>2 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1> ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [0]), - .DI(NlwRenamedSig_OI_drp_dwe), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5989 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [1]) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>2 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [0]) @@ -11126,316 +12165,316 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_15 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [15]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [15]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_14 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [14]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_13 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [13]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_12 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [12]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_11 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [11]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_10 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [10]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_9 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [9]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_8 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [8]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_7 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [7]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_6 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [6]), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [6]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>1 ), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>1 ), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>1 ), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>1 ), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>1 ), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>1 ), .R -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [0]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_7 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<7>1 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_6 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<6>1 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_5 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [5]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_4 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [4]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_3 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [3]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_2 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [2]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_1 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [1]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_0 ( .C(clk156), .CE -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) , .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [0]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) , .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]) ); @@ -11471,49 +12510,49 @@ loopback_ctrl ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy3 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [3]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emptyg ) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy2 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [2]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [2]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy1 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [1]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [1]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [0]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [0]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy3 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [3]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fullg ) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy2 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [2]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [2]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy1 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [1]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [1]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [0]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [0]) ); @@ -11693,7 +12732,7 @@ loopback_ctrl .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fullg ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0_3 ( .C(clk156), @@ -11795,7 +12834,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray_0 ( .C(txusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2577 ), .R(txreset322), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]) ); @@ -11819,7 +12858,7 @@ loopback_ctrl ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray_0 ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2577 ), .R(txreset322), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [0]) ); @@ -13536,7 +14575,7 @@ loopback_ctrl MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcy_i0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [0]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [0]) ); @@ -13544,7 +14583,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcy_i1 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [0]) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [1]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [1]) ); @@ -13552,14 +14591,14 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcy_i2 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [1]) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [2]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb [0]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcy_i0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [0]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [0]) ); @@ -13567,7 +14606,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcy_i1 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [0]) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [1]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [1]) ); @@ -13575,7 +14614,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcy_i2 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [1]) , - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [2]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb [1]) ); @@ -13583,19 +14622,19 @@ loopback_ctrl .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_7 ( .C(rxusrclk2), @@ -14466,14 +15505,14 @@ loopback_ctrl .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_3015 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [1]), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_3014 ) ); FDSE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_1 ( .C(rxusrclk2), @@ -15083,7 +16122,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i7 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [6]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [7]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [7]) @@ -15092,7 +16131,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i5 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [4]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [5]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [5]) @@ -15101,7 +16140,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i3 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [3]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [3]) @@ -15110,7 +16149,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i1 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [1]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [1]) @@ -15119,7 +16158,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i8 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [7]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [8]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb [1]) ); @@ -15127,7 +16166,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i6 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [5]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [6]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [6]) @@ -15136,7 +16175,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i4 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [3]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [4]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [4]) @@ -15145,7 +16184,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i2 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [2]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [2]) @@ -15153,7 +16192,7 @@ loopback_ctrl MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [0]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [0]) @@ -15162,7 +16201,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i7 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [6]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [7]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [7]) @@ -15171,7 +16210,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i5 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [4]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [5]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [5]) @@ -15180,7 +16219,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i3 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [3]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [3]) @@ -15189,7 +16228,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i1 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [1]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [1]) @@ -15198,7 +16237,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i8 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [7]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [8]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb [0]) ); @@ -15206,7 +16245,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i6 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [5]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [6]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [6]) @@ -15215,7 +16254,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i4 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [3]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [4]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [4]) @@ -15224,7 +16263,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i2 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [2]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [2]) @@ -15232,56 +16271,56 @@ loopback_ctrl MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [0]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [0]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy3 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [3]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emptyg ) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy2 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [2]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [2]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy1 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [1]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [1]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [0]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [0]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy3 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [3]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fullg ) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy2 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [2]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [2]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy1 ( .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [1]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [1]) ); MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [0]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [0]) ); @@ -15302,7 +16341,7 @@ loopback_ctrl FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr_1 ( .C(clk156), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_3238 ), .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]) ); @@ -15341,24 +16380,6 @@ loopback_ctrl .R(rxreset322), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]) ); - FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<3> ) -, - .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]) - ); - FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_2 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<2> ) -, - .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [2]) - ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk_3 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [3]), @@ -15687,7 +16708,7 @@ loopback_ctrl ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_3238 ), .R(reset), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [0]) ); @@ -17830,7 +18851,7 @@ loopback_ctrl MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [0]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [0]) @@ -17839,7 +18860,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i2 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [2]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [2]) @@ -17848,7 +18869,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i4 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [3]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [4]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [4]) @@ -17857,7 +18878,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i6 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [5]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [6]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [6]) @@ -17866,7 +18887,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i8 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [7]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [8]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [1]) ); @@ -17874,7 +18895,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i1 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [1]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [1]) @@ -17883,7 +18904,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i3 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [3]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [3]) @@ -17892,7 +18913,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i5 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [4]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [5]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [5]) @@ -17901,7 +18922,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i7 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [6]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [7]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [7]) @@ -17909,7 +18930,7 @@ loopback_ctrl MUXCY_L \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i0 ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [0]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [0]) @@ -17918,7 +18939,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i2 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [1]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [2]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [2]) @@ -17927,7 +18948,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i4 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [3]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [4]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [4]) @@ -17936,7 +18957,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i6 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [5]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [6]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [6]) @@ -17945,7 +18966,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i8 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [7]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [8]), .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [0]) ); @@ -17953,7 +18974,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i1 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [0]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [1]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [1]) @@ -17962,7 +18983,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i3 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [2]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [3]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [3]) @@ -17971,7 +18992,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i5 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [4]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [5]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [5]) @@ -17980,7 +19001,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i7 ( .CI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [6]), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [7]), .LO (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [7]) @@ -17989,7 +19010,7 @@ loopback_ctrl .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_7 ( .C(clk156), @@ -18751,13 +19772,13 @@ loopback_ctrl .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156_3376 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156_3620 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2_3377 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2_3621 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156 ( .C(rxusrclk2), @@ -18769,607 +19790,607 @@ loopback_ctrl .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1_3378 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1_3622 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [33]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_732 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_768 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [2]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_733 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_769 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [3]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_734 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_770 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [4]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_735 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_771 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [5]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_736 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_772 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [6]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_737 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_773 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [7]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_738 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_774 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [8]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_739 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_775 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [9]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_740 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_776 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [10]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_741 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_777 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [12]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_743 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_779 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [13]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_744 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_780 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [11]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_742 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_778 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [14]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_745 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_781 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [15]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_746 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_782 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [16]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_747 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_783 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [17]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_748 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_784 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [18]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_749 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_785 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [19]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_750 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_786 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [21]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_752 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_788 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [22]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_753 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_789 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [20]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_751 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_787 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [23]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_754 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_790 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [24]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_755 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_791 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [25]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_756 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_792 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [26]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_757 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_793 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [27]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_758 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_794 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [28]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_759 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_795 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [30]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_761 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_797 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [31]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_762 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_798 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [29]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_760 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_796 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [32]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_763 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_799 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [33]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_764 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_800 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [0]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_699 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_735 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [1]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_700 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_736 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [2]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_701 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_737 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [3]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_702 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_738 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [4]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_703 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_739 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [5]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_704 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_740 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [6]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_705 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_741 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [7]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_706 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_742 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [8]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_707 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_743 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [9]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_708 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_744 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [10]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_709 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_745 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [11]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_710 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_746 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [13]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_712 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_748 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [14]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_713 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_749 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [12]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_711 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_747 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [15]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_714 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_750 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [16]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_715 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_751 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [17]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_716 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_752 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [18]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_717 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_753 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [19]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_718 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_754 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [20]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_719 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_755 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [22]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_721 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_757 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [23]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_722 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_758 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [21]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_720 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_756 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [24]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_723 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_759 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [25]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_724 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_760 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [26]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_725 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_761 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [27]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_726 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_762 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [28]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_727 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_763 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [29]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_728 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_764 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [31]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_730 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_766 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [32]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_731 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_767 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [30]), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_729 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_765 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3379 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3636 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3623 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3381 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3624 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3625 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3642 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3383 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3627 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3385 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3628 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3629 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3641 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3387 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3637 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3631 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3389 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3632 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3633 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3640 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_694 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_730 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3399 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3656 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3643 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3401 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3644 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3645 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3662 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3403 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3647 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3405 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3648 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3649 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3661 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3407 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3657 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3651 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3409 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3652 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3653 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3660 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_695 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_731 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3419 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3676 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3663 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3421 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3664 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3665 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3682 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3423 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3667 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3425 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3668 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3669 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3681 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3427 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3677 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3671 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3429 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3672 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3673 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/out_comb ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3680 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_696 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_732 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_2 ( .C(clk156), @@ -21348,7 +22369,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<57> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [57]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_56 ( @@ -21356,7 +22377,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<56> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [56]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_55 ( @@ -21364,7 +22385,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<55> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [55]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_54 ( @@ -21372,7 +22393,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<54> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [54]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_53 ( @@ -21380,7 +22401,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<53> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [53]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_52 ( @@ -21388,7 +22409,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<52> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [52]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_51 ( @@ -21396,7 +22417,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<51> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [51]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_50 ( @@ -21404,7 +22425,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<50> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [50]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_49 ( @@ -21412,7 +22433,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<49> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [49]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_48 ( @@ -21420,7 +22441,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<48> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [48]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_47 ( @@ -21428,7 +22449,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<47> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [47]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_46 ( @@ -21436,7 +22457,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<46> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [46]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_45 ( @@ -21444,7 +22465,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<45> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [45]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_44 ( @@ -21452,7 +22473,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<44> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [44]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_43 ( @@ -21460,7 +22481,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<43> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [43]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_42 ( @@ -21468,7 +22489,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<42> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [42]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_41 ( @@ -21476,7 +22497,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<41> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [41]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_40 ( @@ -21484,7 +22505,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<40> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [40]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_39 ( @@ -21492,7 +22513,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<39> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [39]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_38 ( @@ -21500,7 +22521,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<38> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_37 ( @@ -21508,7 +22529,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<37> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_36 ( @@ -21516,7 +22537,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<36> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_35 ( @@ -21524,7 +22545,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<35> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_34 ( @@ -21532,7 +22553,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<34> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_33 ( @@ -21540,7 +22561,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<33> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_32 ( @@ -21548,7 +22569,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<32> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [32]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_31 ( @@ -21556,7 +22577,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<31> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_30 ( @@ -21564,7 +22585,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<30> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_29 ( @@ -21572,7 +22593,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<29> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_28 ( @@ -21580,7 +22601,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<28> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_27 ( @@ -21588,7 +22609,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<27> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_26 ( @@ -21596,7 +22617,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<26> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_25 ( @@ -21604,7 +22625,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<25> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_24 ( @@ -21612,7 +22633,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<24> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_23 ( @@ -21620,7 +22641,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<23> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_22 ( @@ -21628,7 +22649,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<22> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_21 ( @@ -21636,7 +22657,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<21> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [21]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_20 ( @@ -21644,7 +22665,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<20> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_19 ( @@ -21652,7 +22673,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<19> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_18 ( @@ -21660,7 +22681,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<18> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_17 ( @@ -21668,7 +22689,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<17> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_16 ( @@ -21676,7 +22697,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<16> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [16]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_15 ( @@ -21684,7 +22705,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<15> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_14 ( @@ -21692,7 +22713,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<14> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [14]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_13 ( @@ -21700,7 +22721,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<13> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [13]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_12 ( @@ -21708,7 +22729,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<12> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [12]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_11 ( @@ -21716,7 +22737,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<11> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [11]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_10 ( @@ -21724,7 +22745,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<10> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [10]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_9 ( @@ -21732,7 +22753,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<9> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [9]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_8 ( @@ -21740,7 +22761,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<8> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [8]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_7 ( @@ -21748,7 +22769,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<7> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [7]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_6 ( @@ -21756,7 +22777,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<6> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [6]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_5 ( @@ -21764,7 +22785,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<5> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [5]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_4 ( @@ -21772,7 +22793,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<4> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [4]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_3 ( @@ -21780,7 +22801,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<3> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [3]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_2 ( @@ -21788,7 +22809,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<2> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [2]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_1 ( @@ -21796,7 +22817,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<1> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [1]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_0 ( @@ -21804,7 +22825,7 @@ loopback_ctrl .D (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<0> ) , - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [0]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed ( @@ -21812,25 +22833,25 @@ loopback_ctrl .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4087 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4331 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/_n0043 [58]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1 ( .C(clk156), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_65 ( .C(clk156), @@ -22167,193 +23188,188 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4466 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4465 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_466 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt3 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_2 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt2 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_4395 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ) ); - FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_3 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ) + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv ), + .D +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<3> ) +, + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]) + ); + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_2 ( + .C(rxusrclk2), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv ), + .D +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<2> ) +, + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_6 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_1 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]) + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv ), + .D +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<1> ) +, + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_5 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_0 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<5> ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv ), + .D +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<0> ) +, + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]) + ); + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_5 ( + .C(rxusrclk2), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<5> ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_4 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_4 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<4> ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<4> ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_3 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_3 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<3> ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<3> ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_2 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_2 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<2> ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<2> ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_1 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_1 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<1> ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<1> ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_0 ( + FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_0 ( .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<0> ), + .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<0> ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]) ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_4 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]) - ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_3 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]) - ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_2 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<2> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]) - ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_1 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]) - ); - FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_0 ( - .C(rxusrclk2), - .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ), - .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]) - ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_394_o ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_399_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4660 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_555 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_591 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[2]_GND_26_o_Mux_27_o ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_PWR_27_o_Mux_51_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4661 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<15> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4428 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4669 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<15> ) @@ -22363,7 +23379,7 @@ loopback_ctrl XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4671 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> ) @@ -22373,20 +23389,20 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4671 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4428 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4669 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4673 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> ) @@ -22396,20 +23412,20 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4673 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4671 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4675 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> ) @@ -22419,20 +23435,20 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4675 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4673 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4677 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> ) @@ -22442,20 +23458,20 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4677 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4675 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4679 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> ) @@ -22465,20 +23481,20 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4679 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4677 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4681 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> ), @@ -22487,19 +23503,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4681 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4679 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4683 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> ), @@ -22508,19 +23524,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4683 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4681 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4685 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> ), @@ -22529,19 +23545,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4685 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4683 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4687 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> ), @@ -22550,19 +23566,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4687 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4685 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4689 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> ), @@ -22571,19 +23587,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4689 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4687 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4691 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> ), @@ -22592,19 +23608,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4691 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4689 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4693 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> ), @@ -22613,19 +23629,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4693 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4691 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4695 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> ), @@ -22634,19 +23650,19 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4695 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4693 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4697 ) , .LI (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ), @@ -22655,32 +23671,32 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4697 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4695 ) ); XORCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<0> ( .CI(N0), .LI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5990 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<0> ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0> ( .CI(N0), - .DI(NlwRenamedSig_OI_drp_dwe), + .DI(NlwRenamedSig_OI_loopback_ctrl[0]), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5990 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4697 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt_4 ( @@ -22716,34 +23732,34 @@ loopback_ctrl FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4465 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4706 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_27_o ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_587 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_25_o ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4726 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_15 ( .C(rxusrclk2), @@ -22877,430 +23893,430 @@ loopback_ctrl .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_56 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_55 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [10]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [55]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_54 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_53 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_52 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_51 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_50 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_49 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [49]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_48 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [48]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_47 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [47]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_46 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_45 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [45]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_44 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [44]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_43 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_42 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [42]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_41 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [24]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [41]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_40 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [40]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_39 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [39]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_38 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [27]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_37 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [28]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_36 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_35 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_34 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [31]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_33 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [32]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_32 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [33]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_31 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_30 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_29 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_28 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [28]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_27 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_26 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [26]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_25 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_24 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [41]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_23 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [42]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_22 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_21 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [44]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_20 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [45]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_19 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [46]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_18 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_17 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_16 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [49]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [16]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_15 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_14 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [14]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_13 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [52]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [13]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_12 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_11 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [54]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_10 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_9 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [56]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_8 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [7]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [59]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [60]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [61]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_2 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [63]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4469 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4587 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4828 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4586 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4827 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4830 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4829 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4587 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4828 ) ); LUT6 #( @@ -23313,20 +24329,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4829 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4591 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4832 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4590 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4831 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4830 ) ); LUT6 #( @@ -23339,20 +24355,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4590 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4831 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4593 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4834 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4592 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4833 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4591 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4832 ) ); LUT6 #( @@ -23365,20 +24381,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4592 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4833 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4595 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4836 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4594 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4835 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4593 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4834 ) ); LUT6 #( @@ -23391,20 +24407,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4594 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4835 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4597 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4838 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4596 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4837 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4595 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4836 ) ); LUT6 #( @@ -23417,20 +24433,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4596 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4837 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4599 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4840 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4598 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4839 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4597 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4838 ) ); LUT6 #( @@ -23443,20 +24459,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4598 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4839 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4601 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4842 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4600 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4841 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4599 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4840 ) ); LUT6 #( @@ -23469,20 +24485,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4600 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4841 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4603 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4844 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4602 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4843 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4601 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4842 ) ); LUT6 #( @@ -23495,20 +24511,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4602 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4843 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4605 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4846 ) , .DI(N0), .S -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4604 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4845 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4603 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4844 ) ); LUT6 #( @@ -23521,37 +24537,37 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4604 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4845 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4607 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4848 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4605 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4846 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4607 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4848 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<21> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4616 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4857 ) , .DI(N0), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]), @@ -23560,329 +24576,329 @@ loopback_ctrl MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4618 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4859 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<20> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4616 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4857 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4620 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4861 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<19> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4618 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4859 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4622 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4863 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<18> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4620 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4861 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4624 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4865 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<17> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4622 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4863 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4626 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4867 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<16> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4624 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4865 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4628 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4869 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<15> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4626 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4867 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4630 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4871 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<14> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4628 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4869 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4632 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4873 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<13> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4630 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4871 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4634 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4875 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<12> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4632 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4873 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4636 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4877 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<11> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4634 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4875 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4638 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4879 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<10> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4636 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4877 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4640 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4881 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<9> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4638 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4879 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4642 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4883 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<8> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4640 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4881 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4644 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4885 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<7> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4642 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4883 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4646 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4887 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<6> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4644 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4885 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4648 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4889 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<5> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4646 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4887 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4650 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4891 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<4> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4648 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4889 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4652 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4893 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<3> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4650 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4891 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4654 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4895 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<2> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4652 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4893 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1> ( .CI -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4656 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4897 ) , .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<1> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4654 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4895 ) ); MUXCY \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0> ( - .CI(NlwRenamedSig_OI_drp_dwe), + .CI(NlwRenamedSig_OI_loopback_ctrl[0]), .DI(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4656 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4897 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [6]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [6]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [5]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [5]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [4]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [3]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_2 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [2]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [1]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [0]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_424_o ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_434_o ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_63 ( .C(rxusrclk2), @@ -24290,337 +25306,337 @@ loopback_ctrl .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_4996 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_5237 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_4995 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_5236 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_4994 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_5235 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_4993 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_5234 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_4992 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_5233 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_4991 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_5232 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_4990 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_5231 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_4989 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_5230 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_4988 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_5229 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_4987 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_5228 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_4986 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_5227 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_4985 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_5226 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_4984 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_5225 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_4983 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_5224 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_4982 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_5223 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_4981 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_5222 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_4980 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_5221 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_4979 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_5220 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_4978 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_5219 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_4977 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_5218 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_4976 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_5217 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_4975 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_5216 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_4974 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_5215 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_4973 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_5214 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_4972 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_5213 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_4971 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_5212 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_4970 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_5211 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_4969 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_5210 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_4968 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_5209 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_4967 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_5208 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_4966 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_5207 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_4965 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_5206 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_4964 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_5205 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_4963 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_5204 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_4962 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_5203 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_4961 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_5202 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_4960 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_5201 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_4959 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_5200 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_4958 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_5199 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_4957 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_5198 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_4956 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_5197 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_4955 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_5196 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_4954 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_5195 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_4953 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_5194 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_4952 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_5193 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_4951 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_5192 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_4950 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_5191 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_4949 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_5190 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_4948 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_5189 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<7> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_4947 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_5188 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<6> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_4946 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_5187 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<5> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_4945 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_5186 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<4> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_4944 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_5185 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<3> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_4943 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_5184 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<1> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_4942 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_5183 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<0> ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_4941 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_5182 ) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_7 ( .C(rxusrclk2), @@ -24700,481 +25716,481 @@ loopback_ctrl .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [65]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_64 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [64]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_63 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [63]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_62 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [62]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_61 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [61]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_60 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [60]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_59 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [59]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_58 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [58]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_57 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [57]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_56 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [56]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_55 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [55]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_54 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [54]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_53 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [53]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_52 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [52]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_51 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [51]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_50 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [50]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_49 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [49]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_48 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [48]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_47 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [47]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_46 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [46]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_45 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [45]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_44 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [44]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_43 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [43]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_42 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [42]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_41 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_40 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [40]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_39 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_38 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_37 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_36 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_35 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_34 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_33 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_32 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_31 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_30 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_29 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_28 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [28]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_27 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [27]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_26 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [26]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_25 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [25]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_24 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [24]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_23 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [23]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_22 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [22]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_21 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [21]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_20 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [20]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_19 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [19]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_18 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [18]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_17 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_16 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_15 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_14 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_13 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_12 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [12]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_11 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_10 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_9 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_8 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_7 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_6 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_5 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_4 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_3 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_2 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_1 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]) ); FDRE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_0 ( .C(rxusrclk2), .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5070 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5311 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5071 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5312 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3 ( .C(rxusrclk2), .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ) + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_7 ( .C(rxusrclk2), @@ -25610,42 +26626,42 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h00000008 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_385_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_576 ), .I1(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_575 ), .I4(rxreset322), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_385_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/Mmux_d1_d_MUX_806_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/Mmux_d1_d_MUX_810_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_311 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_806_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_810_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/Mmux_d1_d_MUX_806_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/Mmux_d1_d_MUX_810_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_314 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_810_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/Mmux_d1_d_MUX_806_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/Mmux_d1_d_MUX_810_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_317 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [0]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ) ); LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd110 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [0]), .O(xgmii_rxd[0]) @@ -25653,7 +26669,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd210 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [10]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [10]), .O(xgmii_rxd[10]) @@ -25661,7 +26677,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd310 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [11]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [11]), .O(xgmii_rxd[11]) @@ -25669,7 +26685,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd410 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [12]), .O(xgmii_rxd[12]) @@ -25677,7 +26693,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd510 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [13]), .O(xgmii_rxd[13]) @@ -25685,7 +26701,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd65 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [14]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [14]), .O(xgmii_rxd[14]) @@ -25693,7 +26709,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [15]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [15]), .O(xgmii_rxd[15]) @@ -25701,7 +26717,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [16]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [16]), .O(xgmii_rxd[16]) @@ -25709,7 +26725,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [17]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [17]), .O(xgmii_rxd[17]) @@ -25717,7 +26733,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [18]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [18]), .O(xgmii_rxd[18]) @@ -25725,7 +26741,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [19]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [19]), .O(xgmii_rxd[19]) @@ -25733,7 +26749,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [1]), .O(xgmii_rxd[1]) @@ -25741,7 +26757,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [20]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [20]), .O(xgmii_rxd[20]) @@ -25749,7 +26765,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [21]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [21]), .O(xgmii_rxd[21]) @@ -25757,7 +26773,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [22]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [22]), .O(xgmii_rxd[22]) @@ -25765,7 +26781,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [23]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [23]), .O(xgmii_rxd[23]) @@ -25773,7 +26789,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd171 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [24]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [24]), .O(xgmii_rxd[24]) @@ -25781,7 +26797,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd181 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [25]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [25]), .O(xgmii_rxd[25]) @@ -25789,7 +26805,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd191 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [26]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [26]), .O(xgmii_rxd[26]) @@ -25797,7 +26813,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd201 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [27]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [27]), .O(xgmii_rxd[27]) @@ -25805,7 +26821,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd211 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [28]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [28]), .O(xgmii_rxd[28]) @@ -25813,7 +26829,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd221 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [29]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [29]), .O(xgmii_rxd[29]) @@ -25821,7 +26837,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd231 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [2]), .O(xgmii_rxd[2]) @@ -25829,7 +26845,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd241 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [30]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [30]), .O(xgmii_rxd[30]) @@ -25837,7 +26853,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd251 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [31]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [31]), .O(xgmii_rxd[31]) @@ -25845,7 +26861,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd261 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [32]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [32]), .O(xgmii_rxd[32]) @@ -25853,7 +26869,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd271 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [33]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [33]), .O(xgmii_rxd[33]) @@ -25861,7 +26877,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd281 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [34]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [34]), .O(xgmii_rxd[34]) @@ -25869,7 +26885,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd291 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [35]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [35]), .O(xgmii_rxd[35]) @@ -25877,7 +26893,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd301 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [36]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [36]), .O(xgmii_rxd[36]) @@ -25885,7 +26901,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd311 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [37]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [37]), .O(xgmii_rxd[37]) @@ -25893,7 +26909,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd321 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [38]), .O(xgmii_rxd[38]) @@ -25901,7 +26917,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd331 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [39]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [39]), .O(xgmii_rxd[39]) @@ -25909,7 +26925,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd341 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [3]), .O(xgmii_rxd[3]) @@ -25917,7 +26933,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd351 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [40]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [40]), .O(xgmii_rxd[40]) @@ -25925,7 +26941,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd361 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [41]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [41]), .O(xgmii_rxd[41]) @@ -25933,7 +26949,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd371 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [42]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [42]), .O(xgmii_rxd[42]) @@ -25941,7 +26957,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd381 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [43]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [43]), .O(xgmii_rxd[43]) @@ -25949,7 +26965,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd391 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [44]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [44]), .O(xgmii_rxd[44]) @@ -25957,7 +26973,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd401 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [45]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [45]), .O(xgmii_rxd[45]) @@ -25965,7 +26981,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd411 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [46]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [46]), .O(xgmii_rxd[46]) @@ -25973,7 +26989,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd421 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [47]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [47]), .O(xgmii_rxd[47]) @@ -25981,7 +26997,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd431 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [48]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [48]), .O(xgmii_rxd[48]) @@ -25989,7 +27005,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd441 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [49]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [49]), .O(xgmii_rxd[49]) @@ -25997,7 +27013,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd451 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [4]), .O(xgmii_rxd[4]) @@ -26005,7 +27021,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd461 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [50]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [50]), .O(xgmii_rxd[50]) @@ -26013,7 +27029,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd471 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [51]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [51]), .O(xgmii_rxd[51]) @@ -26021,7 +27037,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd481 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [52]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [52]), .O(xgmii_rxd[52]) @@ -26029,7 +27045,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd491 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [53]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [53]), .O(xgmii_rxd[53]) @@ -26037,7 +27053,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd501 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [54]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [54]), .O(xgmii_rxd[54]) @@ -26045,7 +27061,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd511 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [55]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [55]), .O(xgmii_rxd[55]) @@ -26053,7 +27069,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd521 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [56]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [56]), .O(xgmii_rxd[56]) @@ -26061,7 +27077,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd531 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [57]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [57]), .O(xgmii_rxd[57]) @@ -26069,7 +27085,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd541 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [58]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [58]), .O(xgmii_rxd[58]) @@ -26077,7 +27093,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd551 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [59]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [59]), .O(xgmii_rxd[59]) @@ -26085,7 +27101,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd561 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [5]), .O(xgmii_rxd[5]) @@ -26093,7 +27109,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd571 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [60]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [60]), .O(xgmii_rxd[60]) @@ -26101,7 +27117,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd581 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [61]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [61]), .O(xgmii_rxd[61]) @@ -26109,7 +27125,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd591 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [62]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [62]), .O(xgmii_rxd[62]) @@ -26117,7 +27133,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd601 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [63]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [63]), .O(xgmii_rxd[63]) @@ -26125,7 +27141,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd611 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [6]), .O(xgmii_rxd[6]) @@ -26133,7 +27149,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd621 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [7]), .O(xgmii_rxd[7]) @@ -26141,7 +27157,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd631 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [8]), .O(xgmii_rxd[8]) @@ -26149,7 +27165,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd641 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [9]), .O(xgmii_rxd[9]) @@ -26157,7 +27173,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [0]), .O(xgmii_rxc[0]) @@ -26165,7 +27181,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [1]), .O(xgmii_rxc[1]) @@ -26173,7 +27189,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [2]), .O(xgmii_rxc[2]) @@ -26181,7 +27197,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [3]), .O(xgmii_rxc[3]) @@ -26189,7 +27205,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [4]), .O(xgmii_rxc[4]) @@ -26197,7 +27213,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [5]), .O(xgmii_rxc[5]) @@ -26205,7 +27221,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [6]), .O(xgmii_rxc[6]) @@ -26213,7 +27229,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [7]), .O(xgmii_rxc[7]) @@ -26221,100 +27237,100 @@ loopback_ctrl LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_gt_txc_mux<0>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux [0]) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_gt_txc_mux<1>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_580 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux [1]) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/Mmux_q_d1_MUX_807_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/Mmux_q_d1_MUX_811_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .I1(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_807_o ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_308 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_811_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/Mmux_d1_d_MUX_806_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/Mmux_d1_d_MUX_810_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_546 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_806_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_308 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_582 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_810_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/Mmux_q_d1_MUX_807_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/Mmux_q_d1_MUX_811_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_807_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_311 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_811_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/Mmux_q_d1_MUX_807_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/Mmux_q_d1_MUX_811_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_317 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_811_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/Mmux_q_d1_MUX_807_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/Mmux_q_d1_MUX_811_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_314 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_811_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/Mmux_q_d1_MUX_807_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/Mmux_q_d1_MUX_811_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_576 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_320 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_811_o ) ); LUT3 #( .INIT ( 8'hE4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/Mmux_d1_d_MUX_806_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/Mmux_d1_d_MUX_810_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_545 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_320 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_581 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_547 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_583 ), .I1(resetdone), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_575 ), .I1(rxreset322), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset ) ); LUT2 #( .INIT ( 4'h4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/Mmux_mdc_reg1_GND_62_o_MUX_766_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/Mmux_mdc_reg1_GND_62_o_MUX_770_o11 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1343 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_766_o ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1379 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_770_o ) ); LUT2 #( .INIT ( 4'h4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/Mmux_mdc_in_GND_62_o_MUX_765_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/Mmux_mdc_in_GND_62_o_MUX_769_o11 ( .I0(reset), .I1(mdc), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_765_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_769_o ) ); LUT6 #( .INIT ( 64'hEEEEEEEB44444441 )) @@ -26330,47 +27346,47 @@ loopback_ctrl LUT5 #( .INIT ( 32'hABAB2101 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]) ); LUT6 #( .INIT ( 64'h0000000000800000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1645 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_371_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1680 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_371_o ) ); LUT5 #( .INIT ( 32'h00000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ) ); LUT6 #( .INIT ( 64'h0000000000800000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_359_o ) ); LUT4 #( .INIT ( 16'hFFA9 )) @@ -26383,155 +27399,155 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h00000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>31 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>31 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) ); LUT6 #( .INIT ( 64'h2000000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>21 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF7FFF7F7F )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) ); LUT5 #( .INIT ( 32'h00000008 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>31 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>31 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) ); LUT6 #( .INIT ( 64'h0000000000800000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>21 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFDFDFFFDF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) ); LUT5 #( .INIT ( 32'h00010000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>31 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>31 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) ); LUT6 #( .INIT ( 64'h0000002000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>21 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFEFEFFFEF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) ); LUT6 #( .INIT ( 64'hB9BBBBBBFFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ) @@ -26557,1050 +27573,1050 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h02020002 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_529_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_529_o ) ); LUT6 #( .INIT ( 64'h2AAA2A2A2AAAEAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In ) ); LUT3 #( .INIT ( 8'h10 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_122_o<4>1 ) ); LUT4 #( .INIT ( 16'hFF08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<1> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<1> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<9>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<9> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<9> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<2> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<2> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<3> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<3> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<4>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<4> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<4> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<5>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<5> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<5> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<6>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<6> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<6> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<7>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<7> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<7> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<8>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<8> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<8> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<10>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<10> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<10> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<11>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<11> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<11> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<13>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<13> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<13> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<14>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<14> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<14> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<15> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<15> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<12>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>1_1475 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_129_OUT<12> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_147_OUT<12> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<0> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<1> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<2> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<3> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<4> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<5> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<6> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<7> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<8> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<9> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<10> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<11> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<12> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<15> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<13> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1474 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_135_OUT<14> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<1> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<0> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<2> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<3> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<4> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<5> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<6> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<7> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<8> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<10> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<11> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<13> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<12> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<14> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<9> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1473 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_132_OUT<15> ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ) ); LUT4 #( @@ -27608,35 +28624,35 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1679 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_88_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ) ); LUT4 #( .INIT ( 16'h0800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_366_o ) ); LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad11 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]) ); LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad21 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]) @@ -27645,7 +28661,7 @@ loopback_ctrl .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad31 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]) @@ -27654,7 +28670,7 @@ loopback_ctrl .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad41 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]) @@ -27663,7 +28679,7 @@ loopback_ctrl .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad51 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4]) @@ -27671,49 +28687,49 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0110 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_drp_cs11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ) ); LUT4 #( .INIT ( 16'hA3A2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1375 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In1 ) ); LUT4 #( .INIT ( 16'h5548 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_cs11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_01 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I1(reset), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ) ); LUT2 #( .INIT ( 4'hD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_ipif_rnw1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ) ); LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), @@ -27723,7 +28739,7 @@ loopback_ctrl .INIT ( 32'h00800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), @@ -27735,7 +28751,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ) ); @@ -27747,7 +28763,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 ) @@ -27756,7 +28772,7 @@ loopback_ctrl .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -27771,7 +28787,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ) ); LUT6 #( @@ -27781,7 +28797,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -27815,7 +28831,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ) ); @@ -27826,9 +28842,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I3(NlwRenamedSig_OI_pcs_resetout), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ) ); LUT6 #( .INIT ( 64'h8000000000000000 )) @@ -27837,7 +28853,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ) ); @@ -27848,14 +28864,14 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ) ); LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), @@ -27884,7 +28900,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ) ); @@ -27903,7 +28919,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ) ); LUT3 #( @@ -27911,7 +28927,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ) ); LUT3 #( @@ -27919,7 +28935,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ) ); LUT3 #( @@ -27927,7 +28943,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 ) @@ -27937,9 +28953,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) ); LUT3 #( @@ -27979,20 +28995,20 @@ loopback_ctrl ); LUT3 #( .INIT ( 8'h10 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n0397171 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n0399171 ( .I0 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ) ); LUT3 #( .INIT ( 8'h20 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n0397711 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n0399711 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ) ); LUT2 #( .INIT ( 4'h4 )) @@ -28018,26 +29034,284 @@ loopback_ctrl ); LUT3 #( .INIT ( 8'hFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398<20>1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400<20>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/pcs_reset_core1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .O(NlwRenamedSig_OI_pcs_resetout) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_2034 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ) ); + LUT6 #( + .INIT ( 64'h45446766CDCCEFEE )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2-In1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_reg_2107 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]), + .I4(drp_gnt), + .I5(drp_drdy), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2-In ) + ); + LUT4 #( + .INIT ( 16'h7A2A )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1-In1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(drp_drdy), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ), + .I3(drp_gnt), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1-In ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di17 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [0]), + .O(drp_di[0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di21 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [10]), + .O(drp_di[10]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di31 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [11]), + .O(drp_di[11]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di41 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [12]), + .O(drp_di[12]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di51 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [13]), + .O(drp_di[13]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di61 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [14]), + .O(drp_di[14]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di71 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [15]), + .O(drp_di[15]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di81 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [1]), + .O(drp_di[1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di91 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [2]), + .O(drp_di[2]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di101 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [3]), + .O(drp_di[3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di111 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [4]), + .O(drp_di[4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di121 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [5]), + .O(drp_di[5]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di131 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [6]), + .O(drp_di[6]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di141 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [7]), + .O(drp_di[7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di151 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [8]), + .O(drp_di[8]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_di161 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [9]), + .O(drp_di[9]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr17 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [0]), + .O(drp_daddr[0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr21 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [10]), + .O(drp_daddr[10]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr31 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [11]), + .O(drp_daddr[11]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr41 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [12]), + .O(drp_daddr[12]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr51 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [13]), + .O(drp_daddr[13]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr61 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [14]), + .O(drp_daddr[14]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr71 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [15]), + .O(drp_daddr[15]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr81 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [1]), + .O(drp_daddr[1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr91 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [2]), + .O(drp_daddr[2]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr101 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [3]), + .O(drp_daddr[3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr111 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [4]), + .O(drp_daddr[4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr121 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [5]), + .O(drp_daddr[5]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr131 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [6]), + .O(drp_daddr[6]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr141 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [7]), + .O(drp_daddr[7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr151 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [8]), + .O(drp_daddr[8]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_daddr161 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_addr_dclk [9]), + .O(drp_daddr[9]) + ); + LUT2 #( + .INIT ( 4'hE )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_drp_req1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ), + .O(drp_req) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_reg_2107 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_cs_dclk_ipif_cs_dclk_reg_AND_331_o ) + ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk1 ( @@ -28054,6 +29328,167 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ) ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/den1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .O(drp_den) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT91 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [17]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [17]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [17]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [17]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<17> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT81 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [16]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [16]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [16]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [16]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<16> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT71 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [15]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [15]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [15]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [15]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<15> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT61 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [14]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [14]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [14]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [14]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<14> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT51 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [13]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [13]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [13]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [13]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<13> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT41 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [12]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [12]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [12]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [12]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<12> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT341 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [9]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [9]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [9]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [9]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<9> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT331 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [8]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [8]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [8]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [8]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<8> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT321 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [7]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [7]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [7]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [7]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<7> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT311 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [6]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [6]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [6]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [6]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<6> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT301 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [5]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [5]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [5]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [5]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<5> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT31 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [11]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [11]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [11]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [11]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<11> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT291 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [4]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [4]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [4]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [4]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<4> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT281 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [3]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [3]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [3]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [3]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<3> ) + ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT271 ( @@ -28076,59 +29511,257 @@ loopback_ctrl .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [32]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<32> ) ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT251 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [31]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [31]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [31]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [31]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<31> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT241 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [30]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [30]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [30]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [30]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<30> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT231 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [2]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [2]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [2]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<2> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT221 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [29]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [29]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [29]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [29]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<29> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT211 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [28]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [28]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [28]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [28]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<28> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT201 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [27]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [27]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [27]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [27]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<27> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT21 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [10]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [10]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [10]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [10]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<10> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT191 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [26]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [26]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [26]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [26]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<26> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT181 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [25]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [25]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [25]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [25]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<25> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT171 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [24]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [24]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [24]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [24]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<24> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT161 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [23]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [23]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [23]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [23]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<23> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT151 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [22]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [22]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [22]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [22]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<22> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT141 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [21]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [21]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [21]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [21]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<21> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT131 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [20]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [20]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [20]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [20]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<20> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT121 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [1]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [1]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [1]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<1> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT111 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [19]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [19]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [19]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [19]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<19> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT101 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [18]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [18]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [18]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [18]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<18> ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [0]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [0]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [0]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<0> ) + ); LUT3 #( .INIT ( 8'hE4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In ) ); LUT3 #( .INIT ( 8'h72 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In ) ); LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ) ); LUT3 #( .INIT ( 8'h80 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [17]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [17]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [17]), @@ -28138,8 +29771,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [16]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [16]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [16]), @@ -28149,8 +29782,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [15]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [15]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [15]), @@ -28160,8 +29793,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [14]), @@ -28171,8 +29804,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [13]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [13]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [13]), @@ -28182,8 +29815,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [12]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [12]), @@ -28193,8 +29826,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [11]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [11]), @@ -28204,8 +29837,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [10]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [10]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [10]), @@ -28215,8 +29848,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT181 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [9]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [9]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [9]), @@ -28226,8 +29859,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT171 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [8]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [8]), @@ -28237,8 +29870,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [7]), @@ -28248,8 +29881,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [6]), @@ -28259,8 +29892,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [5]), @@ -28270,8 +29903,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [4]), @@ -28281,8 +29914,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [3]), @@ -28292,8 +29925,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [2]), @@ -28303,8 +29936,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [1]), @@ -28314,8 +29947,8 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [0]), @@ -28428,16 +30061,16 @@ loopback_ctrl LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00792 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ), .I1(txreset322), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2493 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val1 ( .I0(txreset322), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2493 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ) ); LUT3 #( @@ -28749,7 +30382,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [3]) @@ -28758,7 +30391,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [2]) @@ -28767,7 +30400,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [1]) @@ -28776,7 +30409,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<0>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [0]) @@ -28785,7 +30418,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [3]) @@ -28794,7 +30427,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [2]) @@ -28803,7 +30436,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [1]) @@ -28812,7 +30445,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<0>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [0]) @@ -28822,7 +30455,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2577 ) ); LUT2 #( .INIT ( 4'h6 )) @@ -28918,17 +30551,10 @@ loopback_ctrl LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ) ); - LUT2 #( - .INIT ( 4'h1 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert<3>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [2]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert ) - ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra_comb1 ( @@ -28944,7 +30570,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<0> ) @@ -28958,7 +30584,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [18]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<18> ) @@ -28972,7 +30598,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [19]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<19> ) @@ -28986,7 +30612,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<1> ) @@ -29000,7 +30626,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [20]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<20> ) @@ -29014,7 +30640,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [21]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<21> ) @@ -29028,7 +30654,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [22]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<22> ) @@ -29042,7 +30668,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [23]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<23> ) @@ -29056,7 +30682,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [25]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<25> ) @@ -29070,7 +30696,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [26]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<26> ) @@ -29084,7 +30710,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [10]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<10> ) @@ -29098,7 +30724,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [27]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<27> ) @@ -29112,7 +30738,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [28]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<28> ) @@ -29126,7 +30752,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [29]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<29> ) @@ -29140,7 +30766,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [30]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<30> ) @@ -29154,7 +30780,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [31]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<31> ) @@ -29168,7 +30794,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [32]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<32> ) @@ -29182,7 +30808,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [33]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<33> ) @@ -29196,7 +30822,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [11]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<11> ) @@ -29210,7 +30836,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [37]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<37> ) @@ -29224,7 +30850,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [38]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<38> ) @@ -29238,7 +30864,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [40]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<40> ) @@ -29252,7 +30878,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [41]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<41> ) @@ -29266,7 +30892,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [42]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<42> ) @@ -29280,7 +30906,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [43]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<43> ) @@ -29294,7 +30920,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [44]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<44> ) @@ -29308,7 +30934,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [12]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<12> ) @@ -29322,7 +30948,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [45]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<45> ) @@ -29336,7 +30962,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [46]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<46> ) @@ -29350,7 +30976,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [47]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<47> ) @@ -29364,7 +30990,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [48]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<48> ) @@ -29378,7 +31004,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [49]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<49> ) @@ -29392,7 +31018,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [50]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<50> ) @@ -29406,7 +31032,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [51]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<51> ) @@ -29420,7 +31046,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [52]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<52> ) @@ -29434,7 +31060,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [53]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<53> ) @@ -29448,7 +31074,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [13]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<13> ) @@ -29462,7 +31088,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [54]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<54> ) @@ -29476,7 +31102,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [55]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<55> ) @@ -29490,7 +31116,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [57]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<57> ) @@ -29504,7 +31130,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [58]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<58> ) @@ -29518,7 +31144,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [59]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<59> ) @@ -29532,7 +31158,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<5> ) @@ -29546,7 +31172,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [60]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<60> ) @@ -29560,7 +31186,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [61]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<61> ) @@ -29574,7 +31200,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [62]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<62> ) @@ -29588,7 +31214,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [14]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<14> ) @@ -29602,7 +31228,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [63]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<63> ) @@ -29616,7 +31242,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<6> ) @@ -29630,7 +31256,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [8]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<8> ) @@ -29644,7 +31270,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [9]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<9> ) @@ -29658,7 +31284,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [15]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<15> ) @@ -29672,7 +31298,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [16]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<16> ) @@ -29686,7 +31312,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [17]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<17> ) @@ -29700,7 +31326,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<1> ) @@ -29714,7 +31340,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<2> ) @@ -29728,7 +31354,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<3> ) @@ -29742,7 +31368,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<5> ) @@ -29756,7 +31382,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<6> ) @@ -29770,7 +31396,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [7]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<7> ) @@ -29779,12 +31405,12 @@ loopback_ctrl LUT6 #( .INIT ( 64'h66666EEE6EEE6EEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT11101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_3014 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_3015 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) @@ -31022,7 +32648,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [3]) @@ -31031,7 +32657,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [2]) @@ -31040,7 +32666,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [1]) @@ -31049,7 +32675,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<0>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [0]) @@ -31058,7 +32684,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<3>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [3]) @@ -31067,7 +32693,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<2>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [2]) @@ -31076,7 +32702,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [1]) @@ -31085,7 +32711,7 @@ loopback_ctrl .INIT ( 16'hA965 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<0>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [0]) @@ -31133,7 +32759,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_3238 ) ); LUT2 #( .INIT ( 4'h6 )) @@ -31142,13 +32768,6 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [1]) ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_ra_writesync<2>_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [2]) - ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_rd_addr[3]_rd_addr[2]_XOR_509_o_xo<0>1 ( @@ -31350,32 +32969,20 @@ loopback_ctrl LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ) ); LUT5 #( .INIT ( 32'h44404044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ) ); - LUT3 #( - .INIT ( 8'h69 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_xor<3>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]), - .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> ) -, - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<3> ) - - ); LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<0><3>1 ( @@ -31541,26 +33148,26 @@ loopback_ctrl LUT6 #( .INIT ( 64'hAAAA222AAAAAEEEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In ) ); LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_twist11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF4540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1171 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [56]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [24]), @@ -31568,7 +33175,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<24> ) @@ -31576,7 +33183,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFFFFFFFFFFFF4540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1521 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [24]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [56]), @@ -31584,7 +33191,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<56> ) @@ -31592,10 +33199,10 @@ loopback_ctrl LUT4 #( .INIT ( 16'h1014 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_jam_idle[0]_PWR_41_o_equal_16_o11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) @@ -31606,12 +33213,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<35> ) @@ -31622,12 +33229,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [36]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<36> ) @@ -31638,12 +33245,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [39]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<39> ) @@ -31654,12 +33261,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [35]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<3> ) @@ -31670,12 +33277,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [36]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<4> ) @@ -31686,12 +33293,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [39]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<7> ) @@ -31700,8 +33307,8 @@ loopback_ctrl .INIT ( 64'h5555555510111000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT111 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [32]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0]), @@ -31716,8 +33323,8 @@ loopback_ctrl .INIT ( 64'h5555555510111000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT181 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [48]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [16]), @@ -31732,8 +33339,8 @@ loopback_ctrl .INIT ( 64'h5555555510111000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1261 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [32]), @@ -31748,8 +33355,8 @@ loopback_ctrl .INIT ( 64'h5555555510111000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1351 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [40]), @@ -31764,8 +33371,8 @@ loopback_ctrl .INIT ( 64'h5555555510111000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1431 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [16]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [48]), @@ -31780,8 +33387,8 @@ loopback_ctrl .INIT ( 64'h5555555510111000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1631 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [40]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [8]), @@ -31795,12 +33402,12 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0101010101000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_jam_idle[1]_PWR_41_o_equal_19_o11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) @@ -31808,12 +33415,12 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555155544445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_rd_en11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ) ); LUT6 #( @@ -31825,9 +33432,9 @@ loopback_ctrl .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<0> ) @@ -32158,114 +33765,114 @@ loopback_ctrl ); LUT2 #( .INIT ( 4'hE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o1 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_539 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_540 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ) ); LUT2 #( .INIT ( 4'h8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_540 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_539 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ) ); LUT4 #( .INIT ( 16'hFFFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3641 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3639 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3640 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3642 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3381 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3624 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3625 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/out_comb ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3389 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3632 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3633 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/out_comb ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3385 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3628 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3629 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/out_comb ) ); LUT4 #( .INIT ( 16'hFFFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3661 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3659 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3660 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3662 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3401 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3644 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3645 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/out_comb ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3409 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3652 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3653 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/out_comb ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3405 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3648 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3649 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/out_comb ) ); LUT4 #( .INIT ( 16'hFFFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_557_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3681 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3679 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3680 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3682 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_557_o ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3421 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3665 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/out_comb ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3672 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3673 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/out_comb ) ); LUT2 #( .INIT ( 4'h6 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/Mxor_out_comb_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3425 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3668 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3669 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/out_comb ) ); LUT5 #( @@ -32299,7 +33906,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) ); LUT6 #( @@ -32351,11 +33958,11 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT921 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT92 ) ); @@ -32489,7 +34096,7 @@ loopback_ctrl .INIT ( 64'h8000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o12 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), @@ -32532,7 +34139,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o<7>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), @@ -32556,7 +34163,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ) ); LUT5 #( .INIT ( 32'h80000000 )) @@ -32656,7 +34263,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), @@ -32671,7 +34278,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ) @@ -32733,8 +34340,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3687 ) ); LUT4 #( .INIT ( 16'hEA40 )) @@ -32746,7 +34353,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 ) @@ -32814,7 +34421,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'h55404040 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT641 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ), @@ -32827,7 +34434,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'h55404040 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT661 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [7]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ), @@ -32840,7 +34447,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555404040 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT341 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [1]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ), @@ -32855,7 +34462,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555404040 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT561 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [3]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ), @@ -32891,7 +34498,7 @@ loopback_ctrl .INIT ( 8'hFB )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT114111 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ) ); @@ -32901,12 +34508,12 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), @@ -32937,7 +34544,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 ) @@ -33003,7 +34610,7 @@ loopback_ctrl .INIT ( 16'h0002 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), @@ -33036,7 +34643,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) ); @@ -33095,10 +34702,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 ) @@ -33106,21 +34713,21 @@ loopback_ctrl LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_t_type_reg[2]_GND_22_o_mux_458_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<0> ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_t_type_reg[2]_GND_22_o_mux_458_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<1> ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_t_type_reg[2]_GND_22_o_mux_458_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<2> ) ); @@ -33130,7 +34737,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [0]), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [0]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ), @@ -33143,7 +34750,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [2]), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [2]), @@ -33158,7 +34765,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [4]), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [4]), @@ -33173,7 +34780,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [6]), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [6]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ), @@ -33192,7 +34799,7 @@ loopback_ctrl LUT2 #( .INIT ( 4'h1 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08561 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ) ); @@ -33572,14 +35179,14 @@ loopback_ctrl .INIT ( 4'h8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4087 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4331 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ) ); LUT2 #( .INIT ( 4'hD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ) ); LUT2 #( @@ -33594,7 +35201,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT191 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [26]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<26> ) ); @@ -33603,7 +35210,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT451 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [4]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<4> ) ); @@ -33612,7 +35219,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT631 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [6]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<6> ) ); @@ -33621,7 +35228,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT19 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<0> ) ); @@ -33631,9 +35238,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In ) ); LUT6 #( @@ -33641,19 +35248,19 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In ) ); LUT6 #( .INIT ( 64'hFFFFFFFFC944C946 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT10221 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O @@ -33663,17 +35270,17 @@ loopback_ctrl .INIT ( 32'h77557699 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1211 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) ); LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT310 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [11]), @@ -33682,7 +35289,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT45 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [12]), @@ -33691,7 +35298,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT510 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [13]), @@ -33700,7 +35307,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT63 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [14]), @@ -33709,7 +35316,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [19]), @@ -33718,7 +35325,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [20]), @@ -33727,7 +35334,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [21]), @@ -33736,7 +35343,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT181 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [25]), @@ -33745,7 +35352,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT201 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [27]), @@ -33754,7 +35361,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT211 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [28]), @@ -33763,7 +35370,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT261 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [32]), @@ -33772,7 +35379,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT271 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [33]), @@ -33781,7 +35388,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT281 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [34]), @@ -33790,7 +35397,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT291 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [35]), @@ -33799,7 +35406,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT331 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [39]), @@ -33808,7 +35415,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT341 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [3]), @@ -33817,7 +35424,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT351 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [40]), @@ -33826,7 +35433,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT361 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [41]), @@ -33835,7 +35442,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT371 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [42]), @@ -33844,7 +35451,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT411 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [46]), @@ -33853,7 +35460,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT421 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [47]), @@ -33862,7 +35469,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT431 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [48]), @@ -33871,7 +35478,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT441 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [49]), @@ -33880,7 +35487,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT491 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [53]), @@ -33889,7 +35496,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT501 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [54]), @@ -33898,7 +35505,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT511 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [55]), @@ -33907,7 +35514,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT521 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [56]), @@ -33916,7 +35523,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT561 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [5]), @@ -33925,7 +35532,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT581 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [61]), @@ -33934,7 +35541,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT591 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [62]), @@ -33943,7 +35550,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT571 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [60]), @@ -33952,7 +35559,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT601 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [63]), @@ -33961,7 +35568,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h54 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [18]), @@ -33971,62 +35578,62 @@ loopback_ctrl .INIT ( 16'hFF08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT231 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<2> ) ); LUT4 #( .INIT ( 16'hFF08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT541 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [58]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<58> ) ); LUT4 #( .INIT ( 16'hFF08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT651 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<8> ) ); LUT6 #( - .INIT ( 64'h2888888888888888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .INIT ( 64'h0010100010001000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT31 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<2> ) ); - LUT5 #( - .INIT ( 32'h28888888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<3> ) + LUT6 #( + .INIT ( 64'h1444444444444444 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<4>11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 ) ); LUT5 #( - .INIT ( 32'h28888888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>12 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ), + .INIT ( 32'h14444444 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), @@ -34034,163 +35641,180 @@ loopback_ctrl .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt3 ) ); LUT6 #( - .INIT ( 64'h8888888828888888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<6> ) - ); - LUT5 #( - .INIT ( 32'h88882888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<5> ) - ); - LUT6 #( - .INIT ( 64'h0400040000000400 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_slip_int11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<1>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 ) - ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<1> ) + .INIT ( 64'h0880808080808080 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT41 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ) +, + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<3> ) ); - LUT3 #( - .INIT ( 8'h28 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), + LUT4 #( + .INIT ( 16'h8000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Madd_sh_cnt[5]_GND_26_o_add_37_OUT_cy<3>11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<1> ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Madd_sh_cnt[5]_GND_26_o_add_37_OUT_cy<3> ) ); - LUT6 #( - .INIT ( 64'hFFFFFFFF08080888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ) + LUT5 #( + .INIT ( 32'h08808080 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT31 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ) +, + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<2> ) ); LUT4 #( - .INIT ( 16'h2888 )) + .INIT ( 16'h1444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<2>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt2 ) ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n01391 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0139 ) + ); + LUT6 #( + .INIT ( 64'h0000002000000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_slip_done_cnt[4]_GND_26_o_MUX_399_o11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_399_o ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mxor_sh_valid_xo<0>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ) + ); LUT4 #( - .INIT ( 16'h2888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<2> ) + .INIT ( 16'h0880 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT51 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ) +, + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Madd_sh_cnt[5]_GND_26_o_add_37_OUT_cy<3> ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<4> ) + ); + LUT5 #( + .INIT ( 32'h08808080 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT61 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ) +, + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Madd_sh_cnt[5]_GND_26_o_add_37_OUT_cy<3> ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<5> ) ); LUT4 #( - .INIT ( 16'h2888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), + .INIT ( 16'h0880 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ) +, + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<2> ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<1> ) ); - LUT3 #( - .INIT ( 8'h7F )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT4111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ) - ); - LUT5 #( - .INIT ( 32'h00000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT221 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ) + LUT6 #( + .INIT ( 64'h2828280828282828 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0187_inv ) ); - LUT2 #( - .INIT ( 4'h6 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ) + LUT6 #( + .INIT ( 64'h8000000000000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n00341 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ) ); LUT6 #( - .INIT ( 64'h0000000000800000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_slip_done_cnt[4]_GND_26_o_MUX_394_o11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_394_o ) + .INIT ( 64'h2808080828082828 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0210_inv ) ); - LUT2 #( - .INIT ( 4'h4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<0>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt ) + LUT4 #( + .INIT ( 16'h8000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n00151 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ) ); - LUT3 #( - .INIT ( 8'hFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_state[2]_GND_26_o_Mux_27_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[2]_GND_26_o_Mux_27_o ) + LUT5 #( + .INIT ( 32'h6EAA2AAA )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4660 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4661 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In ) + ); + LUT2 #( + .INIT ( 4'hE )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_state[1]_PWR_27_o_Mux_51_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_PWR_27_o_Mux_51_o ) ); LUT2 #( .INIT ( 4'hD )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4466 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4465 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ) ); LUT6 #( .INIT ( 64'h2888888888888888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<4>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]), @@ -34201,7 +35825,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'h28888888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<3>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]), @@ -34211,7 +35835,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h28 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<1>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt1 ) @@ -34219,7 +35843,7 @@ loopback_ctrl LUT4 #( .INIT ( 16'h2888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<2>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]), @@ -34235,9 +35859,9 @@ loopback_ctrl LUT3 #( .INIT ( 8'hFB )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT171 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT17 ) @@ -34246,22 +35870,22 @@ loopback_ctrl .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<0>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt ) ); LUT3 #( .INIT ( 8'hFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_state[2]_GND_27_o_Mux_25_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state__n0148<0>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_25_o ) ); LUT2 #( .INIT ( 4'h8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_state[2]_GND_27_o_Mux_27_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state__n0148<1>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_27_o ) ); LUT3 #( @@ -34805,15 +36429,15 @@ loopback_ctrl LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ) ); LUT2 #( .INIT ( 4'h1 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data [0]) ); LUT2 #( @@ -34845,17 +36469,17 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) ); LUT6 #( .INIT ( 64'h2323030323220300 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT541 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [60]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), @@ -34864,7 +36488,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555555554 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ), @@ -34875,7 +36499,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555555554 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), @@ -34887,7 +36511,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555555554 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I2 @@ -35024,12 +36648,12 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0C0E000A0C0C0000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT531 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_4991 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_5232 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [59]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), @@ -35237,13 +36861,13 @@ loopback_ctrl ); LUT4 #( .INIT ( 16'h8000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o1_4941 ) ); LUT4 #( @@ -35303,22 +36927,22 @@ loopback_ctrl ); LUT3 #( .INIT ( 8'h80 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o311 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o311 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o31 ) ); LUT6 #( .INIT ( 64'h1000000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o2_4950 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o ) ); LUT4 #( .INIT ( 16'hFFFE )) @@ -35603,28 +37227,28 @@ loopback_ctrl LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_reg[2]_GND_30_o_mux_145_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<0> ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_reg[2]_GND_30_o_mux_145_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<1> ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_reg[2]_GND_30_o_mux_145_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<2> ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ) ); @@ -35642,9 +37266,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [56]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<56> ) ); LUT6 #( @@ -35654,9 +37278,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [24]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<24> ) ); LUT6 #( @@ -35665,9 +37289,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 ) ); LUT3 #( @@ -36254,7 +37878,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT51 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [4]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<4> ) ); @@ -36262,7 +37886,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1281 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [34]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<34> ) ); @@ -36270,7 +37894,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1291 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [35]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<35> ) ); @@ -36278,7 +37902,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1301 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [36]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<36> ) ); @@ -36286,7 +37910,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1331 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [39]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<39> ) ); @@ -36294,7 +37918,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1341 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<3> ) ); @@ -36302,7 +37926,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1451 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [4]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<4> ) ); @@ -36310,7 +37934,7 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1621 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [7]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<7> ) ); @@ -36318,14 +37942,14 @@ loopback_ctrl .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<2> ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ) ); @@ -36342,43 +37966,43 @@ loopback_ctrl .INIT ( 64'h0002555755570002 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4]), .I5(N2), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1489 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1525 ) ); LUT2 #( .INIT ( 4'hD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), .O(N4) ); LUT6 #( .INIT ( 64'hAA2AEE6EAA2AAA6E )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), .I4(N4), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1499 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1535 ) ); LUT4 #( .INIT ( 16'h7FFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_356_o_SW0 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .O(N6) ); LUT6 #( .INIT ( 64'h0000000000000002 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_356_o ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3]), @@ -36386,12 +38010,12 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4]), .I5(N6), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_356_o_1666 ) ); LUT6 #( .INIT ( 64'h6FF6FFFFFFFF6FF6 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o5_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_88_o5_SW0 ( .I0(prtad[0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I2(prtad[1]), @@ -36402,68 +38026,68 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h41000041 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o5 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_88_o5 ( .I0(N8), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I2(prtad[3]), .I3(prtad[4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_88_o ) ); LUT3 #( .INIT ( 8'hBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5153 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5394 ) ); LUT6 #( .INIT ( 64'hAAAAAAAA20002222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5153 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5154 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_88_o ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1679 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5394 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5395 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF8A808E8C )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5154 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5395 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In ) ); LUT3 #( .INIT ( 8'h8D )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .O(N10) ); LUT6 #( .INIT ( 64'hCCDF2033AAAAAAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), .I3(N10), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1502 ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1538 ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]), @@ -36471,12 +38095,12 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1_5156 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o1_5397 ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]), @@ -36484,29 +38108,29 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2_5157 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o2_5398 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFBFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o3 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o3 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2_5157 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o2_5398 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1_5156 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o1_5397 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_134_o ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]), @@ -36514,12 +38138,12 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1_5158 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o1_5399 ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]), @@ -36527,29 +38151,29 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2_5159 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o2_5400 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFBFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o3 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o3 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2_5159 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o2_5400 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1_5158 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o1_5399 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_128_o ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]), @@ -36557,12 +38181,12 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1_5160 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o1_5401 ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]), @@ -36570,24 +38194,24 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2_5161 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o2_5402 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFBFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o3 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o3 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2_5161 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o2_5402 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1_5160 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o1_5401 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_131_o ) ); LUT6 #( @@ -36789,7 +38413,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5179 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5420 ) ); LUT6 #( @@ -36803,7 +38427,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15> ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5179 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5420 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ) @@ -36820,7 +38444,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT91 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5181 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5422 ) ); LUT6 #( @@ -36833,7 +38457,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5182 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5423 ) ); LUT3 #( @@ -36843,14 +38467,14 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5183 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5424 ) ); LUT6 #( .INIT ( 64'hFFFFF888F888F888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT96 ) @@ -36858,58 +38482,142 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5182 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5423 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5181 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5422 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5185 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5426 ) ); LUT6 #( .INIT ( 64'hAAAAA888A888A888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5185 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5426 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1993 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5186 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5427 ) ); LUT5 #( .INIT ( 32'hAA808080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT910 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1996 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ), .I4(pma_pmd_type[2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5187 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5428 ) + + ); + LUT5 #( + .INIT ( 32'hAA808080 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) +, + .I1 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) +, + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [13]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [13]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5432 ) + + ); + LUT6 #( + .INIT ( 64'hA888200020002000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [13]), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) +, + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [13]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5433 ) + + ); + LUT5 #( + .INIT ( 32'hD9C85140 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [13]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [13]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [13]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5434 ) + + ); + LUT6 #( + .INIT ( 64'hFFFFFFF8FFF8FFF8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT57 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), + .I1 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5434 ) +, + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5433 ) +, + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5432 ) +, + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [13]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5435 ) + + ); + LUT6 #( + .INIT ( 64'hFFFFFFFFAAAAA888 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT58 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), + .I1 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5435 ) +, + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [13]), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5431 ) +, + .I5 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ) +, + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT57_5436 ) ); LUT6 #( .INIT ( 64'h2020200000200000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1251 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1287 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1963 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 ) ); @@ -36917,7 +38625,7 @@ loopback_ctrl .INIT ( 32'hAA808080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) @@ -36926,7 +38634,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5189 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5438 ) ); LUT6 #( @@ -36941,7 +38649,7 @@ loopback_ctrl , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5190 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5439 ) ); LUT6 #( @@ -36951,16 +38659,16 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [11]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5189 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5438 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5190 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5439 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5191 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5440 ) ); LUT2 #( @@ -36969,24 +38677,24 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5192 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5441 ) ); LUT6 #( .INIT ( 64'hAAAA008000800080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5192 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5441 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [11]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [3]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5193 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5442 ) ); LUT5 #( @@ -36998,58 +38706,145 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5194 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5443 ) ); - LUT4 #( - .INIT ( 16'h8000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + LUT6 #( + .INIT ( 64'h2222222220202000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT310 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38 ) +, + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5440 ) +, + .I5 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 ) +, + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [11]) + ); + LUT6 #( + .INIT ( 64'hFF8F8F8FF8888888 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [9]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) +, + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [9]), + .I5 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5446 ) +, + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5447 ) + + ); + LUT5 #( + .INIT ( 32'hAA808080 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) +, .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5194 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [9]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [9]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37_5195 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5448 ) ); LUT6 #( - .INIT ( 64'h5555555555550040 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT39 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1250 ), + .INIT ( 64'hA888200020002000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [9]), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) +, + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [9]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5449 ) + + ); + LUT5 #( + .INIT ( 32'hD9C85140 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [9]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [9]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [9]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5450 ) + + ); + LUT6 #( + .INIT ( 64'hFFFFFFF8FFF8FFF8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), + .I1 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5450 ) +, .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5449 ) +, + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5448 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5193 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [9]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5451 ) + + ); + LUT6 #( + .INIT ( 64'hEAEAEAEAFFEAEAEA )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT168 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5451 ) , - .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37_5195 ) + .I1 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [9]), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5447 ) , + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38_5196 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5452 ) ); LUT6 #( - .INIT ( 64'h2222222220202000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT310 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38_5196 ) + .INIT ( 64'hFFFFFFFFAA808080 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT169 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5445 ) , + .I1 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5191 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5452 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [11]) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [9]) ); LUT6 #( .INIT ( 64'hFF8F8F8FF8888888 )) @@ -37059,21 +38854,21 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [6]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5197 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5453 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5198 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5454 ) ); LUT5 #( .INIT ( 32'hAA808080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) @@ -37082,7 +38877,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5199 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5455 ) ); LUT6 #( @@ -37096,7 +38891,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5200 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5456 ) ); LUT6 #( @@ -37111,7 +38906,7 @@ loopback_ctrl , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5201 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5457 ) ); LUT6 #( @@ -37120,64 +38915,64 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5201 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5457 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5200 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5456 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5199 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5455 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5202 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5458 ) ); LUT6 #( .INIT ( 64'hEAEAEAEAFFEAEAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5202 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5458 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [6]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5198 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5454 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5203 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5459 ) ); LUT6 #( .INIT ( 64'hFFFFAA08AA08AA08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT138 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 ) , .I2(pma_pmd_type[0]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5203 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5459 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5204 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5460 ) ); LUT5 #( .INIT ( 32'hAA808080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1963 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 ) , @@ -37194,14 +38989,14 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [7]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5206 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5462 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5207 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5463 ) ); LUT6 #( @@ -37216,7 +39011,7 @@ loopback_ctrl , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5208 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5464 ) ); LUT5 #( @@ -37228,7 +39023,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5209 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5465 ) ); LUT5 #( @@ -37237,19 +39032,19 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5209 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5465 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5208 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5464 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5210 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5466 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5211 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5467 ) ); LUT5 #( @@ -37257,47 +39052,47 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1962 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5211 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5467 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5212 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5468 ) ); LUT6 #( .INIT ( 64'hEAEAEAEAFFEAEAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT149 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5212 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5468 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [7]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5207 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5463 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5213 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5469 ) ); LUT5 #( .INIT ( 32'h22202020 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1410 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5213 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5469 ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [7]) ); @@ -37305,7 +39100,7 @@ loopback_ctrl .INIT ( 64'hAAAAA888A888A888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT111 ) @@ -37318,7 +39113,7 @@ loopback_ctrl , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5215 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5471 ) ); LUT6 #( @@ -37331,7 +39126,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5218 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5474 ) ); LUT6 #( @@ -37340,32 +39135,32 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5218 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5474 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5217 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5473 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5215 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5471 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5219 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5475 ) ); LUT6 #( .INIT ( 64'h4040404040000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [4]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5219 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5475 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [4]) @@ -37379,10 +39174,10 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5221 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5477 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5222 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5478 ) ); LUT6 #( @@ -37395,17 +39190,17 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5223 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5479 ) ); LUT5 #( .INIT ( 32'hFFA8A8A8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5224 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5480 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT106 ) @@ -37413,10 +39208,10 @@ loopback_ctrl .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5223 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5479 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5226 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5482 ) ); LUT6 #( @@ -37426,30 +39221,30 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [3]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5222 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5478 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5226 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5482 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5227 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5483 ) ); LUT6 #( .INIT ( 64'h2222200020002000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1010 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5227 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5483 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [3]) ); @@ -37463,7 +39258,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5228 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5484 ) ); LUT6 #( @@ -37476,7 +39271,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5232 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5488 ) ); LUT6 #( @@ -37485,10 +39280,10 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5232 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5488 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5231 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5487 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT122 ) @@ -37497,7 +39292,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5233 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5489 ) ); LUT6 #( @@ -37505,138 +39300,121 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .I2(pma_pmd_type[1]), .I3(pma_pmd_type[2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5233 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5489 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5234 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5490 ) ); LUT6 #( .INIT ( 64'hA282A08022022000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [14]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [14]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [14]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [10]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [10]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5236 ) - +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT66 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5494 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5238 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5493 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5236 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1962 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5495 ) ); - LUT6 #( - .INIT ( 64'hAAAAA888A888A888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT67 ( + LUT5 #( + .INIT ( 32'hFFF8F8F8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 ) -, - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5240 ) -, - .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [14]), - .I4 + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [10]), + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5495 ) +, + .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [14]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [14]) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5496 ) + ); LUT6 #( - .INIT ( 64'hFD75B931EC64A820 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [8]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [8]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [8]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [8]), + .INIT ( 64'hA282A08022022000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [14]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [14]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5241 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5498 ) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT66 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5245 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5501 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5244 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5500 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5242 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5498 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [8]), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5246 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5502 ) ); LUT6 #( .INIT ( 64'hAAAAA888A888A888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT157 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT67 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 ) +, .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5246 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5502 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [8]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [14]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [8]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5247 ) - - ); - LUT6 #( - .INIT ( 64'h2222222220202000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT158 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ), - .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5247 ) -, + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [8]) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [14]) ); LUT3 #( .INIT ( 8'hBF )) @@ -37649,13 +39427,13 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ), .I3(NlwRenamedSig_OI_pcs_resetout), .I4(N44), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ) ); LUT6 #( .INIT ( 64'hA282A08022022000 )) @@ -37668,53 +39446,53 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [12]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41_5249 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41 ) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5252 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5507 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5251 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5506 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41_5249 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5253 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5508 ) ); LUT6 #( .INIT ( 64'hAAAAA888A888A888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT47 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5253 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5508 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1992 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5254 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5509 ) ); LUT6 #( .INIT ( 64'hAAAAAAAA00000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT48 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5445 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), .I2 @@ -37723,127 +39501,75 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5254 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5509 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [12]) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [9]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [9]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [9]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [9]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [8]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [8]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [8]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5255 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5510 ) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5259 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5514 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5258 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5513 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5256 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5511 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [9]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5260 ) - - ); - LUT6 #( - .INIT ( 64'hAAAAA888A888A888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5260 ) -, - .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [9]), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [9]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5261 ) - - ); - LUT6 #( - .INIT ( 64'hA282A08022022000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [13]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [13]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [13]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5264 ) - - ); - LUT5 #( - .INIT ( 32'hFFFEFEFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5267 ) -, - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5264 ) -, - .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) -, - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5265 ) -, + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5268 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5515 ) ); LUT6 #( .INIT ( 64'hAAAAA888A888A888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT57 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT157 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5268 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5515 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [13]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [8]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [13]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5269 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5516 ) ); LUT6 #( .INIT ( 64'h2222222020222020 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), .I4 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT7 ) ); @@ -37858,38 +39584,38 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [15]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5271 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5519 ) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5274 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5522 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5273 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5521 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5271 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5519 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5275 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5523 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF22202020 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT77 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5275 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5523 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [15]), .I4 @@ -37898,79 +39624,8 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT7 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5276 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5524 ) - ); - LUT6 #( - .INIT ( 64'hA282A08022022000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [10]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [10]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [10]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 ) - - ); - LUT6 #( - .INIT ( 64'hFFFFFFF8FFF8FFF8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) -, - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5281 ) -, - .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5280 ) -, - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 ) -, - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5282 ) - - ); - LUT6 #( - .INIT ( 64'hAAAAA888A888A888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT27 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5282 ) -, - .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [10]), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [10]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26_5283 ) - - ); - LUT6 #( - .INIT ( 64'hAAAAAAAA80000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT28 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ) -, - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), - .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) -, - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26_5283 ) -, - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [10]) ); LUT5 #( .INIT ( 32'h28200800 )) @@ -37979,7 +39634,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1959 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1995 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1 ) ); @@ -38002,7 +39657,7 @@ loopback_ctrl .I5 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5285 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5526 ) ); LUT6 #( @@ -38015,13 +39670,13 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5288 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5529 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5289 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5530 ) ); LUT6 #( @@ -38031,16 +39686,16 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [0]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5289 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5530 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5287 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5528 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5290 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5531 ) ); LUT6 #( @@ -38056,33 +39711,33 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5291 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5532 ) ); LUT6 #( .INIT ( 64'hAAAAAAAAAAAAAA80 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1990 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5292 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5533 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5290 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5531 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5291 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5532 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5293 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5534 ) ); LUT5 #( .INIT ( 32'hAAA8A8A8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ), .I2 @@ -38102,13 +39757,13 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5296 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5537 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5297 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5538 ) ); LUT6 #( @@ -38118,16 +39773,16 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [1]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5297 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5538 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5536 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5298 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5539 ) ); LUT6 #( @@ -38143,27 +39798,27 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5299 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5540 ) ); LUT6 #( .INIT ( 64'hAAAAAAAAAAAAAA80 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT89 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1991 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5300 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5541 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5298 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5539 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5299 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5540 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5301 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT89_5542 ) ); LUT6 #( @@ -38176,7 +39831,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [15]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ) ); LUT6 #( .INIT ( 64'h8000000000000000 )) @@ -38188,15 +39843,15 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [9]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ) ); LUT2 #( .INIT ( 4'h8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode13 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ) ); LUT6 #( @@ -38219,31 +39874,31 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [8]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [7]), .I5(N46), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ) ); LUT2 #( .INIT ( 4'h8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]), .O(N48) ); LUT6 #( .INIT ( 64'h2AAAAAAAAAAAAAAA )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_696 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_732 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]), .I5(N48), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_193_o_2490 ) ); LUT4 #( .INIT ( 16'h8000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]), @@ -38252,20 +39907,20 @@ loopback_ctrl ); LUT6 #( .INIT ( 64'h2AAAAAAAAAAAAAAA )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_695 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_731 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]), .I5(N50), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_194_o_2489 ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7]), @@ -38273,12 +39928,12 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1_5307 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o1_5548 ) ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1]), @@ -38286,35 +39941,35 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2_5308 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o2_5549 ) ); LUT4 #( .INIT ( 16'h7FFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3_5309 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o3_5550 ) ); LUT4 #( .INIT ( 16'hAAA8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o4 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_694 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o4 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_730 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2_5308 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o2_5549 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3_5309 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o3_5550 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1_5307 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o1_5548 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_195_o ) ); LUT2 #( @@ -38340,39 +39995,39 @@ loopback_ctrl .I3(N54), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2493 ) ); LUT4 #( .INIT ( 16'hF888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_3015 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5312 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_3014 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5553 ) ); LUT6 #( .INIT ( 64'h0202722200007000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_3014 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_3015 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5313 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5554 ) ); LUT6 #( .INIT ( 64'h0100ABAA01000100 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5313 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5554 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5314 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5555 ) ); LUT6 #( .INIT ( 64'h2000000000000000 )) @@ -38384,7 +40039,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5315 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5556 ) ); LUT6 #( .INIT ( 64'h0000000000000001 )) @@ -38396,16 +40051,16 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5316 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5557 ) ); LUT3 #( .INIT ( 8'hEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [0]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5315 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5556 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5316 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5557 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]) ); LUT6 #( @@ -38418,7 +40073,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5317 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5558 ) ); LUT6 #( .INIT ( 64'h0000000000000001 )) @@ -38430,16 +40085,16 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5318 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5559 ) ); LUT3 #( .INIT ( 8'hEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5317 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5558 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5318 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5559 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]) ); LUT6 #( @@ -38448,38 +40103,38 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5319 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5560 ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5320 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5561 ) ); LUT6 #( .INIT ( 64'h0080008000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5320 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5561 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5568 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5321 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5562 ) ); LUT2 #( .INIT ( 4'h8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08544 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5319 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5321 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5560 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5562 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0854 ) ); LUT6 #( @@ -38491,8 +40146,8 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5324 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5325 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5565 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5566 ) ); LUT5 #( .INIT ( 32'h55554000 )) @@ -38501,7 +40156,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT173 ) @@ -38513,7 +40168,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out142 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3687 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT14 ) ); LUT6 #( @@ -38522,12 +40177,12 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5332 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5573 ) ); LUT6 #( .INIT ( 64'h2A2A2AAA08080888 )) @@ -38549,7 +40204,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]), - .O(N58) + .O(N60) ); LUT6 #( .INIT ( 64'h04400440F4400440 )) @@ -38559,7 +40214,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]), - .I5(N58), + .I5(N60), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [6]) ); LUT4 #( @@ -38569,7 +40224,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]), - .O(N60) + .O(N62) ); LUT6 #( .INIT ( 64'h0000800011119111 )) @@ -38578,7 +40233,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]), - .I4(N60), + .I4(N62), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [5]) ); @@ -38590,7 +40245,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]), - .O(N62) + .O(N64) ); LUT6 #( .INIT ( 64'h04400440F4400440 )) @@ -38600,7 +40255,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]), - .I5(N62), + .I5(N64), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [6]) ); LUT4 #( @@ -38610,7 +40265,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]), - .O(N64) + .O(N66) ); LUT6 #( .INIT ( 64'h0000800011119111 )) @@ -38619,7 +40274,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]), - .I4(N64), + .I4(N66), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [5]) ); @@ -38630,7 +40285,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]), - .O(N66) + .O(N68) ); LUT6 #( .INIT ( 64'h0000008088000080 )) @@ -38640,7 +40295,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]), - .I5(N66), + .I5(N68), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [5]) ); LUT2 #( @@ -38648,7 +40303,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5343 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5584 ) ); LUT4 #( .INIT ( 16'h4002 )) @@ -38657,17 +40312,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5344 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5585 ) ); LUT6 #( .INIT ( 64'hA880808028000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5343 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5584 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5344 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5585 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [6]) ); LUT4 #( @@ -38677,7 +40332,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]), - .O(N68) + .O(N70) ); LUT6 #( .INIT ( 64'h0000008088000080 )) @@ -38687,7 +40342,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]), - .I5(N68), + .I5(N70), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [5]) ); LUT2 #( @@ -38695,7 +40350,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5346 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5587 ) ); LUT4 #( .INIT ( 16'h4002 )) @@ -38704,17 +40359,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5347 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5588 ) ); LUT6 #( .INIT ( 64'hA880808028000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5346 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5587 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5347 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5588 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [6]) ); LUT4 #( @@ -38724,7 +40379,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]), - .O(N70) + .O(N72) ); LUT6 #( .INIT ( 64'h0000008088000080 )) @@ -38734,7 +40389,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]), - .I5(N70), + .I5(N72), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [5]) ); LUT2 #( @@ -38742,7 +40397,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5349 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5590 ) ); LUT4 #( .INIT ( 16'h4002 )) @@ -38751,17 +40406,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5350 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5591 ) ); LUT6 #( .INIT ( 64'hA880808028000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5349 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5590 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5350 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5591 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [6]) ); LUT4 #( @@ -38771,7 +40426,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]), - .O(N72) + .O(N74) ); LUT6 #( .INIT ( 64'h0000008088000080 )) @@ -38781,7 +40436,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]), - .I5(N72), + .I5(N74), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [5]) ); LUT2 #( @@ -38789,7 +40444,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5352 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5593 ) ); LUT4 #( .INIT ( 16'h4002 )) @@ -38798,17 +40453,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5353 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5594 ) ); LUT6 #( .INIT ( 64'hA880808028000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5352 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5593 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5353 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5594 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [6]) ); LUT4 #( @@ -38818,7 +40473,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]), - .O(N74) + .O(N76) ); LUT6 #( .INIT ( 64'h0000008088000080 )) @@ -38828,7 +40483,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]), - .I5(N74), + .I5(N76), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [5]) ); LUT2 #( @@ -38836,7 +40491,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5355 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5596 ) ); LUT4 #( .INIT ( 16'h4002 )) @@ -38845,17 +40500,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5356 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5597 ) ); LUT6 #( .INIT ( 64'hA880808028000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5355 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5596 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5356 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5597 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [6]) ); LUT4 #( @@ -38865,7 +40520,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]), - .O(N76) + .O(N78) ); LUT6 #( .INIT ( 64'h0000008088000080 )) @@ -38875,7 +40530,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]), - .I5(N76), + .I5(N78), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [5]) ); LUT2 #( @@ -38883,7 +40538,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5358 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5599 ) ); LUT4 #( .INIT ( 16'h4002 )) @@ -38892,17 +40547,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5359 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5600 ) ); LUT6 #( .INIT ( 64'hA880808028000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5358 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5599 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5359 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5600 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [6]) ); LUT6 #( @@ -38917,18 +40572,18 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [1]), - .O(N78) + .O(N80) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [1]), - .I4(N78), + .I4(N80), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<11> ) ); @@ -38944,18 +40599,18 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [2]), - .O(N80) + .O(N82) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT4 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [2]), - .I4(N80), + .I4(N82), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<12> ) ); @@ -38971,18 +40626,18 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [3]), - .O(N82) + .O(N84) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT5 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [3]), - .I4(N82), + .I4(N84), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<13> ) ); @@ -38998,18 +40653,18 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [4]), - .O(N84) + .O(N86) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT6 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [4]), - .I4(N84), + .I4(N86), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<14> ) ); @@ -39020,7 +40675,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -39028,18 +40683,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [1]), - .O(N86) + .O(N88) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT57 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [2]), - .I4(N86), + .I4(N88), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<60> ) ); @@ -39050,7 +40705,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -39058,18 +40713,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [2]), - .O(N88) + .O(N90) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT58 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [3]), - .I4(N88), + .I4(N90), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<61> ) ); @@ -39080,7 +40735,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -39088,18 +40743,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [3]), - .O(N90) + .O(N92) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT59 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [4]), - .I4(N90), + .I4(N92), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<62> ) ); @@ -39110,7 +40765,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -39118,66 +40773,66 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [4]), - .O(N92) + .O(N94) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT60 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [5]), - .I4(N92), + .I4(N94), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<63> ) ); LUT6 #( .INIT ( 64'h5554545455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT33 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3730 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [5]), - .I5(N94), + .I5(N96), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<39> ) ); LUT6 #( .INIT ( 64'h5554545455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT35 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3730 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [6]), - .I5(N96), + .I5(N98), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<40> ) ); LUT6 #( .INIT ( 64'h5554545455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT36 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3730 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [7]), - .I5(N98), + .I5(N100), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<41> ) ); @@ -39187,27 +40842,27 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [4]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [0]), - .O(N100) + .O(N102) ); LUT5 #( .INIT ( 32'h54445555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT37 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [0]), - .I4(N100), + .I4(N102), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<42> ) ); @@ -39216,7 +40871,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [2]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I3 @@ -39235,18 +40890,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5373 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5614 ) ); LUT5 #( .INIT ( 32'h55545454 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT483 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5373 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5614 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT48 ) @@ -39262,7 +40917,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I3 @@ -39281,18 +40936,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5375 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5616 ) ); LUT5 #( .INIT ( 32'h55545454 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT533 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5375 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5616 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT53 ) @@ -39314,19 +40969,19 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [0]), - .O(N102) + .O(N104) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [0]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [0]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N102), + .I5(N104), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<10> ) ); @@ -39341,19 +40996,19 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [5]), - .O(N104) + .O(N106) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT7 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [5]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N104), + .I5(N106), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<15> ) ); @@ -39368,19 +41023,19 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [6]), - .O(N106) + .O(N108) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT8 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [6]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N106), + .I5(N108), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<16> ) ); @@ -39389,7 +41044,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), - .O(N108) + .O(N110) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -39397,11 +41052,11 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), - .I3(N108), + .I3(N110), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) ); LUT3 #( @@ -39410,7 +41065,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]), - .O(N110) + .O(N112) ); LUT6 #( .INIT ( 64'h2000000000000000 )) @@ -39420,7 +41075,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]), - .I5(N110), + .I5(N112), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o ) ); LUT3 #( @@ -39430,7 +41085,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5381 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5622 ) ); LUT6 #( @@ -39440,7 +41095,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5381 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5622 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]), @@ -39449,7 +41104,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5382 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5623 ) ); LUT6 #( @@ -39458,16 +41113,16 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5383 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5624 ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5384 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5625 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5385 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5626 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5382 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5623 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) @@ -39489,7 +41144,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]), - .O(N112) + .O(N114) ); LUT6 #( .INIT ( 64'h2000000000000000 )) @@ -39499,7 +41154,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]), - .I5(N112), + .I5(N114), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ) ); LUT4 #( @@ -39518,7 +41173,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5389 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5630 ) ); LUT6 #( .INIT ( 64'h6444200020002000 )) @@ -39527,9 +41182,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code5 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5389 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5630 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5631 ) ); LUT4 #( .INIT ( 16'h0800 )) @@ -39539,7 +41194,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5631 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ) ); LUT6 #( @@ -39553,89 +41208,89 @@ loopback_ctrl .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [0]), - .O(N114) + .O(N116) ); LUT4 #( .INIT ( 16'h4055 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT40 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [3]), - .I3(N114), + .I3(N116), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<45> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT38 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [1]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), - .I5(N116), + .I5(N118), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<43> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT39 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [2]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), - .I5(N118), + .I5(N120), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<44> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [6]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N120), + .I5(N122), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<24> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT22 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [3]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [3]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N122), + .I5(N124), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<29> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT24 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [4]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [4]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N124), + .I5(N126), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<30> ) ); @@ -39648,19 +41303,19 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [0]), - .O(N126) + .O(N128) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT25 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [5]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N126), + .I5(N128), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<31> ) ); @@ -39676,7 +41331,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [5]), - .O(N128) + .O(N130) ); LUT6 #( .INIT ( 64'h011105553333FFFF )) @@ -39690,7 +41345,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [6]), - .O(N130) + .O(N132) ); LUT4 #( .INIT ( 16'h153F )) @@ -39701,7 +41356,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [1]), - .O(N132) + .O(N134) ); LUT4 #( .INIT ( 16'h153F )) @@ -39712,7 +41367,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [6]), - .O(N134) + .O(N136) ); LUT4 #( .INIT ( 16'h153F )) @@ -39723,7 +41378,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [7]), - .O(N136) + .O(N138) ); LUT5 #( .INIT ( 32'hAAA8A8A8 )) @@ -39735,9 +41390,9 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , - .O(N138) + .O(N140) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) @@ -39745,8 +41400,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [0]), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .I3(N138), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .I3(N140), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [0]), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), @@ -39757,7 +41412,7 @@ loopback_ctrl .INIT ( 64'h0000000000000002 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5404 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5645 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ), @@ -39768,10 +41423,10 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) ); LUT6 #( @@ -39786,14 +41441,14 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5711 ) ); LUT2 #( .INIT ( 4'hE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]), - .O(N140) + .O(N142) ); LUT6 #( .INIT ( 64'hAAA0888088808880 )) @@ -39802,26 +41457,26 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), - .I3(N140), + .I3(N142), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3730 ) ); LUT6 #( .INIT ( 64'hAAAAAAAA80008080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT55 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5409 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5650 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5410 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5411 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5651 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5652 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5412 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5653 ) ); LUT3 #( .INIT ( 8'hEB )) @@ -39829,7 +41484,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]), - .O(N142) + .O(N144) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -39838,10 +41493,10 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]), - .I4(N142), + .I4(N144), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) ); LUT3 #( @@ -39850,13 +41505,13 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [56]), - .O(N144) + .O(N146) ); LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o<63> ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62]), - .I1(N144), + .I1(N146), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [59]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61]), @@ -39879,7 +41534,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5416 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5657 ) ); LUT6 #( .INIT ( 64'h6444200020002000 )) @@ -39888,9 +41543,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [56]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code8 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5416 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5657 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5658 ) ); LUT4 #( .INIT ( 16'h0800 )) @@ -39900,7 +41555,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5658 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ) ); LUT4 #( @@ -39920,7 +41575,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]), - .O(N148) + .O(N150) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -39929,10 +41584,10 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]), - .I4(N148), + .I4(N150), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) ); LUT4 #( @@ -39951,7 +41606,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [29]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [28]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [30]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5421 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5662 ) ); LUT6 #( .INIT ( 64'h6444200020002000 )) @@ -39960,9 +41615,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [28]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code4 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5421 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5662 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5663 ) ); LUT4 #( .INIT ( 16'h0800 )) @@ -39972,7 +41627,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5663 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ) ); LUT3 #( @@ -39981,7 +41636,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [22]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16]), - .O(N150) + .O(N152) ); LUT6 #( .INIT ( 64'h0000000000800000 )) @@ -39991,7 +41646,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [19]), - .I5(N150), + .I5(N152), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ) ); LUT4 #( @@ -40010,7 +41665,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5425 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5666 ) ); LUT6 #( .INIT ( 64'h6444200020002000 )) @@ -40019,9 +41674,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code3 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5425 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5666 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5426 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5667 ) ); LUT4 #( .INIT ( 16'h0800 )) @@ -40031,7 +41686,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5426 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5667 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ) ); LUT3 #( @@ -40040,13 +41695,13 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [8]), - .O(N152) + .O(N154) ); LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o<15> ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [11]), - .I1(N152), + .I1(N154), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [10]), @@ -40069,7 +41724,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5429 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5670 ) ); LUT6 #( .INIT ( 64'h6444200020002000 )) @@ -40078,9 +41733,9 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code2 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5429 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5670 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5430 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5671 ) ); LUT4 #( .INIT ( 16'h0800 )) @@ -40090,7 +41745,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5430 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5671 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ) ); LUT6 #( @@ -40102,7 +41757,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5431 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5672 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF5551 )) @@ -40112,7 +41767,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5431 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5672 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [3]) ); LUT4 #( @@ -40122,7 +41777,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5432 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5673 ) ); LUT4 #( .INIT ( 16'h1151 )) @@ -40131,7 +41786,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5433 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5674 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFF76 )) @@ -40140,8 +41795,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5433 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5432 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5674 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5673 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [2]) ); LUT5 #( @@ -40152,7 +41807,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5434 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5675 ) ); LUT5 #( .INIT ( 32'h04545555 )) @@ -40162,14 +41817,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5435 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5676 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5434 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5435 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5676 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [1]) ); LUT6 #( @@ -40181,7 +41836,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5436 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5677 ) ); LUT6 #( .INIT ( 64'h0E0E0E0E0EAEFFFF )) @@ -40192,14 +41847,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5437 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5678 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5437 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5436 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5678 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5677 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [2]) ); LUT6 #( @@ -40211,7 +41866,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5438 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5679 ) ); LUT4 #( .INIT ( 16'h222A )) @@ -40220,17 +41875,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5439 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5680 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFDFFDDD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5439 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5680 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5438 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5679 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [4]) ); LUT5 #( @@ -40241,7 +41896,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5440 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5681 ) ); LUT5 #( .INIT ( 32'h04545555 )) @@ -40251,14 +41906,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5441 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5682 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5440 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5441 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5681 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5682 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [1]) ); LUT6 #( @@ -40270,7 +41925,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5442 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5683 ) ); LUT6 #( .INIT ( 64'h0E0E0E0E0EAEFFFF )) @@ -40281,14 +41936,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5443 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5684 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5443 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5442 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5684 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5683 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [2]) ); LUT6 #( @@ -40300,7 +41955,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5444 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5685 ) ); LUT4 #( .INIT ( 16'h222A )) @@ -40309,17 +41964,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5445 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5686 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFDFFDDD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5445 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5686 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5444 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5685 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [4]) ); LUT5 #( @@ -40330,7 +41985,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5446 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5687 ) ); LUT5 #( .INIT ( 32'h04545555 )) @@ -40340,14 +41995,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5447 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5688 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5446 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5447 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5687 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5688 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [1]) ); LUT6 #( @@ -40359,7 +42014,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5448 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5689 ) ); LUT6 #( .INIT ( 64'h0E0E0E0E0EAEFFFF )) @@ -40370,14 +42025,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5449 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5690 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5449 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5448 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5690 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5689 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [2]) ); LUT6 #( @@ -40389,7 +42044,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5450 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5691 ) ); LUT4 #( .INIT ( 16'h222A )) @@ -40398,17 +42053,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5451 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5692 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFDFFDDD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5451 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5692 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5450 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5691 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [4]) ); LUT5 #( @@ -40419,7 +42074,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5452 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5693 ) ); LUT5 #( .INIT ( 32'h04545555 )) @@ -40429,14 +42084,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5453 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5694 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5452 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5453 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5693 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5694 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [1]) ); LUT6 #( @@ -40448,7 +42103,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5454 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5695 ) ); LUT6 #( .INIT ( 64'h0E0E0E0E0EAEFFFF )) @@ -40459,14 +42114,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5455 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5696 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5455 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5454 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5696 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5695 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [2]) ); LUT6 #( @@ -40478,7 +42133,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5456 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5697 ) ); LUT4 #( .INIT ( 16'h222A )) @@ -40487,17 +42142,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5457 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5698 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFDFFDDD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5457 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5698 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5456 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5697 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [4]) ); LUT5 #( @@ -40508,7 +42163,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5458 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5699 ) ); LUT5 #( .INIT ( 32'h04545555 )) @@ -40518,14 +42173,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5459 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5700 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5458 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5459 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5699 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5700 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [1]) ); LUT6 #( @@ -40537,7 +42192,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5460 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5701 ) ); LUT6 #( .INIT ( 64'h0E0E0E0E0EAEFFFF )) @@ -40548,14 +42203,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5461 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5702 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5461 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5460 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5702 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5701 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [2]) ); LUT6 #( @@ -40567,7 +42222,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5462 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5703 ) ); LUT4 #( .INIT ( 16'h222A )) @@ -40576,17 +42231,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5463 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5704 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFDFFDDD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5463 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5704 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5462 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5703 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [4]) ); LUT5 #( @@ -40597,7 +42252,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5464 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5705 ) ); LUT5 #( .INIT ( 32'h04545555 )) @@ -40607,14 +42262,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5465 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5706 ) ); LUT3 #( .INIT ( 8'hFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5464 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5465 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5705 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5706 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [1]) ); LUT6 #( @@ -40626,7 +42281,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5466 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5707 ) ); LUT6 #( .INIT ( 64'hFFFFFFEE772AFFEE )) @@ -40637,14 +42292,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5467 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5708 ) ); LUT3 #( .INIT ( 8'hFB )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5467 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5708 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5466 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5707 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [4]) ); LUT6 #( @@ -40656,16 +42311,16 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1711 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5469 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5710 ) ); LUT5 #( .INIT ( 32'hFFFFA888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1178 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5469 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5710 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5473 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5714 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [1]) ); LUT3 #( @@ -40674,7 +42329,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]), - .O(N154) + .O(N156) ); LUT6 #( .INIT ( 64'h0000000000800000 )) @@ -40684,7 +42339,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]), - .I5(N154), + .I5(N156), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ) ); LUT3 #( @@ -40693,7 +42348,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]), - .O(N156) + .O(N158) ); LUT6 #( .INIT ( 64'h0000000000800000 )) @@ -40703,15 +42358,15 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]), - .I5(N156), + .I5(N158), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ) ); LUT6 #( .INIT ( 64'h5555440455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT113 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 ), - .I2(N158), + .I2(N160), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) , @@ -40725,8 +42380,8 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .I3(N166), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .I3(N168), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [0]), @@ -40742,7 +42397,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5479 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5720 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF5551 )) @@ -40752,7 +42407,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5479 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5720 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [3]) ); LUT6 #( @@ -40764,7 +42419,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5480 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5721 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF5551 )) @@ -40774,7 +42429,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5480 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5721 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [3]) ); LUT6 #( @@ -40786,7 +42441,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5481 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5722 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF5551 )) @@ -40796,7 +42451,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5481 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5722 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [3]) ); LUT6 #( @@ -40808,7 +42463,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5482 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5723 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF5551 )) @@ -40818,7 +42473,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5482 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5723 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [3]) ); LUT6 #( @@ -40830,7 +42485,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5483 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5724 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF5551 )) @@ -40840,7 +42495,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5483 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5724 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [3]) ); LUT5 #( @@ -40860,12 +42515,12 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5485 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5726 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT202 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5486 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5727 ) ); LUT5 #( .INIT ( 32'h00010000 )) @@ -40875,7 +42530,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [45]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [42]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5487 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5728 ) ); LUT5 #( .INIT ( 32'h40404000 )) @@ -40883,11 +42538,11 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5487 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5728 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5488 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5729 ) ); LUT4 #( .INIT ( 16'h0800 )) @@ -40896,113 +42551,113 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [42]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5489 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5730 ) ); LUT5 #( .INIT ( 32'h82202202 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5489 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5730 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [47]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [45]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [46]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5490 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5731 ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT10 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [0]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [0]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N168), + .I5(N170), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<18> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [1]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [1]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N170), + .I5(N172), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<19> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT13 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [2]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N172), + .I5(N174), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<20> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT14 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [3]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [3]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N174), + .I5(N176), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<21> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT18 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [7]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [7]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N176), + .I5(N178), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<25> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT20 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [1]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [1]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N178), + .I5(N180), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<27> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [2]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N180), + .I5(N182), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<28> ) ); @@ -41012,24 +42667,24 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [4]), - .O(N182) + .O(N184) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [4]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [1]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ), - .I5(N182), + .I5(N184), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<46> ) ); @@ -41039,24 +42694,24 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [5]), - .O(N184) + .O(N186) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT42 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [2]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ), - .I5(N184), + .I5(N186), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<47> ) ); @@ -41066,24 +42721,24 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [6]), - .O(N186) + .O(N188) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT43 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [3]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ), - .I5(N186), + .I5(N188), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<48> ) ); @@ -41093,24 +42748,24 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [7]), - .O(N188) + .O(N190) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT44 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [7]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [4]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ), - .I5(N188), + .I5(N190), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<49> ) ); @@ -41122,23 +42777,23 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [3]), - .O(N190) + .O(N192) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT49 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [3]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [1]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ), - .I5(N190), + .I5(N192), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<53> ) ); @@ -41150,23 +42805,23 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [4]), - .O(N192) + .O(N194) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT50 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [4]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [2]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ), - .I5(N192), + .I5(N194), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<54> ) ); @@ -41178,23 +42833,23 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [5]), - .O(N194) + .O(N196) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [3]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ), - .I5(N194), + .I5(N196), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<55> ) ); @@ -41206,23 +42861,23 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [6]), - .O(N196) + .O(N198) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT52 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [4]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ), - .I5(N196), + .I5(N198), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<56> ) ); @@ -41234,82 +42889,82 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11121 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5507 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5748 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5508 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5749 ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT9 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [7]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [7]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N198), + .I5(N200), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<17> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT15 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [4]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [4]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N200), + .I5(N202), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<22> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT16 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [5]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N202), + .I5(N204), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<23> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT26 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [6]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N204), + .I5(N206), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<32> ) ); LUT6 #( .INIT ( 64'h5540404055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT27 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [7]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [7]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ), - .I5(N206), + .I5(N208), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<33> ) ); @@ -41319,7 +42974,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), - .O(N214) + .O(N216) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) @@ -41329,7 +42984,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]), - .I5(N214), + .I5(N216), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ) ); LUT6 #( @@ -41541,7 +43196,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [6]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5528 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5769 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<38> ) @@ -41556,7 +43211,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [5]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5529 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5770 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<37> ) @@ -41705,7 +43360,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [13]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5539 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5780 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<29> ) @@ -41720,7 +43375,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [12]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5540 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5781 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<28> ) @@ -41870,7 +43525,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [1]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5550 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5791 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<1> ) @@ -41884,7 +43539,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [3]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5551 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5792 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<19> ) @@ -41924,7 +43579,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/out_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]), - .O(N216) + .O(N218) ); LUT6 #( .INIT ( 64'h8000000000000000 )) @@ -41934,144 +43589,46 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]), - .I5(N216), + .I5(N218), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ) ); LUT2 #( - .INIT ( 4'h7 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<4>1_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), - .O(N218) - ); - LUT6 #( - .INIT ( 64'h8888A88888882888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<4>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]), - .I4(N218), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFBFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .INIT ( 4'h8 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT4_SW0 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), .O(N220) ); LUT6 #( - .INIT ( 64'h44444444444444E4 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .INIT ( 64'h0010100010001000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT4 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), .I5(N220), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_4395 ) + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<3> ) ); LUT6 #( - .INIT ( 64'hFFFFFFFF5551FFFF )) + .INIT ( 64'h9BAA9BAADFAA9BAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5557 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3_5558 ) - ); - LUT3 #( - .INIT ( 8'h01 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4_5559 ) - ); - LUT6 #( - .INIT ( 64'hFA8ADA8AAA8A8A8A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4_5559 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3_5558 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4661 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5797 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In ) ); - LUT2 #( - .INIT ( 4'h7 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .O(N222) - ); - LUT6 #( - .INIT ( 64'hEFEEFFFFFFFFEFEE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11 ( - .I0(N222), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFDFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1_5561 ) - ); - LUT6 #( - .INIT ( 64'hFFA8FFAA88A8AAAA )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2_5562 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In ) - ); - LUT2 #( - .INIT ( 4'h7 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .O(N224) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFF11111115 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv ( - .I0(N224), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ) - ); LUT3 #( .INIT ( 8'h80 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), - .O(N226) + .O(N224) ); LUT6 #( .INIT ( 64'hAA000000FF3CFF3C )) @@ -42079,32 +43636,32 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(N226), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(N224), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4666 ) ); LUT6 #( .INIT ( 64'hFF57AA02AA02AA02 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5565 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4726 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5799 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5566 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5800 ) ); LUT6 #( .INIT ( 64'hC4C44444F4C4F444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4726 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In11 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5567 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5801 ) ); LUT5 #( .INIT ( 32'h7FFF0000 )) @@ -42113,59 +43670,59 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5567 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5568 ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5801 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5802 ) ); LUT6 #( .INIT ( 64'h44F444F444F400F0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In5 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5566 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5568 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5800 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5802 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In ) ); LUT2 #( .INIT ( 4'hD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .O(N228) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .O(N226) ); LUT6 #( .INIT ( 64'h222A22EE222A222A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ), - .I3(N228), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4666 ), + .I3(N226), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT17 ) , - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4465 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4726 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4706 ) ); LUT6 #( .INIT ( 64'hFF08080808080808 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5570 ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4666 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5804 ) ); LUT5 #( .INIT ( 32'h44F400F0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5570 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5804 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In ) ); LUT6 #( @@ -42188,7 +43745,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [4]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5572 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5806 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) @@ -42197,29 +43754,29 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [15]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [12]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [13]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5572 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5806 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ) ); LUT2 #( .INIT ( 4'h8 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mmux_err_block_count_inc_in_GND_28_o_MUX_424_o1_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .O(N230) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mmux_err_block_count_inc_in_GND_28_o_MUX_434_o1_SW0 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .O(N228) ); LUT6 #( .INIT ( 64'h08FF080008000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mmux_err_block_count_inc_in_GND_28_o_MUX_424_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mmux_err_block_count_inc_in_GND_28_o_MUX_434_o1 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ), - .I3(N230), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_424_o ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4912 ), + .I3(N228), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_434_o ) ); LUT3 #( .INIT ( 8'hFE )) @@ -42227,7 +43784,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]), - .O(N234) + .O(N232) ); LUT6 #( .INIT ( 64'h0000000000000002 )) @@ -42237,85 +43794,85 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]), - .I5(N234), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4665 ) + .I5(N232), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4906 ) ); LUT6 #( .INIT ( 64'hFEFEFEFAFCFCFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT421 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_4982 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_5223 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [57]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5575 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5809 ) ); LUT6 #( .INIT ( 64'hFEFEFEFAFCFCFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT411 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_4981 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_5222 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [56]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT41 ) ); LUT6 #( .INIT ( 64'hFEFEFEFAFCFCFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT401 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_4980 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_5221 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [55]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT40 ) ); LUT6 #( .INIT ( 64'hFEFEFEFAFCFCFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT391 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_4979 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_5220 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [54]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT39 ) ); LUT6 #( .INIT ( 64'hFEFEFEFAFCFCFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT381 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_4978 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_5219 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [53]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT38 ) ); LUT6 #( .INIT ( 64'hFEFEFEFAFCFCFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_4976 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_5217 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [50]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT35 ) ); @@ -42326,21 +43883,21 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [51]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_4977 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_5218 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT36 ) ); LUT4 #( .INIT ( 16'h5444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT362 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT36 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [43]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<41> ) ); @@ -42354,7 +43911,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [46]), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ), - .O(N238) + .O(N236) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) @@ -42366,7 +43923,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [45]), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ), - .O(N240) + .O(N238) ); LUT6 #( .INIT ( 64'h0EEEEEEEEEEEEEEE )) @@ -42378,21 +43935,21 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5584 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5818 ) ); LUT5 #( .INIT ( 32'hFEFAFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_4975 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_5216 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [49]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5584 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5818 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5585 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5819 ) ); LUT6 #( .INIT ( 64'hFFFFFFFEFFFFFFFC )) @@ -42405,7 +43962,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ), - .O(N246) + .O(N244) ); LUT3 #( .INIT ( 8'hFE )) @@ -42426,12 +43983,12 @@ loopback_ctrl .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT32 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5823 ) ); LUT6 #( .INIT ( 64'hFEEEFCCCFAAAF000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_4955 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_5196 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [26]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), @@ -42444,7 +44001,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFEEEFCCCFAAAF000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_4961 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_5202 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), @@ -42457,7 +44014,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFEEEFCCCFAAAF000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_4960 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_5201 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), @@ -42470,7 +44027,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFEEEFCCCFAAAF000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_4959 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_5200 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), @@ -42483,7 +44040,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFEEEFCCCFAAAF000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_4958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_5199 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), @@ -42496,7 +44053,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFEEEFCCCFAAAF000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_4957 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_5198 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), @@ -42511,18 +44068,18 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT60_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [65]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , - .O(N250) + .O(N248) ); LUT6 #( .INIT ( 64'h0302333303003333 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT60 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_4996 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_5237 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), - .I4(N250), + .I4(N248), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<63> ) @@ -42532,18 +44089,18 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT59_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [64]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , - .O(N252) + .O(N250) ); LUT6 #( .INIT ( 64'h0302333303003333 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT59 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_4995 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_5236 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), - .I4(N252), + .I4(N250), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<62> ) @@ -42553,18 +44110,18 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT58_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [63]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , - .O(N254) + .O(N252) ); LUT6 #( .INIT ( 64'h0302333303003333 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT58 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_4994 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_5235 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), - .I4(N254), + .I4(N252), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<61> ) @@ -42574,18 +44131,18 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT57_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [62]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , - .O(N256) + .O(N254) ); LUT6 #( .INIT ( 64'h0302333303003333 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT57 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_4993 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_5234 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), - .I4(N256), + .I4(N254), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<60> ) @@ -42595,18 +44152,18 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT55_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [61]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , - .O(N258) + .O(N256) ); LUT6 #( .INIT ( 64'h0302333303003333 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT55 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_4992 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_5233 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), - .I4(N258), + .I4(N256), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<59> ) @@ -42614,7 +44171,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0F0E0F0A0F0C0F00 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT511 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_4989 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_5230 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [65]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), @@ -42627,9 +44184,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT512 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [57]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT51 ), @@ -42638,7 +44195,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0F0E0F0A0F0C0F00 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT501 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_4988 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_5229 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [64]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), @@ -42651,9 +44208,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT502 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [56]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT50 ), @@ -42662,7 +44219,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0F0E0F0A0F0C0F00 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT491 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_4987 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_5228 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [63]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), @@ -42675,9 +44232,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT492 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [55]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT49 ), @@ -42686,7 +44243,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0F0E0F0A0F0C0F00 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT481 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_4986 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_5227 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [62]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), @@ -42699,9 +44256,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT482 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [54]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT48 ), @@ -42710,7 +44267,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0F0E0F0A0F0C0F00 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT471 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_4985 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_5226 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [61]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), @@ -42723,9 +44280,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT472 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [53]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT47 ), @@ -42734,7 +44291,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0F0E0F0A0F0C0F00 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT431 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_4983 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_5224 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [58]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), @@ -42747,9 +44304,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT432 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [50]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT43 ), @@ -42758,24 +44315,24 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT6 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ), - .I5(N262), + .I5(N260), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<5> ) ); LUT6 #( .INIT ( 64'h5555555455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ), - .I5(N264), + .I5(N262), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<2> ) ); LUT3 #( @@ -42784,18 +44341,18 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), - .O(N268) + .O(N266) ); LUT6 #( .INIT ( 64'h5555555455555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT7 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ), - .I5(N268), + .I5(N266), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<6> ) ); LUT5 #( @@ -42806,7 +44363,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]), - .O(N272) + .O(N270) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42816,7 +44373,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ), - .I5(N272), + .I5(N270), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<5> ) ); LUT5 #( @@ -42827,7 +44384,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), - .O(N276) + .O(N274) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42837,7 +44394,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ), - .I5(N276), + .I5(N274), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<5> ) ); LUT6 #( @@ -42848,7 +44405,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ), - .I5(N278), + .I5(N276), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]) ); LUT5 #( @@ -42859,7 +44416,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]), - .O(N280) + .O(N278) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42869,7 +44426,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ), - .I5(N280), + .I5(N278), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<5> ) ); LUT6 #( @@ -42880,7 +44437,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ), - .I5(N282), + .I5(N280), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]) ); LUT5 #( @@ -42891,7 +44448,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]), - .O(N284) + .O(N282) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42901,7 +44458,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ), - .I5(N284), + .I5(N282), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<5> ) ); LUT6 #( @@ -42912,7 +44469,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ), - .I5(N286), + .I5(N284), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]) ); LUT5 #( @@ -42923,7 +44480,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]), - .O(N290) + .O(N288) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42933,7 +44490,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ), - .I5(N290), + .I5(N288), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<5> ) ); LUT6 #( @@ -42944,7 +44501,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ), - .I5(N292), + .I5(N290), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]) ); LUT5 #( @@ -42955,7 +44512,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]), - .O(N294) + .O(N292) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42965,7 +44522,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ), - .I5(N294), + .I5(N292), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<5> ) ); LUT6 #( @@ -42976,7 +44533,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ), - .I5(N296), + .I5(N294), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]) ); LUT5 #( @@ -42987,7 +44544,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]), - .O(N298) + .O(N296) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) @@ -42997,7 +44554,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ), - .I5(N298), + .I5(N296), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<5> ) ); LUT6 #( @@ -43008,7 +44565,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ), - .I5(N300), + .I5(N298), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]) ); LUT3 #( @@ -43017,7 +44574,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), - .O(N302) + .O(N300) ); LUT6 #( .INIT ( 64'h0000000000000200 )) @@ -43027,7 +44584,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]), - .I5(N302), + .I5(N300), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ) ); LUT3 #( @@ -43036,7 +44593,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), - .O(N304) + .O(N302) ); LUT6 #( .INIT ( 64'h0000000000800000 )) @@ -43046,7 +44603,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]), - .I5(N304), + .I5(N302), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ) ); LUT3 #( @@ -43055,7 +44612,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]), - .O(N306) + .O(N304) ); LUT6 #( .INIT ( 64'h0000000001000000 )) @@ -43065,19 +44622,19 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]), - .I5(N306), + .I5(N304), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFBFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .O(N308) + .O(N306) ); LUT6 #( .INIT ( 64'h0000000000000008 )) @@ -43087,30 +44644,30 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), - .I5(N306), + .I5(N304), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ) ); LUT6 #( .INIT ( 64'h0000000000008001 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), - .I5(N320), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ) + .I5(N318), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o2_4950 ) ); LUT6 #( .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT624 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT621 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5634 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5868 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<7> ) @@ -43124,14 +44681,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]), - .O(N324) + .O(N322) ); LUT4 #( .INIT ( 16'hFFBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]), - .I2(N324), + .I2(N322), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<3> ) ); @@ -43144,14 +44701,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]), - .O(N326) + .O(N324) ); LUT4 #( .INIT ( 16'hFFBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]), - .I2(N326), + .I2(N324), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<3> ) ); @@ -43164,14 +44721,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]), - .O(N328) + .O(N326) ); LUT4 #( .INIT ( 16'hFFBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]), - .I2(N328), + .I2(N326), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<3> ) ); @@ -43184,7 +44741,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), - .O(N330) + .O(N328) ); LUT6 #( .INIT ( 64'hFAF7FFF7BF5FBFFF )) @@ -43195,14 +44752,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]), - .O(N332) + .O(N330) ); LUT4 #( .INIT ( 16'hFFBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), - .I2(N332), + .I2(N330), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<3> ) ); @@ -43224,7 +44781,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5641 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5875 ) ); LUT5 #( .INIT ( 32'hFFFFFFFD )) @@ -43232,7 +44789,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT4 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5641 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5875 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<3> ) ); @@ -43245,14 +44802,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), - .O(N334) + .O(N332) ); LUT4 #( .INIT ( 16'hFFBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]), - .I2(N334), + .I2(N332), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<3> ) ); @@ -43265,14 +44822,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]), - .O(N336) + .O(N334) ); LUT4 #( .INIT ( 16'hFFBF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]), - .I2(N336), + .I2(N334), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<3> ) ); @@ -43285,56 +44842,56 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5878 ) ); LUT6 #( .INIT ( 64'h4440404000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o5 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2_5646 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o2_5880 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3_5647 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o3_5881 ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4_5648 ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o4_5882 ) , - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o31 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o5_5883 ) ); LUT6 #( .INIT ( 64'h8000000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o6 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6_5650 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o6_5884 ) ); LUT6 #( .INIT ( 64'hFFA8FFA0FF00FF00 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7_5651 ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o10 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o7_5885 ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9_5653 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o9_5887 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8_5652 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o8_5886 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6_5650 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o6_5884 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o10_5888 ) ); LUT6 #( .INIT ( 64'h2323232323232320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT56 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), - .I4(N338), + .I4(N336), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<5> ) @@ -43343,19 +44900,19 @@ loopback_ctrl .INIT ( 8'hEC )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT52_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [58]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , - .O(N344) + .O(N342) ); LUT6 #( .INIT ( 64'hFF32FF30FF33FF33 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT52 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_4990 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_5231 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), - .I3(N344), + .I3(N342), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), @@ -43365,11 +44922,11 @@ loopback_ctrl .INIT ( 64'h2323030322230003 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT46 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [52]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N346), + .I3(N344), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ), @@ -43379,9 +44936,9 @@ loopback_ctrl .INIT ( 16'h3320 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT442 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [51]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT44 ), @@ -43390,7 +44947,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'hFEFAFCF0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT171 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_4962 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_5203 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ), .I3 @@ -43403,10 +44960,10 @@ loopback_ctrl .INIT ( 64'hEFCFEECCEFCFEFCF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT172 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [26]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4915 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT17 ), @@ -43415,7 +44972,7 @@ loopback_ctrl ); LUT6 #( .INIT ( 64'h0000000000001000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), @@ -43423,19 +44980,19 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o2_5898 ) ); LUT5 #( .INIT ( 32'h00000001 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o3_5899 ) ); LUT4 #( @@ -43444,41 +45001,41 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .O(N362) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .O(N360) ); LUT6 #( - .INIT ( 64'h44444444444444E4 )) + .INIT ( 64'h5555555D00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .I5(N362), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5071 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .I4(N360), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5312 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .O(N364) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .O(N362) ); LUT6 #( .INIT ( 64'h00FF80FF00008000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), - .I4(N364), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5070 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), + .I4(N362), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5311 ) ); LUT6 #( .INIT ( 64'hA2A2A2A2A2FFA2A2 )) @@ -43486,30 +45043,30 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5668 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5902 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFAAA28880 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5668 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5669 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5902 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5903 ) ); LUT6 #( .INIT ( 64'h00200020FFFF0020 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In3 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5669 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5903 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In ) ); @@ -43517,9 +45074,9 @@ loopback_ctrl .INIT ( 64'h1455145514553655 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ) @@ -43535,7 +45092,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'h08080888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), @@ -43546,21 +45103,21 @@ loopback_ctrl .INIT ( 64'h1414FFFF14144404 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1632 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT163 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5672 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5906 ) ); LUT4 #( .INIT ( 16'h0008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1633 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5672 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5906 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [8]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<8> ) ); @@ -43568,467 +45125,467 @@ loopback_ctrl .INIT ( 64'hFFFFFFFFFEFEFEFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]), - .I1(N366), + .I1(N364), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<0> ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5674 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5908 ), .R(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0 ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5675 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5909 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6 ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5676 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5910 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5677 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5911 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3636 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5678 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5912 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3637 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5679 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5913 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5680 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5914 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3656 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5681 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5915 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3657 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5682 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5916 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5683 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5917 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3676 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5684 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5918 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3677 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2 ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5685 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5919 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5686 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5920 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [7]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5687 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5921 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [6]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5688 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5922 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [5]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5689 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5923 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [4]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5690 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5924 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [3]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5691 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5925 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [2]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5692 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5926 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [1]) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5693 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5927 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [0]) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<14>_rt_5928 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<13>_rt_5929 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<12>_rt_5930 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<11>_rt_5931 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<10>_rt_5932 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<9>_rt_5933 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<8>_rt_5934 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<7>_rt_5935 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<6>_rt_5936 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<5>_rt_5937 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<4>_rt_5938 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<3>_rt_5939 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<2>_rt_5940 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_cy<1>_rt_5941 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<14>_rt_5942 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<13>_rt_5943 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<12>_rt_5944 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<11>_rt_5945 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<10>_rt_5946 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<9>_rt_5947 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<8>_rt_5948 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<7>_rt_5949 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<6>_rt_5950 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<5>_rt_5951 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<4>_rt_5952 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<3>_rt_5953 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<2>_rt_5954 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_cy<1>_rt_5955 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<14>_rt_5956 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<13>_rt_5957 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<12>_rt_5958 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<11>_rt_5959 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<10>_rt_5960 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<9>_rt_5961 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<8>_rt_5962 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<7>_rt_5963 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<6>_rt_5964 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<5>_rt_5965 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<4>_rt_5966 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<3>_rt_5967 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<2>_rt_5968 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_cy<1>_rt_5969 ) ); LUT1 #( @@ -44036,165 +45593,165 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5970 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5971 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5972 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5973 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5974 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5975 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5976 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5977 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5978 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5979 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5980 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5981 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5982 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5983 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5984 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5985 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5986 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5987 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5988 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5989 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5990 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<15>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt_5757 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_xor<15>_rt_5991 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<15>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt_5758 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_xor<15>_rt_5992 ) ); LUT1 #( .INIT ( 2'h2 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<15>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt_5759 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_xor<15>_rt_5993 ) ); LUT1 #( @@ -44202,44 +45759,44 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5760 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5994 ) ); LUT1 #( .INIT ( 2'h2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5761 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5995 ) ); FDR #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_586 ), .R (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1959 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1995 ) ); FDR #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5762 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5996 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1988 ) ); FDR #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5763 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5997 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1989 ) ); FDR #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5764 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5998 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ), .Q (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ) @@ -44248,223 +45805,229 @@ loopback_ctrl .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5765 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5999 ), .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ) ); FDR #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_5766 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_6000 ), .R (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_5767 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_6001 ), .S(txreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ) + ); + FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3 ( + .C(rxusrclk2), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3_rstpot_6002 ), + .R(rxreset322), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]) ); FDS \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_5768 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_6003 ), .S(reset), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ) ); FDR #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_5769 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_6004 ), .R(rxreset322), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ) + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_5770 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_6005 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_189_o ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ) ); FDR \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_5771 ), - .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_6006 ), + .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_5772 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_261 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_6007 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_294 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_5773 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_6008 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_810_o ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_5774 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_6009 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1375 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_5775 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_6010 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_5776 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1676 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_6011 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1711 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable ( .C(txusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_5777 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_6012 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2 ( .C(clk156), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_5778 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_6013 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1 ( .C(clk156), .D -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_5779 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_6014 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_5780 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_6015 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3624 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_5781 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_6016 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3628 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_5782 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_6017 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3632 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_5783 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_6018 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3644 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_5784 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_6019 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3648 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_5785 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_6020 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3652 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_5786 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_6021 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3664 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_5787 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_6022 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3668 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_5788 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_6023 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3672 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_5789 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_6024 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4 [0]) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_5790 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_6025 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0 [0]) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_5791 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_6026 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_5792 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_6027 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3639 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_5793 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_6028 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3659 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_5794 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_6029 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3679 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch ( .C(rxusrclk2), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_5795 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_6030 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4912 ) ); FD \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_5796 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_6031 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1398 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_5797 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_6032 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1963 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_5798 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_6033 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1962 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_5799 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_6034 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1996 ) ); FD #( .INIT ( 1'b0 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0 ( .C(clk156), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_5800 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ) + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_6035 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1993 ) ); LUT6 #( .INIT ( 64'h0660042002400000 )) @@ -44475,7 +46038,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 ), - .O(N370) + .O(N368) ); LUT5 #( .INIT ( 32'hFFFFFFFE )) @@ -44484,7 +46047,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ), - .I4(N370), + .I4(N368), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]) ); LUT6 #( @@ -44496,7 +46059,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 ), - .O(N278) + .O(N276) ); LUT6 #( .INIT ( 64'h1009000110080000 )) @@ -44507,7 +46070,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 ), - .O(N282) + .O(N280) ); LUT6 #( .INIT ( 64'h0421000104200000 )) @@ -44518,7 +46081,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 ), - .O(N286) + .O(N284) ); LUT6 #( .INIT ( 64'h1009000110080000 )) @@ -44529,7 +46092,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ), - .O(N292) + .O(N290) ); LUT6 #( .INIT ( 64'h0241024000010000 )) @@ -44540,7 +46103,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 ), - .O(N296) + .O(N294) ); LUT6 #( .INIT ( 64'h0421042000010000 )) @@ -44551,7 +46114,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 ), - .O(N300) + .O(N298) ); LUT6 #( .INIT ( 64'h9060090609069060 )) @@ -44562,7 +46125,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]), - .O(N372) + .O(N370) ); LUT6 #( .INIT ( 64'h0010000000000000 )) @@ -44572,7 +46135,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), - .I5(N372), + .I5(N370), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ) ); LUT6 #( @@ -44584,7 +46147,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]), - .O(N374) + .O(N372) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -44592,7 +46155,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), - .I3(N374), + .I3(N372), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ) @@ -44606,7 +46169,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), - .O(N376) + .O(N374) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -44616,7 +46179,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]), - .I5(N376), + .I5(N374), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ) ); LUT5 #( @@ -44624,57 +46187,57 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT3_SW0_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ), - .O(N381) + .O(N379) ); LUT3 #( .INIT ( 8'hBE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT3_SW0_SW1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), - .O(N382) + .O(N380) ); LUT5 #( .INIT ( 32'hFFFFFDFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o211_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o211_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ), - .O(N384) + .O(N382) ); LUT6 #( .INIT ( 64'h4000000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3 ( - .I0(N384), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o3 ( + .I0(N382), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o2_5898 ) , .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o3_5899 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o31 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o1_4941 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o ) ); LUT6 #( .INIT ( 64'h0096000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4_5648 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o4_5882 ) ); LUT5 #( .INIT ( 32'h00000069 )) @@ -44899,15 +46462,15 @@ loopback_ctrl LUT6 #( .INIT ( 64'hFFFFFFFF55554044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) , - .I3(N160), + .I3(N162), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11322 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5686 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5920 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF1110 )) @@ -44916,11 +46479,11 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5331 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5333 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5572 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5574 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT14 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5689 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5923 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFAAA22A22 )) @@ -44930,33 +46493,33 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5508 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5749 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5690 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5924 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF11105554 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5412 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5653 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5 ), - .I4(N390), + .I4(N388), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5692 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5926 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF44405555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT17 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT175 ), - .I4(N394), + .I4(N392), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5688 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5922 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFAEEE0444 )) @@ -44997,7 +46560,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 ) ); @@ -45014,7 +46577,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 ) @@ -45022,7 +46585,7 @@ loopback_ctrl .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5323 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5564 ) ); LUT6 #( .INIT ( 64'h2000000000000000 )) @@ -45046,13 +46609,13 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 ) ); @@ -45069,19 +46632,19 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 ) , - .O(N160) + .O(N162) ); LUT6 #( .INIT ( 64'h1555555555555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ), @@ -45108,7 +46671,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5324 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5565 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) @@ -45118,8 +46681,8 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), - .O(N400) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), + .O(N398) ); LUT6 #( .INIT ( 64'hFFFFFFFEFFFFFFFF )) @@ -45129,7 +46692,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), - .I4(N400), + .I4(N398), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<4> ) ); @@ -45140,8 +46703,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), - .O(N402) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), + .O(N400) ); LUT6 #( .INIT ( 64'hFFFFFFFEFFFFFFFF )) @@ -45150,7 +46713,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ), - .I4(N402), + .I4(N400), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<0> ) ); @@ -45158,11 +46721,11 @@ loopback_ctrl .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT23 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), - .I4(N404), + .I4(N402), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<2> ) ); @@ -45170,14 +46733,14 @@ loopback_ctrl .INIT ( 64'hDFFFFFFFFFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11113 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5577 ) ); LUT4 #( .INIT ( 16'hFF7F )) @@ -45186,19 +46749,19 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49]), - .O(N406) + .O(N404) ); LUT6 #( .INIT ( 64'hDFFFFFFFFFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ), - .I1(N406), + .I1(N404), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) ); LUT6 #( @@ -45210,7 +46773,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ), - .O(N408) + .O(N406) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) @@ -45220,7 +46783,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ), - .I5(N408), + .I5(N406), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]) ); LUT4 #( @@ -45252,7 +46815,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]), - .O(N410) + .O(N408) ); LUT6 #( .INIT ( 64'h0000000000000080 )) @@ -45262,7 +46825,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), - .I5(N410), + .I5(N408), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ) ); LUT5 #( @@ -45283,37 +46846,37 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50]), - .O(N414) + .O(N412) ); LUT6 #( .INIT ( 64'h0080008000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14115 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ), - .I1(N414), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5658 ), + .I1(N412), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5490 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5488 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5731 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5729 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ) ); LUT6 #( .INIT ( 64'h0400000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o211 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o211 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .I2(N416), + .I2(N414), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o21 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/out8 ( - .I0(N248), - .I1(N418), + .I0(N246), + .I1(N416), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ), @@ -45330,7 +46893,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), - .O(N420) + .O(N418) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45339,7 +46902,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]), - .I4(N420), + .I4(N418), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ) ); @@ -45352,7 +46915,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]), - .O(N422) + .O(N420) ); LUT6 #( .INIT ( 64'h0000000000000200 )) @@ -45362,7 +46925,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]), - .I5(N422), + .I5(N420), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o ) ); LUT6 #( @@ -45374,7 +46937,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), - .O(N424) + .O(N422) ); LUT6 #( .INIT ( 64'h0004000000000000 )) @@ -45384,7 +46947,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]), - .I5(N424), + .I5(N422), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o ) ); LUT6 #( @@ -45396,7 +46959,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]), - .O(N426) + .O(N424) ); LUT6 #( .INIT ( 64'h0000000000000008 )) @@ -45406,7 +46969,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]), - .I5(N426), + .I5(N424), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ) ); LUT6 #( @@ -45418,7 +46981,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]), - .O(N428) + .O(N426) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45428,7 +46991,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]), - .I5(N428), + .I5(N426), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ) ); LUT6 #( @@ -45440,7 +47003,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]), - .O(N430) + .O(N428) ); LUT6 #( .INIT ( 64'h0000000010000000 )) @@ -45450,7 +47013,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), - .I5(N430), + .I5(N428), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ) ); LUT6 #( @@ -45462,7 +47025,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]), - .O(N432) + .O(N430) ); LUT6 #( .INIT ( 64'h0000000000020000 )) @@ -45472,7 +47035,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), - .I5(N432), + .I5(N430), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o ) ); LUT6 #( @@ -45484,7 +47047,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]), - .O(N434) + .O(N432) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45494,7 +47057,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]), - .I5(N434), + .I5(N432), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o ) ); LUT6 #( @@ -45506,7 +47069,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]), - .O(N436) + .O(N434) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -45514,7 +47077,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]), - .I3(N436), + .I3(N434), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ) @@ -45528,7 +47091,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]), - .O(N438) + .O(N436) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45538,7 +47101,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]), - .I5(N438), + .I5(N436), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ) ); LUT6 #( @@ -45550,7 +47113,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]), - .O(N440) + .O(N438) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45559,7 +47122,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]), - .I4(N440), + .I4(N438), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ) ); @@ -45572,7 +47135,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12]), - .O(N442) + .O(N440) ); LUT6 #( .INIT ( 64'h0000000000020000 )) @@ -45582,7 +47145,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), - .I5(N442), + .I5(N440), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o ) ); LUT6 #( @@ -45594,7 +47157,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]), - .O(N444) + .O(N442) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45604,7 +47167,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]), - .I5(N444), + .I5(N442), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o ) ); LUT6 #( @@ -45616,7 +47179,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]), - .O(N446) + .O(N444) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -45624,7 +47187,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]), - .I3(N446), + .I3(N444), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ) @@ -45638,7 +47201,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]), - .O(N448) + .O(N446) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45648,7 +47211,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]), - .I5(N448), + .I5(N446), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ) ); LUT6 #( @@ -45660,7 +47223,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]), - .O(N450) + .O(N448) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45669,7 +47232,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]), - .I4(N450), + .I4(N448), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ) ); @@ -45682,7 +47245,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]), - .O(N452) + .O(N450) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45691,7 +47254,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]), - .I4(N452), + .I4(N450), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ) ); @@ -45704,7 +47267,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]), - .O(N454) + .O(N452) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -45712,7 +47275,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), - .I3(N454), + .I3(N452), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o ) @@ -45726,7 +47289,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]), - .O(N456) + .O(N454) ); LUT6 #( .INIT ( 64'h0000000002000000 )) @@ -45736,7 +47299,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), - .I5(N456), + .I5(N454), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ) ); LUT6 #( @@ -45748,7 +47311,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]), - .O(N458) + .O(N456) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45758,7 +47321,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]), - .I5(N458), + .I5(N456), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ) ); LUT6 #( @@ -45770,7 +47333,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), - .O(N460) + .O(N458) ); LUT6 #( .INIT ( 64'h0000000010000000 )) @@ -45780,7 +47343,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), - .I5(N460), + .I5(N458), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ) ); LUT6 #( @@ -45792,7 +47355,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), - .O(N462) + .O(N460) ); LUT6 #( .INIT ( 64'h0000000000040000 )) @@ -45802,7 +47365,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), - .I5(N462), + .I5(N460), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ) ); LUT6 #( @@ -45814,7 +47377,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]), - .O(N464) + .O(N462) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45823,7 +47386,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), - .I4(N464), + .I4(N462), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ) ); @@ -45836,7 +47399,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), - .O(N466) + .O(N464) ); LUT6 #( .INIT ( 64'h0000000002000000 )) @@ -45846,7 +47409,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), - .I5(N466), + .I5(N464), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ) ); LUT6 #( @@ -45858,7 +47421,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), - .O(N468) + .O(N466) ); LUT6 #( .INIT ( 64'h0000000000000020 )) @@ -45868,7 +47431,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]), - .I5(N468), + .I5(N466), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ) ); LUT6 #( @@ -45880,7 +47443,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]), - .O(N470) + .O(N468) ); LUT6 #( .INIT ( 64'h0000000000400000 )) @@ -45890,7 +47453,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), - .I5(N470), + .I5(N468), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ) ); LUT6 #( @@ -45902,7 +47465,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]), - .O(N472) + .O(N470) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45912,7 +47475,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), - .I5(N472), + .I5(N470), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o ) ); LUT6 #( @@ -45924,7 +47487,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]), - .O(N474) + .O(N472) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -45932,7 +47495,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), - .I3(N474), + .I3(N472), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o ) @@ -45946,7 +47509,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]), - .O(N476) + .O(N474) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -45956,7 +47519,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]), - .I5(N476), + .I5(N474), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ) ); LUT6 #( @@ -45968,7 +47531,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]), - .O(N478) + .O(N476) ); LUT6 #( .INIT ( 64'h0001000000000000 )) @@ -45976,7 +47539,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]), - .I3(N478), + .I3(N476), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ) @@ -45990,7 +47553,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), - .O(N480) + .O(N478) ); LUT6 #( .INIT ( 64'h0000000000000001 )) @@ -46000,7 +47563,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), - .I5(N480), + .I5(N478), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ) ); LUT6 #( @@ -46012,7 +47575,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]), - .O(N482) + .O(N480) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -46021,7 +47584,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]), - .I4(N482), + .I4(N480), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ) ); @@ -46034,7 +47597,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]), - .O(N484) + .O(N482) ); LUT6 #( .INIT ( 64'h0000000000000001 )) @@ -46044,7 +47607,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), - .I5(N484), + .I5(N482), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o ) ); LUT6 #( @@ -46056,7 +47619,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]), - .O(N486) + .O(N484) ); LUT6 #( .INIT ( 64'h0000000010000000 )) @@ -46066,17 +47629,17 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), - .I5(N486), + .I5(N484), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ) ); LUT6 #( .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT30 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N488), - .I4(N238), + .I3(N486), + .I4(N236), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<36> ) ); @@ -46084,10 +47647,10 @@ loopback_ctrl .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT29 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N490), - .I4(N240), + .I3(N488), + .I4(N238), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<35> ) ); @@ -46095,11 +47658,11 @@ loopback_ctrl .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT333 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N492), + .I3(N490), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5585 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5819 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<39> ) @@ -46112,16 +47675,16 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]), - .O(N494) + .O(N492) ); LUT6 #( .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT28 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N494), - .I4(N246), + .I3(N492), + .I4(N244), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<34> ) ); @@ -46132,16 +47695,16 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), - .O(N496) + .O(N494) ); LUT6 #( .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT34 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N496), - .I4(N312), + .I3(N494), + .I4(N310), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<3> ) ); @@ -46149,18 +47712,18 @@ loopback_ctrl .INIT ( 64'hEFEFEFECEFEFEFEF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT45 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), - .I3(N496), - .I4(N314), + .I3(N494), + .I4(N312), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<4> ) ); LUT6 #( .INIT ( 64'hCAAAAAAAAAAAAAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314 ( - .I0(N500), - .I1(N501), + .I0(N498), + .I1(N499), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]), @@ -46176,24 +47739,24 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ), - .O(N503) + .O(N501) ); LUT6 #( .INIT ( 64'h222222202222222A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1_5645 ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o2 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o1_5879 ) , - .I1(N504), + .I1(N502), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ), - .I4(N370), - .I5(N503), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2_5646 ) + .I4(N368), + .I5(N501), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o2_5880 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF55551110 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5576 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) @@ -46205,23 +47768,23 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ), - .O(N507) + .O(N505) ); LUT6 #( .INIT ( 64'h2222222200022022 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11117 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114 ), - .I3(N506), - .I4(N507), + .I3(N504), + .I4(N505), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1111 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [2]) ); LUT6 #( .INIT ( 64'h555411105557DDDF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11115 ( - .I0(N514), + .I0(N512), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ), @@ -46229,13 +47792,13 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 ) , - .I5(N513), + .I5(N511), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114 ) ); LUT6 #( .INIT ( 64'h070007778F888FFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT113_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ), @@ -46246,7 +47809,7 @@ loopback_ctrl .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 ) , - .O(N158) + .O(N160) ); LUT6 #( .INIT ( 64'h0000000000800000 )) @@ -46262,7 +47825,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT182 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [27]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -46275,7 +47838,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEE0EAA0ACC0C0000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT181 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_4963 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_5204 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), @@ -46436,8 +47999,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0> ) @@ -46461,8 +48024,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_578 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_577 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1> ) @@ -46499,159 +48062,159 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ), - .O(N516) + .O(N514) ); LUT6 #( .INIT ( 64'h0240024002400040 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), - .I4(N282), - .I5(N516), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3_5647 ) + .I4(N280), + .I5(N514), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o3_5881 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF69FF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o1_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o1_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .O(N518) + .O(N516) ); LUT6 #( .INIT ( 64'h4000000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o1 ( - .I0(N518), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o1 ( + .I0(N516), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o2_4950 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o ) ); LUT5 #( .INIT ( 32'hFFFF96FF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_SW1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_SW1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), - .I4(N308), - .O(N520) + .I4(N306), + .O(N518) ); LUT6 #( .INIT ( 64'h2000000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ), - .I1(N520), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o ), + .I1(N518), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_5044 ) ); LUT6 #( .INIT ( 64'h777F77FFFFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o11_5889 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o10_5888 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o21 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ), - .O(N522) + .O(N520) ); LUT6 #( .INIT ( 64'h0406040404060606 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), - .I3(N523), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), + .I3(N521), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o5_5883 ) , - .I5(N522), + .I5(N520), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<0> ) ); LUT6 #( .INIT ( 64'hFF7FFF7FFF7FAA2A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4912 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ), - .I3(N525), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4665 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_5795 ) + .I3(N523), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4906 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_6030 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFEAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT2_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ), - .I1(N527), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o ), + .I1(N525), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o31 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o1_4941 ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ), - .O(N388) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_5044 ), + .O(N386) ); LUT6 #( .INIT ( 64'h5555551D5547550F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT3 ( - .I0(N382), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 ) + .I0(N380), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o5_5883 ) , - .I2(N381), + .I2(N379), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o ), - .I4(N530), - .I5(N529), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o ), + .I4(N528), + .I5(N527), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<2> ) ); LUT6 #( .INIT ( 64'hFAFAFAFAEAEEEAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]), - .I2(N533), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 ) + .I2(N531), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o5_5883 ) , - .I4(N532), - .I5(N388), + .I4(N530), + .I5(N386), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<1> ) ); LUT5 #( .INIT ( 32'hFF69FFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11_SW0_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o11_SW0_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), - .O(N535) + .O(N533) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFA2FFAA )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o11_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .I3(N535), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ), - .O(N500) + .I3(N533), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5878 ), + .O(N498) ); LUT6 #( .INIT ( 64'h96FFFF96FF9696FF )) @@ -46662,7 +48225,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]), - .O(N537) + .O(N535) ); LUT6 #( .INIT ( 64'h0000000000000800 )) @@ -46672,7 +48235,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]), - .I5(N537), + .I5(N535), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ) ); LUT6 #( @@ -46684,7 +48247,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]), - .O(N539) + .O(N537) ); LUT6 #( .INIT ( 64'h0000000000000400 )) @@ -46694,77 +48257,77 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]), - .I5(N539), + .I5(N537), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ) ); LUT4 #( .INIT ( 16'h7DD7 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW4_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW4_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]), - .O(N541) + .O(N539) ); LUT6 #( .INIT ( 64'h1110110000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW4 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I1(N541), + .I1(N539), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o11_5889 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o10_5888 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o21 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ), - .O(N532) + .O(N530) ); LUT6 #( .INIT ( 64'h8228411441148228 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW2_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW2_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]), - .O(N543) + .O(N541) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFA8A0 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW2 ( - .I0(N543), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW2 ( + .I0(N541), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o11_5889 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o10_5888 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o21 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ), - .O(N529) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_5044 ), + .O(N527) ); LUT5 #( .INIT ( 32'hFFFFFF96 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW3 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_130_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ), - .O(N530) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_132_o_5044 ), + .O(N528) ); LUT6 #( .INIT ( 64'h9600000000000069 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o ) ); LUT4 #( .INIT ( 16'hFFFE )) @@ -46773,60 +48336,60 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ), - .O(N545) + .O(N543) ); LUT6 #( .INIT ( 64'h3300320000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o3_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ), - .I1(N384), - .I2(N408), + .I1(N382), + .I2(N406), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o2_5898 ) , - .I4(N545), + .I4(N543), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o3_5899 ) , - .O(N527) + .O(N525) ); LUT6 #( .INIT ( 64'hFFFFFFFFFD75FDFD )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11_SW1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_126_o11_SW1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .I2(N547), - .I3(N548), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ), - .O(N501) + .I2(N545), + .I3(N546), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_330_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5878 ), + .O(N499) ); LUT3 #( .INIT ( 8'hDF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I2(N500), - .O(N550) + .I2(N498), + .O(N548) ); LUT3 #( .INIT ( 8'hDF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314_SW1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I2(N501), - .O(N551) + .I2(N499), + .O(N549) ); LUT6 #( .INIT ( 64'h00007FFF8000FFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW5 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW5 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), - .I4(N550), - .I5(N551), - .O(N533) + .I4(N548), + .I5(N549), + .O(N531) ); LUT4 #( .INIT ( 16'h9600 )) @@ -46834,8 +48397,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), - .I3(N500), - .O(N553) + .I3(N498), + .O(N551) ); LUT4 #( .INIT ( 16'h9600 )) @@ -46843,24 +48406,24 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), - .I3(N501), - .O(N554) + .I3(N499), + .O(N552) ); LUT6 #( .INIT ( 64'h00007FFF8000FFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o12_SW1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]), - .I4(N553), - .I5(N554), - .O(N523) + .I4(N551), + .I5(N552), + .O(N521) ); LUT6 #( .INIT ( 64'h010103030105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT72_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_4954 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_5195 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -46868,24 +48431,24 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N556) + .O(N554) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT72 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [25]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N556), + .I5(N554), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<15> ) ); LUT6 #( .INIT ( 64'h010103030105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT632_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_4948 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_5189 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -46893,24 +48456,24 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N558) + .O(N556) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT632 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [18]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N558), + .I5(N556), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<8> ) ); LUT6 #( .INIT ( 64'h010103030105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT65_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_4953 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_5194 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -46918,24 +48481,24 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N560) + .O(N558) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT65 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [24]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N560), + .I5(N558), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<14> ) ); LUT6 #( .INIT ( 64'h010103030105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT53_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_4952 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_5193 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -46943,24 +48506,24 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N562) + .O(N560) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT53 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [23]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N562), + .I5(N560), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<13> ) ); LUT6 #( .INIT ( 64'h010103030105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_4951 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_5192 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -46968,24 +48531,24 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N564) + .O(N562) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [22]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N564), + .I5(N562), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<12> ) ); LUT6 #( .INIT ( 64'h010103030105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_4950 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_5191 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -46993,18 +48556,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N566) + .O(N564) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [21]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N566), + .I5(N564), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<11> ) ); LUT6 #( @@ -47017,19 +48580,19 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [20]), - .O(N568) + .O(N566) ); LUT6 #( .INIT ( 64'h5555101110111011 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), - .I3(N568), + .I3(N566), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [12]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4915 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<10> ) ); @@ -47043,44 +48606,44 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [28]), - .O(N570) + .O(N568) ); LUT6 #( .INIT ( 64'h5555101110111011 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT10 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), - .I3(N570), + .I3(N568), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [20]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4915 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<18> ) ); LUT5 #( .INIT ( 32'h1133153F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT642_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_4949 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_5190 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N572) + .O(N570) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT642 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [19]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ), - .I5(N572), + .I5(N570), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<9> ) ); LUT6 #( @@ -47094,18 +48657,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N574) + .O(N572) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT252 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_4968 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_5209 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ), - .I5(N574), + .I5(N572), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<31> ) ); LUT6 #( @@ -47119,18 +48682,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N576) + .O(N574) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT242 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_4967 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_5208 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ), - .I5(N576), + .I5(N574), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<30> ) ); LUT6 #( @@ -47144,18 +48707,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N578) + .O(N576) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT222 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_4966 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_5207 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ), - .I5(N578), + .I5(N576), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<29> ) ); LUT6 #( @@ -47169,18 +48732,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N580) + .O(N578) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT212 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_4965 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_5206 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ), - .I5(N580), + .I5(N578), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<28> ) ); LUT6 #( @@ -47194,18 +48757,18 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ), - .O(N582) + .O(N580) ); LUT6 #( .INIT ( 64'h0C0A0C000C0F0C0F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT202 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_4964 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_5205 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ), - .I5(N582), + .I5(N580), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<27> ) ); LUT6 #( @@ -47217,10 +48780,10 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_4943 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_5184 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .O(N312) + .O(N310) ); LUT6 #( .INIT ( 64'hFFFFFFA8FFA8FFA8 )) @@ -47231,10 +48794,10 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_4944 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_5185 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .O(N314) + .O(N312) ); LUT5 #( .INIT ( 32'hFFA8A8A8 )) @@ -47246,9 +48809,9 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_4946 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_5187 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5631 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5865 ) ); LUT5 #( .INIT ( 32'hFFA8A8A8 )) @@ -47260,9 +48823,9 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_4947 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_5188 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5634 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5868 ) ); LUT5 #( .INIT ( 32'hFFA8A8A8 )) @@ -47272,10 +48835,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_4945 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_5186 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .O(N338) + .O(N336) ); LUT5 #( .INIT ( 32'h01110FFF )) @@ -47286,9 +48849,9 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_4942 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_5183 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]), - .O(N340) + .O(N338) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFA8 )) @@ -47301,12 +48864,12 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), - .O(N404) + .O(N402) ); LUT6 #( .INIT ( 64'hFFFFFFFFAAAAAAA8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT3311_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_4972 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_5213 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), @@ -47314,12 +48877,12 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ), - .O(N488) + .O(N486) ); LUT6 #( .INIT ( 64'hFFFFFFFFAAAAAAA8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT3311_SW1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_4971 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_5212 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), @@ -47327,7 +48890,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ), - .O(N490) + .O(N488) ); LUT5 #( .INIT ( 32'h10080000 )) @@ -47337,7 +48900,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ), - .O(N586) + .O(N584) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) @@ -47347,9 +48910,9 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ), - .I5(N586), + .I5(N584), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4955 ) ); LUT6 #( @@ -47367,7 +48930,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4545454544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT82 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [18]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47380,7 +48943,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4545454544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT162 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [25]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47393,7 +48956,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4545454544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT152 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [24]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47406,7 +48969,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4545454544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT142 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [23]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47419,7 +48982,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4545454544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT132 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [22]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47432,7 +48995,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4545454544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT112 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [21]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47448,12 +49011,12 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [49]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5575 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5809 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<47> ) ); LUT6 #( @@ -47462,9 +49025,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [48]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT41 ), @@ -47476,9 +49039,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [47]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT40 ), @@ -47490,9 +49053,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [46]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT39 ), @@ -47504,9 +49067,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [45]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT38 ), @@ -47518,9 +49081,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [42]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT35 ), @@ -47529,11 +49092,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555551045454500 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT614 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5631 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5865 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT611 ), @@ -47546,8 +49109,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), - .I4(N340), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), + .I4(N338), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<1> ) @@ -47555,7 +49118,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555544444440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT92 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [19]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ), .I3 @@ -47583,7 +49146,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT91 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_4956 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_5197 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ), .I4 @@ -47594,7 +49157,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEE0EAA0ACC0C0000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT441 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_4984 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_5225 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [59]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), @@ -47605,13 +49168,13 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h96FFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_SW0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_128_o2_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .O(N320) + .O(N318) ); LUT5 #( .INIT ( 32'h969669FF )) @@ -47621,7 +49184,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), - .O(N547) + .O(N545) ); LUT6 #( .INIT ( 64'hFFFFFFFF96FFFFFF )) @@ -47632,7 +49195,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .O(N548) + .O(N546) ); LUT5 #( .INIT ( 32'h96000000 )) @@ -47744,15 +49307,15 @@ loopback_ctrl ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW0 ( - .I0(N588), - .I1(N589), + .I0(N586), + .I1(N587), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 ), - .O(N506) + .O(N504) ); LUT6 #( .INIT ( 64'hFFFFFFFF55545555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW0_F ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5576 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o ) , @@ -47764,21 +49327,21 @@ loopback_ctrl , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111112 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ), - .O(N588) + .O(N586) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW0 ( - .I0(N590), + .I0(N588), .I1(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , - .O(N513) + .O(N511) ); LUT6 #( .INIT ( 64'hFFFFFFFF57FF54FC )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW0_F ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5577 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), @@ -47786,21 +49349,21 @@ loopback_ctrl .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , - .O(N590) + .O(N588) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW1 ( - .I0(N592), + .I0(N590), .I1(N0), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , - .O(N514) + .O(N512) ); LUT6 #( .INIT ( 64'hFFFFFFFF444F4440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW1_F ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5577 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), @@ -47808,103 +49371,103 @@ loopback_ctrl .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , - .O(N592) + .O(N590) ); LUT5 #( .INIT ( 32'h2E2EAAA2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_5771 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_6006 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3379 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_5780 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3624 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3623 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3636 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_6015 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3383 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_5781 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3628 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3627 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_6016 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3387 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_5782 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3632 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3631 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3637 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_6017 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3399 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_5783 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3644 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3643 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3656 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_6018 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3403 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_5784 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3648 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3647 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_6019 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3407 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_5785 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3652 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3651 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3657 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_6020 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3419 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_5786 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3663 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3676 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_6021 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3423 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_5787 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3668 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3667 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_6022 ) ); LUT3 #( .INIT ( 8'h9A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3427 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_5788 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3672 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3671 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3677 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_6023 ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_502 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_5772 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_538 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_535 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_6007 ) ); LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_5773 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_810_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_6008 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF808080D5 )) @@ -47912,13 +49475,13 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), - .O(N594) + .O(N592) ); LUT6 #( .INIT ( 64'h5555545555551011 )) @@ -47929,60 +49492,60 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5332 ), - .I3(N594), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5573 ), + .I3(N592), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5333 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5574 ) ); LUT2 #( .INIT ( 4'hD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ), .I1(reset), - .O(N598) + .O(N596) ); LUT6 #( .INIT ( 64'h1000100400000004 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot ( - .I0(N598), + .I0(N596), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_5778 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_6013 ) ); LUT2 #( .INIT ( 4'hD )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3576 ), .I1(reset), - .O(N600) + .O(N598) ); LUT6 #( .INIT ( 64'h5555515555555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot ( - .I0(N600), + .I0(N598), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3577 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3578 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_5779 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_6014 ) ); LUT6 #( .INIT ( 64'hFFFFAA08AA08AA08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT463_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [0]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I3 @@ -47990,18 +49553,18 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [0]), - .O(N602) + .O(N600) ); LUT5 #( .INIT ( 32'h55554440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT463 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), - .I4(N602), + .I4(N600), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<50> ) ); @@ -48010,7 +49573,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT473_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I3 @@ -48018,18 +49581,18 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [1]), - .O(N604) + .O(N602) ); LUT5 #( .INIT ( 32'h55554440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT473 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), - .I4(N604), + .I4(N602), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<51> ) ); @@ -48038,9 +49601,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]), .I1(txreset322), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5675 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2493 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5909 ) ); LUT4 #( .INIT ( 16'h0008 )) @@ -48050,7 +49613,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I3(reset), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_5776 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_6011 ) ); LUT2 #( .INIT ( 4'h4 )) @@ -48062,13 +49625,13 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0111111111111111 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ), .I1(txreset322), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]), .I4(N52), .I5(N606), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_5777 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_6012 ) ); LUT6 #( .INIT ( 64'h1505140411011000 )) @@ -48112,62 +49675,53 @@ loopback_ctrl LUT4 #( .INIT ( 16'hFF7F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0050_SW1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_579 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ), - .O(N525) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4470 ), + .O(N523) ); LUT3 #( .INIT ( 8'hA8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emptyg ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_5768 ) - ); - LUT4 #( - .INIT ( 16'hFA8A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_5770 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_6003 ) ); LUT4 #( .INIT ( 16'hFF8A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1988 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_2034 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5762 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1991 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5996 ) ); LUT4 #( .INIT ( 16'hAA08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1990 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5763 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_2034 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1989 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5997 ) ); LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1340 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1376 ), .I1(reset), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_5774 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1398 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_6009 ) ); LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1342 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1378 ), .I1(reset), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_5775 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1380 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_6010 ) ); LUT5 #( .INIT ( 32'hFFFF8880 )) @@ -48176,7 +49730,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT173 ), .O(N612) @@ -48184,7 +49738,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h20202000A8A8A888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT176 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5568 ), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ) , @@ -48192,7 +49746,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT175 ) ); @@ -48206,14 +49760,14 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_4941 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_5182 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]), .O(N614) ); LUT6 #( .INIT ( 64'h5510555545004545 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), @@ -48258,9 +49812,21 @@ loopback_ctrl .INIT ( 8'hA8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emptyg ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_5767 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2616 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_6001 ) + ); + LUT5 #( + .INIT ( 32'h8DD8D88D )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3_rstpot ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [3]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> ) +, + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3_rstpot_6002 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF20002202 )) @@ -48276,8 +49842,8 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 ) , .I4(N622), - .I5(N392), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5687 ) + .I5(N390), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5921 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF1011 )) @@ -48286,212 +49852,212 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5323 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5564 ), .I3(N624), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT8 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5691 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5925 ) ); LUT5 #( .INIT ( 32'hAA80AAAA )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0260_inv ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT17 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1667 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<0> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT21 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<10> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<10> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT31 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT31 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [11]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<11> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<11> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT41 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT41 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<12> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<12> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT51 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT51 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [13]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<13> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<13> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT61 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT61 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<14> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<14> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT71 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT71 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<15> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<15> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT81 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT81 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<1> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<1> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT91 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT91 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<2> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<2> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT101 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT101 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<3> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<3> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT111 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT111 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<4> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<4> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT121 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT121 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<5> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<5> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT131 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT131 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [6]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<6> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<6> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT141 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT141 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<7> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<7> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT151 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT151 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<8> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<8> ) ); LUT4 #( .INIT ( 16'hEA2A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT161 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_74_OUT161 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [9]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<9> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_74_OUT<9> ) ); LUT6 #( @@ -48602,7 +50168,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT28 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [3]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ), @@ -48632,7 +50198,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555555555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT29 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [4]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ), @@ -48649,7 +50215,7 @@ loopback_ctrl .INIT ( 32'hFF808080 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) @@ -48668,12 +50234,12 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5287 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5528 ) ); LUT6 #( @@ -48687,7 +50253,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5292 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5533 ) ); LUT6 #( @@ -48701,21 +50267,23 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5300 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5541 ) ); LUT6 #( - .INIT ( 64'hAAA22022FFFBBABB )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [2]), + .INIT ( 64'h0001000000000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), + .I3 +(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 ) +, + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> ) - +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ) ); LUT6 #( .INIT ( 64'hFFFFFFFFFEFFFEFE )) @@ -48727,7 +50295,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4915 ) ); LUT4 #( .INIT ( 16'hFFFE )) @@ -48770,19 +50338,6 @@ loopback_ctrl .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT621 ) - ); - LUT6 #( - .INIT ( 64'h23DCDC232AD5D52A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_xor<2>11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [2]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<2> ) - ); LUT4 #( .INIT ( 16'h8000 )) @@ -48799,10 +50354,10 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]), .I1(N636), .I2(N52), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2493 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2502 ), .I5(txreset322), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5676 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5910 ) ); LUT6 #( .INIT ( 64'h2222200020002000 )) @@ -48815,7 +50370,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5288 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5529 ) ); LUT6 #( @@ -48829,7 +50384,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5296 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5537 ) ); LUT6 #( @@ -48840,7 +50395,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o ) ); LUT6 #( @@ -48851,7 +50406,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ) ); LUT6 #( @@ -48872,10 +50427,10 @@ loopback_ctrl .INIT ( 32'h40404000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5228 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5484 ) , .I4(N638), .O @@ -48884,26 +50439,38 @@ loopback_ctrl ); LUT6 #( .INIT ( 64'h2020200000200000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n02561 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n02541 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1679 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0254 ) ); LUT5 #( .INIT ( 32'h88800800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0266_inv ) + ); + LUT5 #( + .INIT ( 32'h9099FFFF )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT211 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT21_4620 ) + ); LUT6 #( .INIT ( 64'h8000000000000000 )) @@ -48913,43 +50480,43 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ) ); LUT6 #( .INIT ( 64'h2112844884482112 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1_5645 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o1_5879 ) ); LUT6 #( .INIT ( 64'h1221488448841221 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o7 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [55]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7_5651 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o7_5885 ) ); LUT6 #( .INIT ( 64'h1221488448841221 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o11_5889 ) ); LUT5 #( .INIT ( 32'h82800200 )) @@ -48960,7 +50527,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [7]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5210 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5466 ) ); LUT5 #( @@ -48984,19 +50551,19 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5230 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5486 ) ); LUT5 #( .INIT ( 32'h14100400 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [8]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [8]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [10]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5243 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21_5492 ) ); LUT5 #( @@ -49008,31 +50575,19 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [12]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5250 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5505 ) ); LUT5 #( .INIT ( 32'h14100400 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [9]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [9]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5257 ) - - ); - LUT5 #( - .INIT ( 32'h14100400 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [13]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [13]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [8]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5266 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5512 ) ); LUT5 #( @@ -49044,32 +50599,20 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [15]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5272 ) - - ); - LUT5 #( - .INIT ( 32'h14100400 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [10]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [10]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5279 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5520 ) ); LUT6 #( .INIT ( 64'h8684060482800200 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [8]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [8]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [10]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5245 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5494 ) ); LUT6 #( @@ -49082,33 +50625,20 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [12]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5252 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5507 ) ); LUT6 #( .INIT ( 64'h8684060482800200 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [9]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [9]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5259 ) - - ); - LUT6 #( - .INIT ( 64'h8684060482800200 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [13]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [13]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [0]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [8]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5265 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5514 ) ); LUT6 #( @@ -49117,24 +50647,11 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1989 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [15]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5274 ) - - ); - LUT6 #( - .INIT ( 64'h8684060482800200 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [10]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [10]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5281 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5522 ) ); LUT5 #( @@ -49146,7 +50663,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5216 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5472 ) ); LUT5 #( @@ -49158,7 +50675,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5224 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5480 ) ); LUT5 #( @@ -49170,7 +50687,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5237 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5499 ) ); LUT6 #( @@ -49179,11 +50696,11 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1988 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [14]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5239 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5501 ) ); LUT6 #( @@ -49195,7 +50712,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ), - .O(N418) + .O(N416) ); LUT5 #( .INIT ( 32'hFEFEFEFF )) @@ -49204,7 +50721,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ), - .I4(N370), + .I4(N368), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<1> ) ); LUT6 #( @@ -49214,7 +50731,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ), - .I4(N370), + .I4(N368), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<6> ) ); @@ -49225,7 +50742,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ), - .I4(N370), + .I4(N368), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<7> ) ); @@ -49234,31 +50751,23 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT4 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ), - .I2(N370), - .I3(N330), + .I2(N368), + .I3(N328), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<3> ) ); - LUT3 #( - .INIT ( 8'h96 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_ra_writesync<1>_xo<0>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [1]) - ); LUT6 #( .INIT ( 64'hFFFFFFFFFFFF111F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT12311 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5305 ) ); LUT6 #( .INIT ( 64'h000E000E000E0000 )) @@ -49266,21 +50775,21 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4467 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 ) ); LUT6 #( .INIT ( 64'h96FFFF96FF9696FF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o211_SW1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o211_SW1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]), - .O(N416) + .O(N414) ); LUT5 #( .INIT ( 32'hFFFEFEFE )) @@ -49290,18 +50799,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]), - .O(N492) - ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode211 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) - + .O(N490) ); LUT6 #( .INIT ( 64'hDFFFFFFFFFFFFFFF )) @@ -49383,17 +50881,6 @@ loopback_ctrl .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<0> ) ); - LUT6 #( - .INIT ( 64'h0000000100010000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5557 ) - ); LUT6 #( .INIT ( 64'h7FFFFFFFFFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT46_SW0 ( @@ -49403,7 +50890,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [60]), - .O(N346) + .O(N344) ); LUT5 #( .INIT ( 32'h2AAAAAAA )) @@ -49415,13 +50902,13 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5576 ) ); LUT3 #( .INIT ( 8'hF2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I2(reset), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ) ); @@ -49439,7 +50926,7 @@ loopback_ctrl .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5404 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5645 ) ); LUT6 #( @@ -49447,19 +50934,19 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5197 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5453 ) ); LUT6 #( .INIT ( 64'h0111051501110111 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT10_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -49468,13 +50955,13 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), - .O(N168) + .O(N170) ); LUT6 #( .INIT ( 64'h0111051501110111 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT11_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -49483,13 +50970,13 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), - .O(N170) + .O(N172) ); LUT6 #( .INIT ( 64'h0111051501110111 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT13_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -49498,13 +50985,13 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), - .O(N172) + .O(N174) ); LUT6 #( .INIT ( 64'h0111051501110111 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT14_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), @@ -49513,12 +51000,12 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), - .O(N174) + .O(N176) ); LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o<15>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), @@ -49532,7 +51019,7 @@ loopback_ctrl .I0(pma_pmd_type[2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I4(pma_pmd_type[1]), @@ -49588,7 +51075,7 @@ loopback_ctrl .INIT ( 64'h0004040400555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT26_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), @@ -49597,13 +51084,13 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [1]), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), - .O(N204) + .O(N206) ); LUT6 #( .INIT ( 64'h0004040400555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT27_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), @@ -49612,7 +51099,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [2]), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ), - .O(N206) + .O(N208) ); LUT5 #( .INIT ( 32'hFFABFFA8 )) @@ -49621,7 +51108,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [0]), .O @@ -49635,7 +51122,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [24]), .O @@ -49649,7 +51136,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [2]), .O @@ -49663,7 +51150,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [34]), .O @@ -49677,7 +51164,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [35]), .O @@ -49691,7 +51178,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [36]), .O @@ -49705,7 +51192,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [39]), .O @@ -49719,7 +51206,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [3]), .O @@ -49733,7 +51220,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [4]), .O @@ -49747,7 +51234,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [56]), .O @@ -49761,7 +51248,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [7]), .O @@ -49775,20 +51262,52 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I3(rxreset322), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [4]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<4> ) ); + LUT6 #( + .INIT ( 64'h0000DDFDDDFD0000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<1>11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0139 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 ) + ); + LUT6 #( + .INIT ( 64'h2222202222222222 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_cnt[5]_wide_mux_49_OUT11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_valid ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_cnt[5]_wide_mux_49_OUT<0> ) + ); + LUT5 #( + .INIT ( 32'h8000FFFF )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5797 ) + ); LUT4 #( .INIT ( 16'h0008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n10781 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ) ); LUT6 #( @@ -49798,10 +51317,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<37> ) @@ -49814,10 +51333,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<38> ) @@ -49830,10 +51349,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [43]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [11]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<43> ) @@ -49846,10 +51365,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [44]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [12]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<44> ) @@ -49862,10 +51381,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [45]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [13]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<45> ) @@ -49878,10 +51397,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [46]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [14]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<46> ) @@ -49894,10 +51413,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [47]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [15]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<47> ) @@ -49910,10 +51429,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [51]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [19]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<51> ) @@ -49926,10 +51445,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [52]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [20]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<52> ) @@ -49942,10 +51461,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [53]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [21]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<53> ) @@ -49958,10 +51477,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [54]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [22]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<54> ) @@ -49974,10 +51493,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [55]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [23]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<55> ) @@ -49990,10 +51509,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [59]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [27]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<59> ) @@ -50006,10 +51525,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [60]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [28]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<60> ) @@ -50022,10 +51541,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [61]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [29]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<61> ) @@ -50038,10 +51557,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [62]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [30]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<62> ) @@ -50054,10 +51573,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [63]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [31]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<63> ) @@ -50067,13 +51586,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT61 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [69]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<5> ) @@ -50083,13 +51602,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT71 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [70]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<6> ) @@ -50099,13 +51618,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT81 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [71]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<7> ) @@ -50115,13 +51634,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1271 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [33]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<33> ) @@ -50131,13 +51650,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1361 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [9]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [41]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<41> ) @@ -50147,13 +51666,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1371 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [10]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [42]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<42> ) @@ -50163,13 +51682,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1441 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [17]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [49]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<49> ) @@ -50179,13 +51698,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1461 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [18]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [50]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<50> ) @@ -50195,13 +51714,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1531 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [25]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [57]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<57> ) @@ -50211,13 +51730,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1541 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [26]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [58]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<58> ) @@ -50229,12 +51748,12 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [64]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [68]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<4> ) @@ -50245,12 +51764,12 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<34> ) @@ -50258,43 +51777,69 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000040004000400 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [4]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ) ); LUT6 #( .INIT ( 64'hFFFFFFFF44404044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), .I5(rxreset322), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ) ); + LUT6 #( + .INIT ( 64'h5555400040004000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [5]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [13]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5430 ) + + ); + LUT6 #( + .INIT ( 64'h5555400040004000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [9]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5446 ) + + ); LUT6 #( .INIT ( 64'h5555400040004000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5206 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5462 ) ); LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_54_o<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), @@ -50309,9 +51854,9 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o ) ); LUT6 #( @@ -50319,7 +51864,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50333,14 +51878,14 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o ) ); LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o<15>1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), @@ -50350,34 +51895,20 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5241 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5510 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5242 ) - - ); - LUT5 #( - .INIT ( 32'h00800000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5255 ) -, - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5256 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5511 ) ); LUT6 #( .INIT ( 64'h0000002000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT168 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT158 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50385,10 +51916,10 @@ loopback_ctrl (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5262 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT157_5517 ) ); LUT6 #( @@ -50400,30 +51931,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ), - .O(N390) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFBFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<0> ) - ); - LUT6 #( - .INIT ( 64'hFFFFFFFFBFFFFFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<0> ) + .O(N388) ); LUT6 #( .INIT ( 64'h6AAAAAAAAAAAAAAA )) @@ -50462,14 +51970,14 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ) ); LUT4 #( .INIT ( 16'h0008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), @@ -50486,7 +51994,7 @@ loopback_ctrl .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), @@ -50498,15 +52006,15 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5507 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5748 ) ); LUT4 #( .INIT ( 16'h5DFF )) @@ -50521,14 +52029,14 @@ loopback_ctrl .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2014 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2050 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ) ); @@ -50541,7 +52049,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_377_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [16]) ); LUT6 #( @@ -50553,26 +52061,26 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_377_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [17]) ); LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we11 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3(NlwRenamedSig_OI_pcs_resetout), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ) ); LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50585,7 +52093,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50598,7 +52106,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50611,7 +52119,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50624,7 +52132,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50637,7 +52145,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50650,7 +52158,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50663,7 +52171,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50676,7 +52184,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50689,7 +52197,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50702,7 +52210,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50715,7 +52223,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50728,7 +52236,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50741,7 +52249,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50754,7 +52262,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50767,7 +52275,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -50780,7 +52288,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50793,7 +52301,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50806,7 +52314,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50819,7 +52327,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50832,7 +52340,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50845,7 +52353,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50858,7 +52366,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50871,7 +52379,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50884,7 +52392,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50897,7 +52405,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50910,7 +52418,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50923,7 +52431,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50936,7 +52444,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50949,7 +52457,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50962,7 +52470,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50975,7 +52483,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -50988,7 +52496,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51001,7 +52509,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51014,7 +52522,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51027,7 +52535,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51040,7 +52548,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51053,7 +52561,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51066,7 +52574,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51079,7 +52587,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51092,7 +52600,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51105,7 +52613,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51118,7 +52626,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51131,7 +52639,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51144,7 +52652,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51157,7 +52665,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51170,7 +52678,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51183,7 +52691,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), @@ -51197,7 +52705,7 @@ loopback_ctrl .INIT ( 64'hFEFEFEFFFEFEFEFE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>11 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), @@ -51218,7 +52726,7 @@ loopback_ctrl .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]), .I4 @@ -51393,15 +52901,6 @@ loopback_ctrl .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [21]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [19]) ); - LUT4 #( - .INIT ( 16'h028A )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ) - ); LUT6 #( .INIT ( 64'h1111111011110100 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT131 ( @@ -51409,10 +52908,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [11]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [43]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<11> ) @@ -51425,10 +52924,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [12]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [44]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<12> ) @@ -51441,10 +52940,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [13]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [45]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<13> ) @@ -51457,10 +52956,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [14]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [46]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<14> ) @@ -51473,10 +52972,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [15]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [47]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<15> ) @@ -51489,10 +52988,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [19]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [51]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<19> ) @@ -51505,10 +53004,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [20]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [52]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<20> ) @@ -51521,10 +53020,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [21]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [53]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<21> ) @@ -51537,10 +53036,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [22]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [54]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<22> ) @@ -51553,10 +53052,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [23]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [55]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<23> ) @@ -51569,10 +53068,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [27]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [59]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<27> ) @@ -51585,10 +53084,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [28]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [60]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<28> ) @@ -51601,10 +53100,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [29]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [61]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<29> ) @@ -51617,10 +53116,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [30]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [62]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<30> ) @@ -51633,10 +53132,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [31]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [63]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<31> ) @@ -51649,10 +53148,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [37]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<5> ) @@ -51665,10 +53164,10 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [38]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<6> ) @@ -51678,13 +53177,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT21 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [5]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<1> ) @@ -51694,13 +53193,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT31 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [6]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<2> ) @@ -51710,13 +53209,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT41 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [7]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<3> ) @@ -51726,13 +53225,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT121 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [42]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [10]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<10> ) @@ -51742,13 +53241,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT191 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [49]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [17]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<17> ) @@ -51758,13 +53257,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1101 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [50]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [18]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<18> ) @@ -51774,13 +53273,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1121 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [33]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<1> ) @@ -51790,13 +53289,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1181 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [57]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [25]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<25> ) @@ -51806,13 +53305,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1191 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [58]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [26]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<26> ) @@ -51822,13 +53321,13 @@ loopback_ctrl .INIT ( 64'h5555555155555540 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1641 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [41]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [9]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<9> ) @@ -51840,12 +53339,12 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [34]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_384_o ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<2> ) @@ -51853,12 +53352,12 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00010000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<1> ) @@ -51868,9 +53367,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [10]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<10> ) ); @@ -51879,9 +53378,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT71 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [15]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<15> ) ); @@ -51890,9 +53389,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT81 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [16]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<16> ) ); @@ -51901,9 +53400,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT91 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [17]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<17> ) ); @@ -51912,9 +53411,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [1]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<1> ) ); @@ -51923,9 +53422,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT151 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [22]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<22> ) ); @@ -51934,9 +53433,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT161 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [23]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<23> ) ); @@ -51945,9 +53444,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT171 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [24]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<24> ) ); @@ -51956,9 +53455,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT221 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [29]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<29> ) ); @@ -51967,9 +53466,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT241 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [30]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<30> ) ); @@ -51978,9 +53477,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT251 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [31]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<31> ) ); @@ -51989,9 +53488,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT301 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [36]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<36> ) ); @@ -52000,9 +53499,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT321 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [38]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<38> ) ); @@ -52011,9 +53510,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT311 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [37]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<37> ) ); @@ -52022,9 +53521,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT381 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [43]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<43> ) ); @@ -52033,9 +53532,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT391 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [44]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<44> ) ); @@ -52044,9 +53543,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT401 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [45]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<45> ) ); @@ -52055,9 +53554,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT461 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [50]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<50> ) ); @@ -52066,9 +53565,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT471 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [51]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<51> ) ); @@ -52077,9 +53576,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT481 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [52]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<52> ) ); @@ -52088,9 +53587,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT531 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [57]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<57> ) ); @@ -52099,9 +53598,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT551 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [59]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<59> ) ); @@ -52110,9 +53609,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT611 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [64]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<64> ) ); @@ -52121,9 +53620,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT621 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [65]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<65> ) ); @@ -52132,9 +53631,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT641 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<7> ) ); @@ -52143,9 +53642,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT661 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [9]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4392 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<9> ) ); @@ -52159,7 +53658,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [27]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5528 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5769 ) ); LUT6 #( @@ -52172,7 +53671,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [28]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5529 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5770 ) ); LUT6 #( @@ -52276,7 +53775,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [36]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5539 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5780 ) ); LUT6 #( @@ -52289,7 +53788,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [37]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5540 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5781 ) ); LUT6 #( @@ -52334,8 +53833,8 @@ loopback_ctrl LUT2 #( .INIT ( 4'h4 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ) ); LUT4 #( @@ -52508,10 +54007,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata17 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [0]) ); @@ -52519,10 +54018,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [10]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [10]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [10]) ); @@ -52530,10 +54029,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata31 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [11]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [11]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [11]) ); @@ -52541,10 +54040,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata41 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [12]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [12]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [12]) ); @@ -52552,10 +54051,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata51 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [13]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [13]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [13]) ); @@ -52563,10 +54062,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata61 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [14]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [14]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [14]) ); @@ -52574,10 +54073,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata71 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [15]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [15]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [15]) ); @@ -52585,10 +54084,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata81 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [1]) ); @@ -52596,10 +54095,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata91 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [2]) ); @@ -52607,10 +54106,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata101 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [3]) ); @@ -52618,10 +54117,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata111 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [4]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [4]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [4]) ); @@ -52629,10 +54128,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata121 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [5]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [5]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [5]) ); @@ -52640,10 +54139,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata131 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [6]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [6]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [6]) ); @@ -52651,10 +54150,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata141 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [7]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [7]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [7]) ); @@ -52662,10 +54161,10 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata151 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [8]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [8]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [8]) ); @@ -52673,17 +54172,17 @@ loopback_ctrl .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata161 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [9]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [9]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [9]) ); LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]), .O @@ -52693,7 +54192,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]), .O @@ -52703,7 +54202,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]), .O @@ -52713,7 +54212,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]), .O @@ -52723,7 +54222,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]), .O @@ -52733,7 +54232,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5]), .O @@ -52743,7 +54242,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0]), .O @@ -52753,7 +54252,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]), .O @@ -52763,7 +54262,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2]), .O @@ -52773,7 +54272,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]), .O @@ -52783,7 +54282,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]), .O @@ -52793,7 +54292,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]), .O @@ -52803,7 +54302,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]), .O @@ -52813,7 +54312,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]), .O @@ -52823,7 +54322,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [0]), .O @@ -52833,7 +54332,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [10]), .O @@ -52843,7 +54342,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [11]), .O @@ -52853,7 +54352,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [12]), .O @@ -52863,7 +54362,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [13]), .O @@ -52873,7 +54372,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [14]), .O @@ -52883,7 +54382,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [15]), .O @@ -52893,7 +54392,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [1]), .O @@ -52903,7 +54402,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [2]), .O @@ -52913,7 +54412,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [3]), .O @@ -52923,7 +54422,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [4]), .O @@ -52933,7 +54432,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [5]), .O @@ -52943,7 +54442,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [6]), .O @@ -52953,7 +54452,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [7]), .O @@ -52963,7 +54462,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [8]), .O @@ -52973,7 +54472,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [9]), .O @@ -53016,20 +54515,20 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2-In1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4394 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4395 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4393 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/_n0043 [58]) ); LUT6 #( .INIT ( 64'hFFFFFFFF15551515 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_01 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_0 ) ); @@ -53043,7 +54542,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4586 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4827 ) ); LUT6 #( @@ -53062,34 +54561,34 @@ loopback_ctrl LUT5 #( .INIT ( 32'h82D7FFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5565 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5799 ) ); LUT6 #( .INIT ( 64'h0000000000009600 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o8 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8_5652 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o8_5886 ) ); LUT6 #( .INIT ( 64'h0000009600000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o9 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9_5653 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_125_o9_5887 ) ); LUT6 #( .INIT ( 64'hFF96FFFFFFFF69FF )) @@ -53100,7 +54599,24 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]), - .O(N504) + .O(N502) + ); + LUT6 #( + .INIT ( 64'h2222222222202020 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT810 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT89_5542 ) +, + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), + .I5 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT8 ) +, + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [1]) ); LUT6 #( .INIT ( 64'h0800000008000800 )) @@ -53109,8 +54625,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ) ); LUT6 #( @@ -53120,8 +54636,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ) ); LUT6 #( @@ -53130,7 +54646,7 @@ loopback_ctrl .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) , - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ), @@ -53141,14 +54657,14 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0404040004400400 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT139 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5204 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5460 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [6]) ); @@ -53160,29 +54676,13 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5293 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5534 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5286 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5527 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [0]) - ); - LUT6 #( - .INIT ( 64'h0010001000100000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT810 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5301 ) -, - .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT8 ) -, - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [1]) ); LUT4 #( .INIT ( 16'h4555 )) @@ -53191,17 +54691,17 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ), - .O(N366) + .O(N364) ); LUT6 #( .INIT ( 64'hFFFFFFFFAAAA0020 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_121_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ) ); LUT5 #( @@ -53224,36 +54724,35 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o_mmx_out ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3687 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT8 ) ); + LUT6 #( + .INIT ( 64'h2222200020002000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT27 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039971 ), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5496 ) +, + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), + .I5 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [10]) + ); LUT6 #( .INIT ( 64'h0000002000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ) ); - LUT6 #( - .INIT ( 64'h0010001000100000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT58 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5269 ) -, - .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ) -, - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [13]) - ); LUT6 #( .INIT ( 64'h0202020002000200 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13 ( @@ -53262,13 +54761,13 @@ loopback_ctrl (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5285 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5526 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ), .I5(pma_pmd_type[0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5286 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5527 ) ); LUT5 #( @@ -53277,7 +54776,7 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ), @@ -53294,7 +54793,7 @@ loopback_ctrl , .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 ) @@ -53302,20 +54801,20 @@ loopback_ctrl .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ) ); LUT6 #( - .INIT ( 64'hFFFFFFFFAAAAAA80 )) + .INIT ( 64'hFFFFFFFFAAAAA888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT19_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [2]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), .I2 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ), - .O(N166) + .O(N168) ); LUT6 #( .INIT ( 64'h0001010155555555 )) @@ -53331,7 +54830,7 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [1]), - .O(N176) + .O(N178) ); LUT6 #( .INIT ( 64'h0001010155555555 )) @@ -53347,7 +54846,7 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [3]), - .O(N178) + .O(N180) ); LUT6 #( .INIT ( 64'h0001010155555555 )) @@ -53363,7 +54862,7 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [4]), - .O(N180) + .O(N182) ); LUT5 #( .INIT ( 32'hFFFFFFFD )) @@ -53379,68 +54878,100 @@ loopback_ctrl .INIT ( 16'hD580 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In3 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5314 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5555 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In ) ); LUT6 #( - .INIT ( 64'h66F6FFFF0090FFFF )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1_5561 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2_5562 ) + .INIT ( 64'h0000410041000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT21 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<1> ) ); LUT6 #( - .INIT ( 64'h0010001000100000 )) + .INIT ( 64'h2222222222202020 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT911 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5187 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5428 ) , + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5186 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5427 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [2]) + ); + LUT5 #( + .INIT ( 32'h22202020 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT59 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT57_5436 ) +, + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039917 ), + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [13]) + ); + LUT5 #( + .INIT ( 32'h11011000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5430 ) +, + .I4 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 ) +, + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5431 ) + ); LUT6 #( .INIT ( 64'h0404040004400400 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5234 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5490 ) , - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [5]) ); LUT6 #( .INIT ( 64'h0010001000100000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT169 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT159 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5262 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT157_5517 ) , .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5261 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5516 ) , .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [9]) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [8]) ); LUT6 #( .INIT ( 64'h0000002000000000 )) @@ -53451,7 +54982,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5276 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5524 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [15]) @@ -53459,7 +54990,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'hFAFA2AAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]), @@ -53468,27 +54999,6 @@ loopback_ctrl , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In ) ); - LUT5 #( - .INIT ( 32'h28888888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<3> ) - ); - LUT6 #( - .INIT ( 64'h2888888888888888 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<4> ) - ); LUT5 #( .INIT ( 32'hFFFF2000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>11 ( @@ -53499,7 +55009,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ) @@ -53556,9 +55066,9 @@ loopback_ctrl .INIT ( 64'h8880080008000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT10 ) @@ -53568,153 +55078,115 @@ loopback_ctrl , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5221 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5477 ) ); LUT6 #( .INIT ( 64'h8880080008000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5230 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5486 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5231 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5487 ) ); LUT6 #( .INIT ( 64'h8880080008000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5243 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21_5492 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [8]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [10]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5244 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5493 ) ); LUT6 #( .INIT ( 64'h8880080008000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5250 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5505 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [12]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5251 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5506 ) ); LUT6 #( .INIT ( 64'h8880080008000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5257 ) -, - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) -, - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [9]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5258 ) - - ); - LUT6 #( - .INIT ( 64'h8880080008000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5266 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5512 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [13]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [8]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5267 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5513 ) ); LUT6 #( .INIT ( 64'h8880080008000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5272 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5520 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [15]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5273 ) - - ); - LUT6 #( - .INIT ( 64'h8880080008000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24 ( - .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5279 ) -, - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) -, - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [10]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5280 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5521 ) ); LUT5 #( .INIT ( 32'hFFFF0888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5331 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5572 ) ); LUT6 #( .INIT ( 64'h51555555FFFFFFFF )) @@ -53723,13 +55195,13 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5410 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5651 ) ); LUT6 #( .INIT ( 64'hFFFFFFF8FFF8FFF8 )) @@ -53741,11 +55213,11 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ) @@ -53760,7 +55232,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 ) @@ -53787,7 +55259,7 @@ loopback_ctrl .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>11 ) , - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ), .O @@ -53797,45 +55269,45 @@ loopback_ctrl .INIT ( 64'h8880080008000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5216 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5472 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [4]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5217 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5473 ) ); LUT6 #( .INIT ( 64'h8880080008000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5543 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5544 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5237 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5499 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [14]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5238 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5500 ) ); LUT6 #( .INIT ( 64'h011105553333FFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT33_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ), @@ -53845,13 +55317,13 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [1]), - .O(N94) + .O(N96) ); LUT6 #( .INIT ( 64'h011105553333FFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT35_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ), @@ -53861,13 +55333,13 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [2]), - .O(N96) + .O(N98) ); LUT6 #( .INIT ( 64'h011105553333FFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT36_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) , .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ), @@ -53877,7 +55349,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [3]), - .O(N98) + .O(N100) ); LUT5 #( .INIT ( 32'h1555FFFF )) @@ -53889,7 +55361,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [0]), - .O(N120) + .O(N122) ); LUT5 #( .INIT ( 32'h1555FFFF )) @@ -53901,7 +55373,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [5]), - .O(N122) + .O(N124) ); LUT5 #( .INIT ( 32'h1555FFFF )) @@ -53913,19 +55385,19 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [6]), - .O(N124) + .O(N126) ); LUT6 #( .INIT ( 64'h5555555544405555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT30 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), - .I4(N128), + .I4(N130), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 ) , @@ -53935,14 +55407,14 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5555555544405555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [3]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), - .I4(N130), + .I4(N132), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 ) , @@ -53952,48 +55424,48 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4444444055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT55 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [0]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), - .I5(N132), + .I5(N134), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<59> ) ); LUT6 #( .INIT ( 64'h4444444055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), - .I5(N134), + .I5(N136), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<64> ) ); LUT6 #( .INIT ( 64'h4444444055555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT62 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [6]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ), - .I5(N136), + .I5(N138), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<65> ) ); @@ -54007,15 +55479,15 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5409 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5650 ) ); LUT4 #( .INIT ( 16'hEE0E )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n00141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_2034 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ) ); LUT6 #( @@ -54034,7 +55506,7 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), @@ -54047,31 +55519,31 @@ loopback_ctrl .INIT ( 64'h55555155FFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT38_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [1]), - .O(N116) + .O(N118) ); LUT6 #( .INIT ( 64'h55555155FFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT39_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [2]), - .O(N118) + .O(N120) ); LUT5 #( .INIT ( 32'hFFFFFDFF )) @@ -54081,7 +55553,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5485 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5726 ) ); LUT6 #( .INIT ( 64'h69C369693C963C3C )) @@ -54146,26 +55618,35 @@ loopback_ctrl .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [58]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [58]) ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5445 ) + + ); LUT5 #( .INIT ( 32'h00000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 ) ); - LUT4 #( - .INIT ( 16'h0002 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ) + LUT3 #( + .INIT ( 8'h10 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_dwe11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd2_2105 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/state_FSM_FFd1_2106 ), + .O(drp_dwe) ); LUT5 #( .INIT ( 32'h00800000 )) @@ -54330,7 +55811,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h000100050003000F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT31_SW1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_4973 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_5214 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [47]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2721 ), @@ -54345,7 +55826,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4444040054555455 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), @@ -54356,7 +55837,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'h0105030F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT26_SW1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_4969 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_5210 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [42]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ), @@ -54369,7 +55850,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4444040054555455 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT26 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), @@ -54380,7 +55861,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h000100050003000F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT273_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_4970 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_5211 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [43]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT27 ), @@ -54395,7 +55876,7 @@ loopback_ctrl LUT6 #( .INIT ( 64'h4444040054555455 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT273 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), @@ -54419,9 +55900,9 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [44]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4916 ) , .I5(N646), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<42> ) @@ -54434,7 +55915,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3833 ) , .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ), .O(N648) @@ -54450,47 +55931,73 @@ loopback_ctrl .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ) + ); + LUT5 #( + .INIT ( 32'hEAAAAAAA )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT39_SW0 ( + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5442 ) +, + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5443 ) +, + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .O(N650) + ); + LUT6 #( + .INIT ( 64'h5555555501000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT39 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 ) +, + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1286 ), + .I5(N650), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38 ) + ); LUT6 #( .INIT ( 64'h101000101111FF11 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1962 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1754 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_5798 ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1790 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_585 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_6033 ) ); - LUT5 #( - .INIT ( 32'hFF808080 )) + LUT4 #( + .INIT ( 16'hF888 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_SW0 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) -, - .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) -, - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [1]), - .I3 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [1]), + .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [1]), - .O(N650) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [1]), + .O(N652) ); - LUT6 #( - .INIT ( 64'hEAEAEAEAFFEAEAEA )) + LUT5 #( + .INIT ( 32'hFFFFEAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83 ( - .I0(N650), + .I0 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [1]), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .I2 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) +, + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [1]), + .I4(N652), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5536 ) ); LUT5 #( @@ -54498,85 +56005,107 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1 ( .I0 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1963 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1753 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_5797 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1789 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_6032 ) ); LUT5 #( .INIT ( 32'h0808AA08 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_586 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1756 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1792 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1996 ), .I4 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_5799 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_6034 ) ); LUT4 #( .INIT ( 16'hFEE8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_5792 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3641 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3640 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3642 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3639 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_6027 ) ); LUT4 #( .INIT ( 16'hFEE8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_5793 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3661 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3660 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3662 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3659 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_6028 ) ); LUT4 #( .INIT ( 16'hFEE8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_5794 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3681 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3680 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3682 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3679 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_6029 ) ); LUT4 #( .INIT ( 16'h2262 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3676 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5683 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_587 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5917 ) ); LUT4 #( .INIT ( 16'h6222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3677 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5684 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_587 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5918 ) ); LUT4 #( .INIT ( 16'h6222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3678 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5685 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3676 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_587 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5919 ) ); LUT4 #( .INIT ( 16'hFFF8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3579 ), .I2(reset), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_5791 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2733 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_6026 ) + ); + LUT6 #( + .INIT ( 64'h0000000100010000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_SW0 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .O(N654) + ); + LUT6 #( + .INIT ( 64'h2CAA28AA28AA28AA )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .I5(N654), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_6005 ) ); LUT5 #( .INIT ( 32'hEFFFFFFF )) @@ -54586,18 +56115,18 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]), - .O(N652) + .O(N656) ); LUT6 #( .INIT ( 64'hAAAAAAAEAAA2AAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4 [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [4]), - .I2(N652), + .I2(N656), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_5789 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_6024 ) ); LUT5 #( .INIT ( 32'hEFFFFFFF )) @@ -54607,37 +56136,37 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]), - .O(N654) + .O(N658) ); LUT6 #( .INIT ( 64'hAAAAAAAEAAA2AAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0 [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [0]), - .I2(N654), + .I2(N658), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_5790 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_6025 ) ); LUT3 #( .INIT ( 8'hFB )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_SW1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), - .O(N656) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), + .O(N660) ); LUT6 #( .INIT ( 64'h1010101054101010 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1377 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1398 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), - .I5(N656), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_5796 ) + .I5(N660), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_6031 ) ); LUT6 #( .INIT ( 64'h8000000000000000 )) @@ -54648,7 +56177,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]), - .O(N658) + .O(N662) ); LUT6 #( .INIT ( 64'h40FF404040404040 )) @@ -54657,10 +56186,10 @@ loopback_ctrl .I1(N616), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48]), - .I4(N658), + .I4(N662), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5383 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5624 ) ); LUT6 #( @@ -54672,7 +56201,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]), - .O(N660) + .O(N664) ); LUT6 #( .INIT ( 64'h40FF404040404040 )) @@ -54681,10 +56210,10 @@ loopback_ctrl .I1(N618), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]), - .I4(N660), + .I4(N664), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5384 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5625 ) ); LUT6 #( @@ -54696,19 +56225,19 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]), - .O(N662) + .O(N666) ); LUT6 #( .INIT ( 64'h40FF404040404040 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17 ( - .I0(N662), + .I0(N666), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [11]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [10]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]), .I5(N620), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5385 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5626 ) ); LUT5 #( @@ -54722,26 +56251,19 @@ loopback_ctrl .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ) ); LUT6 #( - .INIT ( 64'h0000000000000002 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ) - ); - LUT6 #( - .INIT ( 64'h0001000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o<15>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ) + .INIT ( 64'h0000002000000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT821 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), + .I1 +(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0400 ), + .I5 +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ) + ); LUT6 #( .INIT ( 64'h888888F888888888 )) @@ -54753,14 +56275,14 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , - .O(N664) + .O(N668) ); LUT6 #( .INIT ( 64'h5555555555554440 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT32 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [4]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ), @@ -54768,9 +56290,9 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) , .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3730 ) , - .I5(N664), + .I5(N668), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<38> ) ); @@ -54783,6 +56305,17 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 ) ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode211 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1760 ) + + ); LUT6 #( .INIT ( 64'hEAAAAAAAAAAAAAAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/pcs_clear_test_pattern_error_count_core1 ( @@ -54794,7 +56327,7 @@ loopback_ctrl , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count ) ); @@ -54810,25 +56343,25 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3731 ) ); LUT6 #( .INIT ( 64'hAAABABAAAAA8A8AA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rdack11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rdack ) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]) ); @@ -54912,138 +56445,138 @@ loopback_ctrl LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]) ); LUT3 #( .INIT ( 8'h20 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]) ); LUT6 #( .INIT ( 64'hF9F9F9F9A9298909 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1532 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1533 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1534 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1531 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ) ); LUT5 #( .INIT ( 32'h00800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out221 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5631 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]), .I3 @@ -55052,6 +56585,17 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ) ); + LUT6 #( + .INIT ( 64'h0888888888888888 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[5]_b_lock_AND_96_o ) + ); LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1412 ( @@ -55060,7 +56604,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [26]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5663 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ) @@ -55068,12 +56612,12 @@ loopback_ctrl LUT5 #( .INIT ( 32'hFFFFFDFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT2111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3750 ) , .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ) ); @@ -55087,7 +56631,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5646 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ) @@ -55102,7 +56646,7 @@ loopback_ctrl .I4 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3718 ) , .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ) @@ -55121,20 +56665,20 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h00000008 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_377_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I1 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_377_o ) ); LUT5 #( .INIT ( 32'h00000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -55144,7 +56688,7 @@ loopback_ctrl .INIT ( 32'h00000800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), @@ -55153,7 +56697,7 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), @@ -55163,7 +56707,7 @@ loopback_ctrl LUT3 #( .INIT ( 8'h10 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(reset), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ) @@ -55185,21 +56729,21 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0001000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ) ); LUT4 #( .INIT ( 16'h91A2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1280 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In1 ) ); LUT5 #( @@ -55210,7 +56754,7 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), - .O(N262) + .O(N260) ); LUT6 #( .INIT ( 64'h9696966996699696 )) @@ -55352,7 +56896,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [25]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [64]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5550 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5791 ) ); LUT6 #( @@ -55365,7 +56909,7 @@ loopback_ctrl .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [7]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [46]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5551 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5792 ) ); LUT6 #( @@ -55401,7 +56945,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ), - .O(N248) + .O(N246) ); LUT6 #( .INIT ( 64'hFFFFA7F7FFFFFFFF )) @@ -55412,7 +56956,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]), - .O(N264) + .O(N262) ); LUT6 #( .INIT ( 64'hFFFFFFFFBFFFFFFF )) @@ -55423,15 +56967,15 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]), - .O(N394) + .O(N392) ); LUT3 #( .INIT ( 8'h10 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_311_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1280 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_311_o ) ); LUT5 #( .INIT ( 32'h88880008 )) @@ -55439,26 +56983,26 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5576 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]), - .O(N589) + .O(N587) ); LUT3 #( .INIT ( 8'hFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ), .I2(reset), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_393_o ) ); LUT3 #( .INIT ( 8'hFE )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ), .I2(reset), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_394_o ) ); LUT6 #( @@ -55606,24 +57150,24 @@ loopback_ctrl ); LUT5 #( .INIT ( 32'h00101000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o ) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_519_o1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_519_o ) ); LUT6 #( .INIT ( 64'hAAAAAAAA88808088 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fullg ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_5769 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3316 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_6004 ) ); LUT6 #( .INIT ( 64'h7007522525520770 )) @@ -56101,64 +57645,48 @@ loopback_ctrl LUT6 #( .INIT ( 64'h5155555555555555 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5486 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5727 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ), .O(N622) ); LUT5 #( .INIT ( 32'h00000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/Mmux_q[0]_d[0]_MUX_691_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/Mmux_q[0]_d[0]_MUX_695_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I4 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_691_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_695_o ) ); LUT5 #( .INIT ( 32'h00000800 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/Mmux_q[0]_d[0]_MUX_691_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/Mmux_q[0]_d[0]_MUX_695_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I4 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_691_o ) - ); - LUT6 #( - .INIT ( 64'h1000100010101000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51 ( - .I0 -(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]), - .I3 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ), - .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ) -, - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_695_o ) ); LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT11 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<0> ) @@ -56169,10 +57697,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT21 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<1> ) @@ -56183,10 +57711,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT31 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<2> ) @@ -56197,10 +57725,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT41 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<3> ) @@ -56211,10 +57739,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT51 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<4> ) @@ -56225,10 +57753,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT61 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<5> ) @@ -56239,10 +57767,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT71 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<6> ) @@ -56253,10 +57781,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT81 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<7> ) @@ -56267,10 +57795,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT91 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<8> ) @@ -56281,10 +57809,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT101 ( .I0 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<9> ) @@ -56293,11 +57821,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<0> ) @@ -56306,11 +57834,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<1> ) @@ -56319,11 +57847,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<2> ) @@ -56332,11 +57860,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<3> ) @@ -56345,11 +57873,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<4> ) @@ -56358,11 +57886,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<5> ) @@ -56371,11 +57899,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<6> ) @@ -56384,11 +57912,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<7> ) @@ -56397,11 +57925,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<8> ) @@ -56410,11 +57938,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h0000000000800000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<9> ) @@ -56426,8 +57954,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<0> ) @@ -56439,8 +57967,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<10> ) @@ -56452,8 +57980,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<11> ) @@ -56465,8 +57993,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<12> ) @@ -56478,8 +58006,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<13> ) @@ -56491,8 +58019,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<14> ) @@ -56504,8 +58032,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<15> ) @@ -56517,8 +58045,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<1> ) @@ -56530,8 +58058,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<2> ) @@ -56543,8 +58071,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<3> ) @@ -56556,8 +58084,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<4> ) @@ -56569,8 +58097,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<5> ) @@ -56582,8 +58110,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<6> ) @@ -56595,8 +58123,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<7> ) @@ -56608,8 +58136,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<8> ) @@ -56621,8 +58149,8 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<9> ) @@ -56633,9 +58161,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<0> ) @@ -56646,9 +58174,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<10> ) @@ -56659,9 +58187,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<11> ) @@ -56672,9 +58200,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<12> ) @@ -56685,9 +58213,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<13> ) @@ -56698,9 +58226,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<14> ) @@ -56711,9 +58239,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<15> ) @@ -56724,9 +58252,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<1> ) @@ -56737,9 +58265,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<2> ) @@ -56750,9 +58278,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<3> ) @@ -56763,9 +58291,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<4> ) @@ -56776,9 +58304,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<5> ) @@ -56789,9 +58317,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<6> ) @@ -56802,9 +58330,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<7> ) @@ -56815,9 +58343,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<8> ) @@ -56828,9 +58356,9 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<9> ) @@ -56841,10 +58369,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<0> ) @@ -56854,10 +58382,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<10> ) @@ -56867,10 +58395,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<11> ) @@ -56880,10 +58408,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<12> ) @@ -56893,10 +58421,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<13> ) @@ -56906,10 +58434,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<14> ) @@ -56919,10 +58447,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<15> ) @@ -56932,10 +58460,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<1> ) @@ -56945,10 +58473,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<2> ) @@ -56958,10 +58486,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<3> ) @@ -56971,10 +58499,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<4> ) @@ -56984,10 +58512,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<5> ) @@ -56997,10 +58525,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<6> ) @@ -57010,10 +58538,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<7> ) @@ -57023,10 +58551,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<8> ) @@ -57036,10 +58564,10 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1752 ), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<9> ) @@ -57047,11 +58575,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<0> ) @@ -57060,11 +58588,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<10> ) @@ -57073,11 +58601,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<11> ) @@ -57086,11 +58614,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<12> ) @@ -57099,11 +58627,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<13> ) @@ -57112,11 +58640,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<14> ) @@ -57125,11 +58653,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<15> ) @@ -57138,11 +58666,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<1> ) @@ -57151,11 +58679,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<2> ) @@ -57164,11 +58692,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<3> ) @@ -57177,11 +58705,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<4> ) @@ -57190,11 +58718,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<5> ) @@ -57203,11 +58731,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<6> ) @@ -57216,11 +58744,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<7> ) @@ -57229,11 +58757,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<8> ) @@ -57242,11 +58770,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'h2000000000000000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1753 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<9> ) @@ -57256,9 +58784,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT17 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<0> ) @@ -57268,9 +58796,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT21 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<10> ) @@ -57280,9 +58808,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT31 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<11> ) @@ -57291,10 +58819,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<12> ) @@ -57303,10 +58831,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<13> ) @@ -57316,9 +58844,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT61 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<14> ) @@ -57327,10 +58855,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<15> ) @@ -57340,9 +58868,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT81 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<1> ) @@ -57351,10 +58879,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<2> ) @@ -57364,9 +58892,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT101 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<3> ) @@ -57375,10 +58903,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<4> ) @@ -57387,10 +58915,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<5> ) @@ -57400,9 +58928,9 @@ loopback_ctrl .INIT ( 32'hEEFEEEEE )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT131 ( .I0(reset), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<6> ) @@ -57411,10 +58939,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<7> ) @@ -57423,10 +58951,10 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<8> ) @@ -57435,110 +58963,143 @@ loopback_ctrl LUT5 #( .INIT ( 32'h00000008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<9> ) ); + LUT6 #( + .INIT ( 64'h0000000000000002 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ) + ); + LUT6 #( + .INIT ( 64'h0001000000000000 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o<15>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ) + ); LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT11 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<0> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<0> ) ); + LUT6 #( + .INIT ( 64'h1551155155551551 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<0>11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0139 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt ) + ); LUT6 #( .INIT ( 64'hFFFF04FFFFFFFFFF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ), .I5 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3832 ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5411 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5652 ) ); LUT6 #( - .INIT ( 64'hAAAAAAAAAAAABAAA )) + .INIT ( 64'hAAAAAAAAAAAAAAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT206_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_465 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), - .O(N392) + .O(N390) ); LUT6 #( - .INIT ( 64'hAAAAAAAAAAAABAAA )) + .INIT ( 64'hAAAAAAAAAAAAAAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<3>_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), .O(N12) ); LUT6 #( - .INIT ( 64'hAAAAAAAAAAAABAAA )) + .INIT ( 64'hAAAAAAAAAAAAAAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<4>_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), .O(N14) ); LUT6 #( - .INIT ( 64'hAAAAAAAAAAAABAAA )) + .INIT ( 64'hAAAAAAAAAAAAAAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<6>_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), .O(N16) ); LUT6 #( - .INIT ( 64'hAAAAAAAAAAAABAAA )) + .INIT ( 64'hAAAAAAAAAAAAAAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<8>_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), .O(N18) ); LUT6 #( - .INIT ( 64'hAAAAAAAAAAAABAAA )) + .INIT ( 64'hAAAAAAAAAAAAAAEA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<2>_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), .O(N20) ); LUT6 #( @@ -57548,8 +59109,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]), .O(N22) ); @@ -57560,8 +59121,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]), .O(N24) ); @@ -57572,8 +59133,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]), .O(N26) ); @@ -57584,8 +59145,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]), .O(N28) ); @@ -57596,8 +59157,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]), .O(N30) ); @@ -57608,8 +59169,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]), .O(N32) ); @@ -57620,8 +59181,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]), .O(N34) ); @@ -57632,8 +59193,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]), .O(N36) ); @@ -57644,8 +59205,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]), .O(N38) ); @@ -57656,8 +59217,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]), .O(N40) ); @@ -57668,8 +59229,8 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I2 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]), .O(N42) ); @@ -57685,7 +59246,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [0]), - .O(N198) + .O(N200) ); LUT6 #( .INIT ( 64'h51555555FFFFFFFF )) @@ -57699,7 +59260,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [5]), - .O(N200) + .O(N202) ); LUT6 #( .INIT ( 64'h51555555FFFFFFFF )) @@ -57713,16 +59274,16 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [6]), - .O(N202) + .O(N204) ); LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<1> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<1> ) @@ -57731,11 +59292,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<15> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [15]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<15> ) @@ -57744,11 +59305,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<14> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [14]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<14> ) @@ -57757,11 +59318,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<13> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [13]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<13> ) @@ -57770,11 +59331,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<12> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [12]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<12> ) @@ -57783,11 +59344,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<11> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [11]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<11> ) @@ -57796,11 +59357,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<10> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [10]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<10> ) @@ -57809,11 +59370,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<9> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [9]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<9> ) @@ -57822,11 +59383,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<8> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [8]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<8> ) @@ -57835,11 +59396,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<7> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [7]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<7> ) @@ -57848,11 +59409,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<6> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<6> ) @@ -57861,11 +59422,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<5> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<5> ) @@ -57874,11 +59435,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<4> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [4]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<4> ) @@ -57887,11 +59448,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<3> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<3> ) @@ -57900,11 +59461,11 @@ loopback_ctrl LUT6 #( .INIT ( 64'hEEEEEFEE44444044 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4471 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<2> ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4703 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4750 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4751 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<2> ) @@ -57916,10 +59477,10 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ), .I1 (\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5764 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5998 ) ); LUT6 #( .INIT ( 64'hEAAAAAAAAAAAAAAA )) @@ -57939,9 +59500,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT17 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<0> ) @@ -57950,9 +59511,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT21 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<10> ) @@ -57961,9 +59522,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT31 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<11> ) @@ -57972,9 +59533,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT41 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<12> ) @@ -57983,9 +59544,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT51 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<13> ) @@ -57994,9 +59555,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT61 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<14> ) @@ -58005,9 +59566,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT71 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<15> ) @@ -58016,9 +59577,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT81 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<1> ) @@ -58027,9 +59588,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT91 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<2> ) @@ -58038,9 +59599,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT101 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<3> ) @@ -58049,9 +59610,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT111 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<4> ) @@ -58060,9 +59621,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT121 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<5> ) @@ -58071,9 +59632,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT131 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<6> ) @@ -58082,9 +59643,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT141 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<7> ) @@ -58093,9 +59654,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT151 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<8> ) @@ -58104,9 +59665,9 @@ loopback_ctrl LUT4 #( .INIT ( 16'h0800 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT161 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<9> ) @@ -58116,15 +59677,15 @@ loopback_ctrl .INIT ( 32'h4E444444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5765 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5999 ) ); LUT5 #( .INIT ( 32'h00800000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o1 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]), .I2 @@ -58132,7 +59693,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_375_o ) ); LUT6 #( @@ -58150,25 +59711,25 @@ loopback_ctrl .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5711 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 ), - .O(N666) + .O(N670) ); LUT6 #( .INIT ( 64'hFFFFFFFFEAAA2AAA )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set ( - .I0(N666), + .I0(N670), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11321 ), - .I5(N392), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5693 ) + .I5(N390), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5927 ) ); LUT6 #( .INIT ( 64'h000100050003000F )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT324_SW0 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_4974 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_5215 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [48]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ), @@ -58176,19 +59737,19 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ), .I5 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ), - .O(N668) + .O(N672) ); LUT6 #( .INIT ( 64'h0F0F0D000F0F0D0D )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT324 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5589 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5823 ) , - .I5(N668), + .I5(N672), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<38> ) ); LUT4 #( @@ -58200,7 +59761,7 @@ loopback_ctrl (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ), - .O(N670) + .O(N674) ); LUT6 #( .INIT ( 64'h00AA000000FB00F3 )) @@ -58208,30 +59769,30 @@ loopback_ctrl .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [28]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4468 ), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4915 ) , - .I5(N670), + .I5(N674), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<26> ) ); LUT6 #( .INIT ( 64'h0001000000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o<15>1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o<15>1 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1768 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ) ); LUT5 #( .INIT ( 32'hFFFF0008 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3724 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]), @@ -58257,14 +59818,14 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re1 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ), .I1 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1762 ) , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ), .I3 (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ) , - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ) ); LUT6 #( @@ -58280,30 +59841,30 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5568 ) ); LUT3 #( .INIT ( 8'hF2 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5674 ) + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1707 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1281 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5908 ) ); LUT4 #( .INIT ( 16'h08FF )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_SW0 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3727 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5325 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5566 ), .O(N624) ); LUT6 #( .INIT ( 64'hFFFFFFFFFDFDFDA8 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084<4>1 ( .I0 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ), +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_360_o ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3]), @@ -58393,112 +59954,135 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_we ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_5766 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_6000 ) ); LUT6 #( .INIT ( 64'h02000200AAAA0200 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1 ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1992 ), .I1(reset), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1993 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1757 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_5800 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1793 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_6035 ) ); LUT6 #( .INIT ( 64'h2222262222222222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3636 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), .I2(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5677 ) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5911 ) ); LUT6 #( .INIT ( 64'h2222622222222222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3637 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ), .I4(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5678 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5912 ) ); LUT6 #( .INIT ( 64'h2222622222222222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3638 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ), .I4(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5679 ) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3636 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5913 ) ); LUT5 #( .INIT ( 32'h22262222 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3656 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5680 ) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5914 ) ); LUT5 #( .INIT ( 32'h46444444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5681 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3657 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5915 ) ); LUT5 #( .INIT ( 32'h46444444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5682 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3658 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_537 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_590 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3656 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5916 ) + ); + LUT6 #( + .INIT ( 64'h2002000020022002 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_slip_int11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4663 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0015 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ) + ); + LUT6 #( + .INIT ( 64'h0000200220022002 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT11 ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4664 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/n0034 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_810_o ), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[1]_sh_invalid_cnt[3]_wide_mux_50_OUT<0> ) ); LUT6 #( .INIT ( 64'h0000002000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/Mmux_q[0]_d[0]_MUX_691_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/Mmux_q[0]_d[0]_MUX_695_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_691_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_695_o ) ); LUT6 #( .INIT ( 64'h0000002000000000 )) - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/Mmux_q[0]_d[0]_MUX_691_o11 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/Mmux_q[0]_d[0]_MUX_695_o11 ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1994 ), .I4(reset), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_691_o ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_695_o ) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state23 ( - .I0(N672), - .I1(N673), + .I0(N676), + .I1(N677), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]) ); @@ -58507,37 +60091,37 @@ loopback_ctrl \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state23_F ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .O(N672) + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .O(N676) ); LUT6 #( .INIT ( 64'h0004000400040404 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state23_G ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), - .O(N673) + .O(N677) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state33 ( - .I0(N674), - .I1(N675), + .I0(N678), + .I1(N679), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]) ); LUT5 #( .INIT ( 32'hFFFF882A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state33_F ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5309 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), - .O(N674) + .O(N678) ); LUT6 #( .INIT ( 64'hFFFFFFFFFFA8FFFF )) @@ -58546,13 +60130,13 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ), - .O(N675) + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5310 ), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5308 ), + .O(N679) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code73 ( - .I0(N676), - .I1(N677), + .I0(N680), + .I1(N681), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [51]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 ) ); @@ -58565,7 +60149,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]), - .O(N676) + .O(N680) ); LUT6 #( .INIT ( 64'h4004040404000004 )) @@ -58576,11 +60160,11 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]), - .O(N677) + .O(N681) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code13 ( - .I0(N678), - .I1(N679), + .I0(N682), + .I1(N683), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code12 ) ); @@ -58593,7 +60177,7 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]), - .O(N678) + .O(N682) ); LUT6 #( .INIT ( 64'h4004040404000004 )) @@ -58604,39 +60188,39 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]), - .O(N679) + .O(N683) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In2 ( - .I0(N680), - .I1(N681), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ), + .I0(N684), + .I1(N685), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1708 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In ) ); LUT6 #( .INIT ( 64'hFFFFFFFF66764454 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In2_F ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1676 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1709 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1711 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1375 ), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rdack ), - .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .O(N680) + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .O(N684) ); LUT5 #( .INIT ( 32'hFFFF082A )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In2_G ( - .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ), + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1710 ), .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [17]), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ), - .O(N681) + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1280 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1397 ), + .O(N685) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97 ( - .I0(N682), - .I1(N683), + .I0(N686), + .I1(N687), .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]), .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT96 ) @@ -58649,7 +60233,7 @@ loopback_ctrl .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [2]), - .O(N682) + .O(N686) ); LUT5 #( .INIT ( 32'hFBEA5140 )) @@ -58659,44 +60243,75 @@ loopback_ctrl .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [2]), .I4 -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5183 ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5424 ) , - .O(N683) + .O(N687) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In3 ( - .I0(N684), - .I1(N685), - .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ), + .I0(N688), + .I1(N689), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_3128 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In ) ); LUT5 #( .INIT ( 32'h46444444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In3_F ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), - .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ), - .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5312 ) + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_3126 ), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5553 ) , .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), - .O(N684) + .O(N688) ); LUT5 #( .INIT ( 32'h4E444444 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In3_G ( .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ), - .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_3127 ), .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), - .O(N685) + .O(N689) + ); + MUXF7 + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2>1 ( + .I0(N690), + .I1(N691), + .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [2]), + .O +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> ) + + ); + LUT6 #( + .INIT ( 64'h9999009090990099 )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2>1_F ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [1]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0]), + .O(N690) + ); + LUT6 #( + .INIT ( 64'hFFECECFFFFF8F8FF )) + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2>1_G ( + .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0]), + .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1]), + .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [1]), + .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2]), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]), + .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0]), + .O(N691) ); MUXF7 \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1177 ( - .I0(N686), - .I1(N687), + .I0(N692), + .I1(N693), .S (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ) , - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5473 ) + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5714 ) ); LUT6 #( .INIT ( 64'hFFFFFFFF11111110 )) @@ -58709,9 +60324,9 @@ loopback_ctrl , .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 ), .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1173 ), - .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ), + .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5711 ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ), - .O(N686) + .O(N692) ); LUT6 #( .INIT ( 64'hFFFFFFFF40000000 )) @@ -58724,27 +60339,27 @@ loopback_ctrl .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27]), .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ), .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ), - .O(N687) + .O(N693) ); INV - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0>_INV_0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_lut<0>_INV_0 ( .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_135_OUT_lut<0> ) ); INV - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0>_INV_0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_lut<0>_INV_0 ( .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_129_OUT_lut<0> ) ); INV - \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0>_INV_0 ( + \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_lut<0>_INV_0 ( .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]), .O -(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> ) +(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_132_OUT_lut<0> ) ); INV @@ -58846,9 +60461,9 @@ loopback_ctrl .O (\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ) ); - INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o1_INV_0 ( - .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o ) + INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_317_o1_INV_0 ( + .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2203 ), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_317_o ) ); INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<0>11_INV_0 ( .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]), @@ -58863,9 +60478,13 @@ loopback_ctrl .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [0]) ); INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en1_INV_0 ( - .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ), + .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_874 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ) ); + INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert1_INV_0 ( + .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]), + .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert ) + ); INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_rd_addr_xor<0>11_INV_0 ( .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]), @@ -58876,16 +60495,12 @@ loopback_ctrl .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [0]) ); - INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv1_INV_0 ( - .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ), - .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ) - ); INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv1_INV_0 ( - .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ), + .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_540 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ) ); INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst1_INV_0 ( - .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ), + .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_539 ), .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ) ); INV \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv1_INV_0 ( @@ -58967,39 +60582,39 @@ loopback_ctrl SRLC16E #( .INIT ( 16'h0000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1 ( - .A0(NlwRenamedSig_OI_drp_dwe), - .A1(NlwRenamedSig_OI_drp_dwe), - .A2(NlwRenamedSig_OI_drp_dwe), - .A3(NlwRenamedSig_OI_drp_dwe), + .A0(NlwRenamedSig_OI_loopback_ctrl[0]), + .A1(NlwRenamedSig_OI_loopback_ctrl[0]), + .A2(NlwRenamedSig_OI_loopback_ctrl[0]), + .A3(NlwRenamedSig_OI_loopback_ctrl[0]), .CE(N0), .CLK(dclk), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_5968 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2202 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_6207 ), .Q15(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_Q15_UNCONNECTED ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2_1 ( .C(dclk), .CE(N0), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_5968 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_6207 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]) ); SRLC16E #( .INIT ( 16'h0000 )) \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0 ( - .A0(NlwRenamedSig_OI_drp_dwe), - .A1(NlwRenamedSig_OI_drp_dwe), - .A2(NlwRenamedSig_OI_drp_dwe), - .A3(NlwRenamedSig_OI_drp_dwe), + .A0(NlwRenamedSig_OI_loopback_ctrl[0]), + .A1(NlwRenamedSig_OI_loopback_ctrl[0]), + .A2(NlwRenamedSig_OI_loopback_ctrl[0]), + .A3(NlwRenamedSig_OI_loopback_ctrl[0]), .CE(N0), .CLK(dclk), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ), - .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_5969 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2201 ), + .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_6208 ), .Q15(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_Q15_UNCONNECTED ) ); FDE \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2_0 ( .C(dclk), .CE(N0), - .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_5969 ), + .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_6208 ), .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]) ); diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.veo b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.veo index 857f1bbc6..ecaf2037d 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.veo +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.veo @@ -22,7 +22,7 @@ * devices, or systems. Use in such applications are expressly * * prohibited. * * * -* (c) Copyright 1995-2013 Xilinx, Inc. * +* (c) Copyright 1995-2014 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xco b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xco index 4cdbe22fa..461949471 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xco +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version 14.4 -# Date: Tue Jan 29 00:51:49 2013 +# Xilinx Core Generator version 14.7 +# Date: Thu Sep 4 21:43:24 2014 # ############################################################## # diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xise b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xise index 037ad7b91..47397b6ca 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xise +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma.xise @@ -9,10 +9,10 @@ - + - + @@ -55,7 +55,7 @@ - + @@ -339,8 +339,8 @@ - - + + diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/doc/pg068-ten-gig-eth-pcs-pma.pdf b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/doc/pg068-ten-gig-eth-pcs-pma.pdf index b71b80d3e..152e4b9c3 100644 Binary files a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/doc/pg068-ten-gig-eth-pcs-pma.pdf and b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/doc/pg068-ten-gig-eth-pcs-pma.pdf differ diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v index 8f608bcaf..efc162792 100755 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v @@ -50,11 +50,9 @@ //***********************************Entity Declaration******************************* module ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE ( - // IJB. Remove IBUFDS_GTE2 from 10G PHY hierarchy so that it can be shared. - // - //input wire Q1_CLK0_GTREFCLK_PAD_N_IN, - //input wire Q1_CLK0_GTREFCLK_PAD_P_IN, - //output wire Q1_CLK0_GTREFCLK_OUT, + input wire Q1_CLK0_GTREFCLK_PAD_N_IN, + input wire Q1_CLK0_GTREFCLK_PAD_P_IN, + output wire Q1_CLK0_GTREFCLK_OUT, output GT0_TXUSRCLK_OUT, output GT0_TXUSRCLK2_OUT, @@ -78,7 +76,7 @@ module ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE wire gt0_txoutclk_i; wire gt0_rxoutclk_i; -// wire q1_clk0_gtrefclk; + wire q1_clk0_gtrefclk; wire gt0_txusrclk_i; wire gt0_rxusrclk_i; @@ -91,10 +89,9 @@ module ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE assign gt0_txoutclk_i = GT0_TXOUTCLK_IN; assign gt0_rxoutclk_i = GT0_RXOUTCLK_IN; -// assign Q1_CLK0_GTREFCLK_OUT = q1_clk0_gtrefclk; + assign Q1_CLK0_GTREFCLK_OUT = q1_clk0_gtrefclk; //IBUFDS_GTE2 -/* -----\/----- EXCLUDED -----\/----- IBUFDS_GTE2 ibufds_instQ1_CLK0 ( .O (q1_clk0_gtrefclk), @@ -103,7 +100,6 @@ module ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE .I (Q1_CLK0_GTREFCLK_PAD_P_IN), .IB (Q1_CLK0_GTREFCLK_PAD_N_IN) ); - -----/\----- EXCLUDED -----/\----- */ BUFG txoutclk_bufg0_i ( diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v index 569c2ec3c..4dd920312 100755 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v @@ -52,11 +52,11 @@ //***************************** Entity Declaration **************************** -(* CORE_GENERATION_INFO = "gtwizard_10gbaser,gtwizard_v2_3,{protocol_file=10GBASE-R}" *) module ten_gig_eth_pcs_pma_gtwizard_10gbaser # +module ten_gig_eth_pcs_pma_gtwizard_10gbaser # ( // Simulation attributes parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset - parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C, + parameter RX_DFE_KL_CFG2_IN = 32'h301148AC, parameter PMA_RSV_IN = 32'h001E7080, parameter SIM_VERSION = "4.0" ) diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v index 6638ffefa..8daaf45fd 100755 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v @@ -56,8 +56,8 @@ module ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT # ( // Simulation attributes parameter GT_SIM_GTRESET_SPEEDUP = "false", // Set to 1 to speed up sim reset; - parameter RX_DFE_KL_CFG2_IN = 32'h3008E56A, - parameter PMA_RSV_IN = 32'h00000000, + parameter RX_DFE_KL_CFG2_IN = 32'h301148AC, + parameter PMA_RSV_IN = 32'h001E7080, parameter PCS_RSVD_ATTR_IN = 48'h000000000000, parameter SIM_VERSION = ("4.0") ) @@ -195,7 +195,7 @@ module ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT # //----------------RX Byte and Word Alignment Attributes--------------- .ALIGN_COMMA_DOUBLE ("FALSE"), - .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_ENABLE (10'b0001111111), .ALIGN_COMMA_WORD (1), .ALIGN_MCOMMA_DET ("FALSE"), .ALIGN_MCOMMA_VALUE (10'b1010000011), @@ -317,6 +317,7 @@ module ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT # .RX_DEFER_RESET_BUF_EN ("TRUE"), //---------------------CDR Attributes------------------------- + .RXCDR_CFG (72'h0b000023ff10400020), .RXCDR_FR_RESET_ON_EIDLE (1'b0), .RXCDR_HOLD_DURING_EIDLE (1'b0), diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v index e15946fec..862d6e9f5 100755 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v @@ -58,10 +58,8 @@ module ten_gig_eth_pcs_pma_block # parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "FALSE" ) ( -// input refclk_n, -// input refclk_p, - input refclk156, - input refclk156_buf, + input refclk_n, + input refclk_p, output clk156, output txclk322, output rxclk322, @@ -237,20 +235,15 @@ module ten_gig_eth_pcs_pma_block # .loopback_ctrl(gt0_loopback_i)); // Make the GT Wizard output connect to the core and top level i/f - //assign Q1_CLK0_GTREFCLK_PAD_N_IN = refclk_n; - //assign Q1_CLK0_GTREFCLK_PAD_P_IN = refclk_p; + assign Q1_CLK0_GTREFCLK_PAD_N_IN = refclk_n; + assign Q1_CLK0_GTREFCLK_PAD_P_IN = refclk_p; wire gt0_txusrclk2_i; wire gt0_rxusrclk2_i; wire gt0_drpclk_i; wire clkfbout; - - // - // Single ended 156MHz reference clock brought in from upper hierarchy now. - // - wire q1_clk0_refclk_i = refclk156; - - wire q1_clk0_refclk_i_bufh = refclk156_buf; + wire q1_clk0_refclk_i; + wire q1_clk0_refclk_i_bufh; assign txclk322 = gt0_txusrclk2_i; assign rxclk322 = gt0_rxusrclk2_i; @@ -804,11 +797,9 @@ module ten_gig_eth_pcs_pma_block # // As generated by the GT Wizard - cut from _top level in eg design dir ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE gt_usrclk_source ( - // IJB. Remove IBUFDS_GTE2 from 10G PHY hierarchy so that it can be shared. - // - // .Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN), - // .Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN), - // .Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i), + .Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN), + .Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN), + .Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i), .GT0_TXUSRCLK_OUT (gt0_txusrclk_i), .GT0_TXUSRCLK2_OUT (gt0_txusrclk2_i), @@ -849,14 +840,12 @@ module ten_gig_eth_pcs_pma_block # .LOCKED(mmcm_locked) ); -/* -----\/----- EXCLUDED -----\/----- - BUFG bufg_inst + BUFHCE bufh_inst ( - // .CE (tied_to_vcc_i), + .CE (tied_to_vcc_i), .I (q1_clk0_refclk_i), .O (q1_clk0_refclk_i_bufh) ); - -----/\----- EXCLUDED -----/\----- */ BUFG clk156_bufg_inst ( diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf deleted file mode 100644 index 3b023bfb3..000000000 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf +++ /dev/null @@ -1,126 +0,0 @@ -## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. - -####################################################################### -# Clock frequencies/periods and clock management # -# # -####################################################################### -NET "*sfp_clk" TNM_NET="refclk"; - -TIMESPEC "TS_refclk" = PERIOD "refclk" 6400 ps; - -NET "*clk156_buf*" TNM_NET="clk156"; - -TIMESPEC "TS_clk156" = PERIOD "clk156" 6400 ps; - -NET "*gt0_rxoutclk_i" TNM_NET="rxoutclk"; - -TIMESPEC "TS_rxoutclk" = PERIOD "rxoutclk" 3103 ps; - -NET "*gt0_txoutclk_i" TNM_NET="txoutclk"; - -TIMESPEC "TS_txoutclk" = PERIOD "txoutclk" 3103 ps; - -NET "*txclk322" TNM_NET="txclk322"; - -TIMESPEC "TS_txclk322" = PERIOD "txclk322" 3103 ps; - -NET "*rxclk322" TNM_NET="rxusrclk2"; - -TIMESPEC "TS_rxusrclk2" = PERIOD "rxusrclk2" 3103 ps; - -NET "*rxusrclk2_en156*" TNM_NET = FFS "rxusrclk_en_grp"; - -TIMESPEC "TS_rx_multiclk" = FROM "rxusrclk_en_grp" to "rxusrclk_en_grp" TS_rxusrclk2*2; - -NET "*dclk_buf" TNM_NET="dclk"; - -TIMESPEC "TS_dclk" = PERIOD "dclk" TS_clk156*2; - -# Edit these constraints to select the correct transceiver for your design -#INST *gtxe2_i LOC=GTXE2_CHANNEL_X0Y12; -#INST *gtxe2_i LOC=GTXE2_CHANNEL_X0Y0; -#INST "*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0"; -# IJB Experimental dual 10G declaration -#INST "*ten_gig_eth_pcs_pma_b250_top_port0*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y0; -#INST "*ten_gig_eth_pcs_pma_b250_top_port0*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0"; -#INST "ten_gig_eth_pcs_pma_b250_top_port0/ten_gig_eth_pcs_pma_block/gtwizard_10gbaser_i/gtxe2_i" LOC=GTXE2_CHANNEL_X0Y0; -#INST "ten_gig_eth_pcs_pma_b250_top_port0/ten_gig_eth_pcs_pma_block/gtwizard_10gbaser_i/gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0"; -#INST "ten_gig_eth_pcs_pma_b250_top_port1/ten_gig_eth_pcs_pma_block/gtwizard_10gbaser_i/gtxe2_i" LOC=GTXE2_CHANNEL_X0Y4; -#INST "ten_gig_eth_pcs_pma_b250_top_port1/ten_gig_eth_pcs_pma_block/gtwizard_10gbaser_i/gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y1"; -# JAB moved this to individual port ucfs in top level -#INST "*port0/*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y0; -#INST "*port0/*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0"; -#INST "*port1/*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y4; -#INST "*port1/*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y1"; - - - -NET "*cable_pull_reset" MAXDELAY = 2.0 ns; -NET "*cable_unpull_reset" MAXDELAY = 2.0 ns; - -################################################################## -# Elastic Buffer-related constraints # -################################################################## -NET "*elastic_buffer_i*rd_truegray" MAXDELAY = 6.0 ns; -NET "*elastic_buffer_i?can_insert_wra" TIG; -NET "*wr_gray*" MAXDELAY = 6.0 ns; -NET "*rd_lastgray*" MAXDELAY = 6.0 ns; -################################################################### - -TIMESPEC "TS_rxusrclk2_to_clk156" = FROM rxusrclk2 TO clk156 TIG; - -TIMESPEC "TS_rxusrclk2_to_txclk322" = FROM rxusrclk2 TO txclk322 TIG; - -TIMESPEC "TS_clk156_to_txclk322" = FROM clk156 TO txclk322 TIG; - -TIMESPEC "TS_clk156_to_refclk" = FROM clk156 TO refclk TIG; - -TIMESPEC "TS_txclk322_to_clk156" = FROM txclk322 TO clk156 TIG; - -TIMESPEC "TS_rxusrclk2_to_refclk" = FROM rxusrclk2 TO refclk TIG; - - diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v deleted file mode 100644 index 446fb035b..000000000 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v +++ /dev/null @@ -1,276 +0,0 @@ -//----------------------------------------------------------------------------- -// Title : Example Design level wrapper -// Project : 10GBASE-R -//----------------------------------------------------------------------------- -// File : ten_gig_eth_pcs_pma_example_design.v -//----------------------------------------------------------------------------- -// Description: This file is a wrapper for the 10GBASE-R core; it contains all -// of the clock buffers required for implementing the block level -//----------------------------------------------------------------------------- -// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - -// -// NOTE!: Modified example design to create x300 top level -// for this IP block. -// -module ten_gig_eth_pcs_pma_x300_top - ( -// input refclk_p, -// input refclk_n, - input refclk156, - input refclk156_buf, - output clk156, - input reset, - input [63 : 0] xgmii_txd, - input [7 : 0] xgmii_txc, - output reg [63 : 0] xgmii_rxd, - output reg [7 : 0] xgmii_rxc, -// output xgmii_rx_clk, //IJB - output txp, - output txn, - input rxp, - input rxn, - input mdc, - input mdio_in, - output reg mdio_out, - output reg mdio_tri, - input [4 : 0] prtad, - output [7:0] core_status, - output resetdone, - input signal_detect, - input tx_fault, - output tx_disable); - - // Signal declarations - wire clk156; - - // Sync the global reset to the relevant clocks - reg core_reset_tx; - reg core_reset_rx; - reg txreset322; - reg rxreset322; - reg dclk_reset; - - reg core_reset_tx_tmp; - reg core_reset_rx_tmp; - reg txreset322_tmp; - reg rxreset322_tmp; - reg dclk_reset_tmp; - - (* KEEP = "true" *) - wire txclk322; - wire rxclk322; - wire dclk; - - wire tx_resetdone_int; - wire rx_resetdone_int; - reg [63:0] xgmii_txd_reg; - reg [7:0] xgmii_txc_reg; - wire [63:0] xgmii_rxd_int; - wire [7:0] xgmii_rxc_int; - - wire mdio_out_int; - wire mdio_tri_int; - - assign resetdone = tx_resetdone_int && rx_resetdone_int; - - //synthesis attribute async_reg of core_reset_tx_tmp is "true"; - //synthesis attribute async_reg of core_reset_tx is "true"; - //synthesis attribute async_reg of core_reset_rx_tmp is "true"; - //synthesis attribute async_reg of core_reset_rx is "true"; - always @(posedge reset or posedge clk156) - begin - if(reset) - begin - core_reset_tx_tmp <= 1'b1; - core_reset_tx <= 1'b1; - core_reset_rx_tmp <= 1'b1; - core_reset_rx <= 1'b1; - end - else - begin - // Hold core in reset until everything else is ready... -// IJB. Per AR# 53443 changed these lines: -// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset || -// tx_fault || !(signal_detect) ); - core_reset_tx_tmp <= (!(tx_resetdone_int) || reset); - - core_reset_tx <= core_reset_tx_tmp; -// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || -// tx_fault || !(signal_detect) ); - core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || !(signal_detect)); - - core_reset_rx <= core_reset_rx_tmp; - end - end - - //synthesis attribute async_reg of txreset322_tmp is "true"; - //synthesis attribute async_reg of txreset322 is "true"; - always @(posedge reset or posedge txclk322) - begin - if(reset) - begin - txreset322_tmp <= 1'b1; - txreset322 <= 1'b1; - end - else - begin - txreset322_tmp <= core_reset_tx; - txreset322 <= txreset322_tmp; - end - end - - //synthesis attribute async_reg of rxreset322_tmp is "true"; - //synthesis attribute async_reg of rxreset322 is "true"; - always @(posedge reset or posedge rxclk322) - begin - if(reset) - begin - rxreset322_tmp <= 1'b1; - rxreset322 <= 1'b1; - end - else - begin - rxreset322_tmp <= core_reset_rx; - rxreset322 <= rxreset322_tmp; - end - end - - //synthesis attribute async_reg of dclk_reset_tmp is "true"; - //synthesis attribute async_reg of dclk_reset is "true"; - always @(posedge reset or posedge dclk) - begin - if(reset) - begin - dclk_reset_tmp <= 1'b1; - dclk_reset <= 1'b1; - end - else - begin - dclk_reset_tmp <= core_reset_rx; - dclk_reset <= dclk_reset_tmp; - end - end - - // Add a pipeline to the xmgii_tx inputs, to aid timing closure - always @(posedge clk156) - begin - xgmii_txd_reg <= xgmii_txd; - xgmii_txc_reg <= xgmii_txc; - end - - // Add a pipeline to the xmgii_rx outputs, to aid timing closure - always @(posedge clk156) - begin - xgmii_rxd <= xgmii_rxd_int; - xgmii_rxc <= xgmii_rxc_int; - end - - // Add a pipeline to the mdio outputs, to aid timing closure - // This is safe because the mdio clock is running so slowly - always @(posedge clk156) - begin - mdio_out <= mdio_out_int; - mdio_tri <= mdio_tri_int; - end - - // Instantiate the 10GBASE-R Block Level - - ten_gig_eth_pcs_pma_block # ( - .EXAMPLE_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware - ten_gig_eth_pcs_pma_block - ( -// .refclk_n(refclk_n), -// .refclk_p(refclk_p), - .refclk156(refclk156), - .refclk156_buf(refclk156_buf), - .clk156(clk156), - .txclk322(txclk322), - .rxclk322(rxclk322), - .dclk(dclk), - .areset(reset), - .reset(core_reset_tx), - .rxreset322(rxreset322), - .txreset322(txreset322), - .dclk_reset(dclk_reset), - .xgmii_txd(xgmii_txd_reg), - .xgmii_txc(xgmii_txc_reg), - .xgmii_rxd(xgmii_rxd_int), - .xgmii_rxc(xgmii_rxc_int), - .txp(txp), - .txn(txn), - .rxp(rxp), - .rxn(rxn), - .mdc(mdc), - .mdio_in(mdio_in), - .mdio_out(mdio_out_int), - .mdio_tri(mdio_tri_int), - .prtad(prtad), - .core_status(core_status), - .tx_resetdone(tx_resetdone_int), - .rx_resetdone(rx_resetdone_int), - .signal_detect(signal_detect), - .tx_fault(tx_fault), - .tx_disable(tx_disable)); - - // assign core_clk156_out = clk156; - - // Not needed in X300 -/* -----\/----- EXCLUDED -----\/----- - - ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr( - .Q(xgmii_rx_clk), - .D1(1'b1), - .D2(1'b0), - .C(clk156), - .CE(1'b1), - .R(1'b0), - .S(1'b0)); - - -----/\----- EXCLUDED -----/\----- */ - -endmodule diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_readme.txt b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_readme.txt index c0b15d679..7e206185c 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_readme.txt +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_readme.txt @@ -1,7 +1,7 @@ CHANGE LOG for TEN GIGABIT ETHERNET PCS/PMA -Release Date: December 18, 2012 +Release Date: October 23, 2013 -------------------------------------------------------------------------------- Table of Contents @@ -175,7 +175,22 @@ Table of Contents - CR681628 - Removed unused (reset) logic from Block Level code - CR681627 - Fixed issue of possible deadlock in reset logic - CR681281 - Added TIG constraint to UCF to ignore otherwise unconstrained path + + v2.6 Rev 1 + - CR694301 - Fixed a bug in the management block which had disconnected the + training interface from the DRP interface + - CR694653 - Incorrect version number in core info register - was still at v2.5 + - CR694654 - Incorrect link to v2.5 PG068 in PDF redirect doc + v2.6 Rev 2 + - CR714979 - Incorrect DRP address being used for RX PRBS31 Error Counter in GTH + - CR710726 - Possibility of returning incorrect value from RX PRBS31 Error Counter + - CR710727 - Possibility of corrupting MDIO operations and registers when using RX PRBS31 Error Checking + + v2.6 Rev 3 + - CR679904 (second issue) - PCS Block Lock FSM rewritten to remove the corner-case failure in UNH test 49.3.3 + - Updated GT parameters to Production values + 4.2 Vivado The following issues are resolved in the indicated IP versions: @@ -234,6 +249,12 @@ Table of Contents - CR681628 - Removed unused (reset) logic from Block Level code - CR681627 - Fixed issue of possible deadlock in reset logic + v2.6 Rev 1 + - CR694301 - Fixed a bug in the management block which had disconnected the + training interface from the DRP interface + - CR694653 - Incorrect version number in core info register - was still at v2.5 + - CR694654 - Incorrect link to v2.5 PG068 in PDF redirect doc + 5. KNOWN ISSUES & LIMITATIONS 5.1 ISE @@ -267,6 +288,12 @@ Table of Contents Date By Version Description ================================================================================ +10/23/2013 Xilinx, Inc. 2.6 Rev 3 PCS Block Lock FSM rewritten to remove the + corner-case failure in UNH test 49.3.3 +04/24/2013 Xilinx, Inc. 2.6 Rev 2 Fixed bugs in usage of PRBS31 test features +01/14/2013 Xilinx, Inc. 2.6 Rev 1 Fixed bug in connection from training + interface to GT DRP and fixed Documentation + link. 12/18/2012 Xilinx, Inc. 2.6 Various improvements for new release 10/16/2012 Xilinx, Inc. 2.5 Various improvements for new release, including to Training and AutoNegotiation. @@ -288,7 +315,7 @@ Date By Version Description 8. LEGAL DISCLAIMER - (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. + (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma_flist.txt b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma_flist.txt index 04a16f25c..3bbf77e39 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma_flist.txt +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma_flist.txt @@ -1,4 +1,5 @@ # Output products list for +_xmsgs/pn_parser.xmsgs ten_gig_eth_pcs_pma/doc/pg068-ten-gig-eth-pcs-pma.pdf ten_gig_eth_pcs_pma/example_design/gtx/coregen.cgp ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v diff --git a/fpga/usrp3/top/x300/coregen_chipscope/_xmsgs/pn_parser.xmsgs b/fpga/usrp3/top/x300/coregen_chipscope/_xmsgs/pn_parser.xmsgs deleted file mode 100644 index f905ffcc4..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/_xmsgs/pn_parser.xmsgs +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - -Analyzing Verilog file "/home/ashish/git/fpgadev/usrp3/top/b250/coregen_chipscope/chipscope_ila.v" into library work - - - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/_xmsgs/xst.xmsgs b/fpga/usrp3/top/x300/coregen_chipscope/_xmsgs/xst.xmsgs deleted file mode 100644 index cfed5e533..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/_xmsgs/xst.xmsgs +++ /dev/null @@ -1,666 +0,0 @@ - - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 292: Assignment to logic_1 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_reset_ctrl.vhd" Line 88: Assignment to logic_1 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match.vhd" Line 93: Assignment to logic_0 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gandx.vhd" Line 104: Assignment to logic_1 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gandx.vhd" Line 105: Assignment to logic_0 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gandx_srl_k7.vhd" Line 102: Using initial value '1' for logic_1 since it is never assigned - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7.vhd" Line 64: Using initial value '1' for logic_1 since it is never assigned - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7_slice_rpm_unset.vhd" Line 76: Using initial value '1' for logic_1 since it is never assigned - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7_slice_rpm_unset.vhd" Line 77: Using initial value '0' for logic_0 since it is never assigned - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigcond.vhd" Line 120: Assignment to logic_1 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigcond.vhd" Line 110: Net <iCFG_EN_VEC[15]> does not have a driver. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gand.vhd" Line 83: Assignment to logic_1 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gand.vhd" Line 84: Assignment to logic_0 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_k7_rpm_unset.vhd" Line 156: Using initial value "111111" for srl_remainder since it is never assigned - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_storage.vhd" Line 183: Assignment to logic_1 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_storage.vhd" Line 184: Assignment to logic_0 ignored, since the identifier is never used - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd" Line 68: <ramb18e1> remains a black-box since it has no binding entity. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trace_buffer.vhd" Line 201: Range is empty (null range) - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 383: Net <iCFG_EN_VEC[15]> does not have a driver. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 384: Net <iCFG_EN_16_0> does not have a driver. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 385: Net <iCFG_EN_16_1> does not have a driver. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 279: Net <iCONTROL_IN[17]> does not have a driver. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 283: Net <iATC_CLKIN> does not have a driver. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila.vhd" line 44: Output port <TRIG_OUT> of the instance <U0> is unconnected or connected to loadless signal. - - -Input <TRIG1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG4> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG5> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG6> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG7> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG8> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG9> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG10> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG11> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG12> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG13> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG14> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG15> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" line 1028: Output port <TRIG_OUT> of the instance <I_YES_D.U_ILA> is unconnected or connected to loadless signal. - - -Signal <iCONTROL_IN<17:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -Signal <TRIG_OUT> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -Signal <iATC_CLKIN> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -Input <CONTROL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CONTROL_IN<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CONTROL_IN<10:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CONTROL_IN<17:14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CONTROL_IN<34:20>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <ATC_CLKIN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 601: Output port <HALT> of the instance <U_RST> is unconnected or connected to loadless signal. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 627: Output port <CFG_TSEQ_DOUT> of the instance <U_TRIG> is unconnected or connected to loadless signal. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 790: Output port <CAP_EXT_TRIGOUT> of the instance <U_G2_SQ.U_CAPCTRL> is unconnected or connected to loadless signal. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 874: Output port <WR_TSTAMP_OVERFLOW> of the instance <U_CAPSTOR> is unconnected or connected to loadless signal. - - -Signal <iCFG_EN_VEC> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -Signal <iCFG_EN_16_0> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -Signal <iCFG_EN_16_1> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigger.vhd" line 254: Output port <CFG_DOUT> of the instance <U_TC> is unconnected or connected to loadless signal. - - -Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TRIG_RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_16_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_16_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_combo.vhd" line 160: Output port <CFG_DOUT> of the instance <U_MU> is unconnected or connected to loadless signal. - - -Input <CFG_TSEQ_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Signal <iCFG_EN_VEC> is used but never assigned. This sourceless signal will be automatically connected to value GND. - - -Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CAP_ENDSTATE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <TSTAMP_IN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_16_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_16_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_ctrl_g2_sq.vhd" line 468: Output port <CFG_DOUT> of the instance <I_SRLT_NE_1.U_WHCMPCE> is unconnected or connected to loadless signal. - - -Input <TRIGGER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <REWIND> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CLK_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <RESET_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <WR_TSTAMP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <WR_GAP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <WR_REWIND> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <RD_TSTAMP_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -Input <WR_RESET_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd" line 418: Output port <DOBDO> of the instance <U_RAMB18E1> is unconnected or connected to loadless signal. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd" line 418: Output port <DOPADOP> of the instance <U_RAMB18E1> is unconnected or connected to loadless signal. - - -"/home/jblum/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_k7_ramb18.vhd" line 418: Output port <DOPBDOP> of the instance <U_RAMB18E1> is unconnected or connected to loadless signal. - - -Instance I_B36KGT0.G_RAMB36[127].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[127].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[126].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[126].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[125].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[125].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[124].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[124].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[123].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[123].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[122].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[122].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[121].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[121].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[120].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[120].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[119].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[119].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[118].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[118].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[117].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[117].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[116].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[116].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[115].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[115].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[114].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[114].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[113].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[113].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[112].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[112].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[111].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[111].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[110].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[110].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[109].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[109].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[108].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[108].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[107].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[107].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[106].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[106].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[105].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[105].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[104].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[104].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[103].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[103].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[102].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[102].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[101].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[101].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[100].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[100].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[99].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[99].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[98].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[98].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[97].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[97].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[96].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[96].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[95].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[95].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[94].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[94].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[93].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[93].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[92].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[92].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[91].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[91].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[90].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[90].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[89].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[89].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[88].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[88].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[87].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[87].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[86].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[86].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[85].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[85].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[84].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[84].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[83].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[83].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[82].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[82].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[81].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[81].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[80].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[80].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[79].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[79].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[78].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[78].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[77].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[77].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[76].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[76].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[75].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[75].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[74].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[74].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[73].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[73].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[72].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[72].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[71].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[71].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[70].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[70].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[69].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[69].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[68].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[68].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[67].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[67].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[66].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[66].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[65].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[65].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -Instance I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 - - -HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - - - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.asy b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.asy deleted file mode 100644 index a0153d32c..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.asy +++ /dev/null @@ -1,9 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 chipscope_icon -RECTANGLE Normal 32 32 544 864 -LINE Wide 576 112 544 112 -PIN 576 112 RIGHT 36 -PINATTR PinName control0[35:0] -PINATTR Polarity BOTH - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.ucf b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.ucf deleted file mode 100644 index b83296f8e..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.ucf +++ /dev/null @@ -1,9 +0,0 @@ -NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; -TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; -#Update Constraints -NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; -NET "U0/iSHIFT_OUT" TIG ; -TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; -TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; -TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; -TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.xdc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.xdc deleted file mode 100644 index 903799425..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.constraints/chipscope_icon.xdc +++ /dev/null @@ -1,7 +0,0 @@ -# icon XDC -create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] -set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] -set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 -set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 -set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.gise b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.gise deleted file mode 100644 index a4f878755..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ncf b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ngc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ngc deleted file mode 100644 index 6fd3f1b63..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ucf b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ucf deleted file mode 100644 index b83296f8e..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.ucf +++ /dev/null @@ -1,9 +0,0 @@ -NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; -TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; -#Update Constraints -NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; -NET "U0/iSHIFT_OUT" TIG ; -TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; -TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; -TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; -TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.v b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.v deleted file mode 100644 index aa739062c..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.v +++ /dev/null @@ -1,27 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2013 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 14.4 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_icon.v -// /___/ /\ Timestamp : Wed Jan 30 10:04:14 PST 2013 -// \ \ / \ -// \___\/\___\ -// -// Design Name: Verilog Synthesis Wrapper -/////////////////////////////////////////////////////////////////////////////// -// This wrapper is used to integrate with Project Navigator and PlanAhead - -`timescale 1ns/1ps - -module chipscope_icon( - CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; - - -inout [35 : 0] CONTROL0; - -endmodule diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.veo b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.veo deleted file mode 100644 index b46c0decd..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.veo +++ /dev/null @@ -1,28 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2013 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 14.4 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_icon.veo -// /___/ /\ Timestamp : Wed Jan 30 10:04:14 PST 2013 -// \ \ / \ -// \___\/\___\ -// -// Design Name: ISE Instantiation template -/////////////////////////////////////////////////////////////////////////////// - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -chipscope_icon YourInstanceName ( - .CONTROL0(CONTROL0) // INOUT BUS [35:0] -); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xco b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xco deleted file mode 100644 index 1c998edb1..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Wed Jan 30 18:03:44 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fbg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=chipscope_icon -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=false -CSET number_control_ports=1 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-12-18T02:47:25Z -# END Extra information -GENERATE -# CRC: a8aec264 diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xdc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xdc deleted file mode 100644 index 903799425..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xdc +++ /dev/null @@ -1,7 +0,0 @@ -# icon XDC -create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] -set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] -set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 -set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 -set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xise b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xise deleted file mode 100644 index f3a2e1b32..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_flist.txt b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_flist.txt deleted file mode 100644 index bf55dc492..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_flist.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Output products list for -chipscope_icon.asy -chipscope_icon.constraints/chipscope_icon.ucf -chipscope_icon.constraints/chipscope_icon.xdc -chipscope_icon.gise -chipscope_icon.ngc -chipscope_icon.ucf -chipscope_icon.v -chipscope_icon.veo -chipscope_icon.xco -chipscope_icon.xdc -chipscope_icon.xise -chipscope_icon_flist.txt -chipscope_icon_readme.txt -chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_readme.txt b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_readme.txt deleted file mode 100644 index ff0b1f8c8..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_readme.txt +++ /dev/null @@ -1,45 +0,0 @@ -The following files were generated for 'chipscope_icon' in directory -/home/jblum/coregen_chipscope/ - -XCO file generator: - Generate an XCO file for compatibility with legacy flows. - - * chipscope_icon.xco - -Creates an implementation netlist: - Creates an implementation netlist for the IP. - - * chipscope_icon.constraints/chipscope_icon.ucf - * chipscope_icon.constraints/chipscope_icon.xdc - * chipscope_icon.ngc - * chipscope_icon.ucf - * chipscope_icon.v - * chipscope_icon.veo - * chipscope_icon.xdc - * chipscope_icon_xmdf.tcl - -IP Symbol Generator: - Generate an IP symbol based on the current project options'. - - * chipscope_icon.asy - -Generate ISE subproject: - Create an ISE subproject for use when including this core in ISE designs - - * chipscope_icon.gise - * chipscope_icon.xise - -Deliver Readme: - Readme file for the IP. - - * chipscope_icon_readme.txt - -Generate FLIST file: - Text file listing all of the output files produced when a customized core was - generated in the CORE Generator. - - * chipscope_icon_flist.txt - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_xmdf.tcl b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_xmdf.tcl deleted file mode 100755 index 241f4d5ae..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_icon_xmdf.tcl +++ /dev/null @@ -1,88 +0,0 @@ -# The package naming convention is _xmdf -package provide chipscope_icon_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::chipscope_icon_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::chipscope_icon_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon -} -# ::chipscope_icon_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - - - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.asy b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.asy deleted file mode 100644 index 1ec169765..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.asy +++ /dev/null @@ -1,21 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 chipscope_ila -RECTANGLE Normal 32 32 288 704 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName control[35:0] -PINATTR Polarity IN -LINE Normal 0 112 32 112 -PIN 0 112 LEFT 36 -PINATTR PinName clk -PINATTR Polarity IN -LINE Wide 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName data[255:0] -PINATTR Polarity IN -LINE Wide 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName trig0[7:0] -PINATTR Polarity IN - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.cdc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.cdc deleted file mode 100644 index 183cac389..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.cdc +++ /dev/null @@ -1,275 +0,0 @@ -#ChipScope Core Generator Project File Version 3.0 -#Wed Jan 30 10:07:41 PST 2013 -SignalExport.clockChannel=CLK -SignalExport.dataChannel<0000>=DATA[0] -SignalExport.dataChannel<0001>=DATA[1] -SignalExport.dataChannel<0002>=DATA[2] -SignalExport.dataChannel<0003>=DATA[3] -SignalExport.dataChannel<0004>=DATA[4] -SignalExport.dataChannel<0005>=DATA[5] -SignalExport.dataChannel<0006>=DATA[6] -SignalExport.dataChannel<0007>=DATA[7] -SignalExport.dataChannel<0008>=DATA[8] -SignalExport.dataChannel<0009>=DATA[9] -SignalExport.dataChannel<0010>=DATA[10] -SignalExport.dataChannel<0011>=DATA[11] -SignalExport.dataChannel<0012>=DATA[12] -SignalExport.dataChannel<0013>=DATA[13] -SignalExport.dataChannel<0014>=DATA[14] -SignalExport.dataChannel<0015>=DATA[15] -SignalExport.dataChannel<0016>=DATA[16] -SignalExport.dataChannel<0017>=DATA[17] -SignalExport.dataChannel<0018>=DATA[18] -SignalExport.dataChannel<0019>=DATA[19] -SignalExport.dataChannel<0020>=DATA[20] -SignalExport.dataChannel<0021>=DATA[21] -SignalExport.dataChannel<0022>=DATA[22] -SignalExport.dataChannel<0023>=DATA[23] -SignalExport.dataChannel<0024>=DATA[24] -SignalExport.dataChannel<0025>=DATA[25] -SignalExport.dataChannel<0026>=DATA[26] -SignalExport.dataChannel<0027>=DATA[27] -SignalExport.dataChannel<0028>=DATA[28] -SignalExport.dataChannel<0029>=DATA[29] -SignalExport.dataChannel<0030>=DATA[30] -SignalExport.dataChannel<0031>=DATA[31] -SignalExport.dataChannel<0032>=DATA[32] -SignalExport.dataChannel<0033>=DATA[33] -SignalExport.dataChannel<0034>=DATA[34] -SignalExport.dataChannel<0035>=DATA[35] -SignalExport.dataChannel<0036>=DATA[36] -SignalExport.dataChannel<0037>=DATA[37] -SignalExport.dataChannel<0038>=DATA[38] -SignalExport.dataChannel<0039>=DATA[39] -SignalExport.dataChannel<0040>=DATA[40] -SignalExport.dataChannel<0041>=DATA[41] -SignalExport.dataChannel<0042>=DATA[42] -SignalExport.dataChannel<0043>=DATA[43] -SignalExport.dataChannel<0044>=DATA[44] -SignalExport.dataChannel<0045>=DATA[45] -SignalExport.dataChannel<0046>=DATA[46] -SignalExport.dataChannel<0047>=DATA[47] -SignalExport.dataChannel<0048>=DATA[48] -SignalExport.dataChannel<0049>=DATA[49] -SignalExport.dataChannel<0050>=DATA[50] -SignalExport.dataChannel<0051>=DATA[51] -SignalExport.dataChannel<0052>=DATA[52] -SignalExport.dataChannel<0053>=DATA[53] -SignalExport.dataChannel<0054>=DATA[54] -SignalExport.dataChannel<0055>=DATA[55] -SignalExport.dataChannel<0056>=DATA[56] -SignalExport.dataChannel<0057>=DATA[57] -SignalExport.dataChannel<0058>=DATA[58] -SignalExport.dataChannel<0059>=DATA[59] -SignalExport.dataChannel<0060>=DATA[60] -SignalExport.dataChannel<0061>=DATA[61] -SignalExport.dataChannel<0062>=DATA[62] -SignalExport.dataChannel<0063>=DATA[63] -SignalExport.dataChannel<0064>=DATA[64] -SignalExport.dataChannel<0065>=DATA[65] -SignalExport.dataChannel<0066>=DATA[66] -SignalExport.dataChannel<0067>=DATA[67] -SignalExport.dataChannel<0068>=DATA[68] -SignalExport.dataChannel<0069>=DATA[69] -SignalExport.dataChannel<0070>=DATA[70] -SignalExport.dataChannel<0071>=DATA[71] -SignalExport.dataChannel<0072>=DATA[72] -SignalExport.dataChannel<0073>=DATA[73] -SignalExport.dataChannel<0074>=DATA[74] -SignalExport.dataChannel<0075>=DATA[75] -SignalExport.dataChannel<0076>=DATA[76] -SignalExport.dataChannel<0077>=DATA[77] -SignalExport.dataChannel<0078>=DATA[78] -SignalExport.dataChannel<0079>=DATA[79] -SignalExport.dataChannel<0080>=DATA[80] -SignalExport.dataChannel<0081>=DATA[81] -SignalExport.dataChannel<0082>=DATA[82] -SignalExport.dataChannel<0083>=DATA[83] -SignalExport.dataChannel<0084>=DATA[84] -SignalExport.dataChannel<0085>=DATA[85] -SignalExport.dataChannel<0086>=DATA[86] -SignalExport.dataChannel<0087>=DATA[87] -SignalExport.dataChannel<0088>=DATA[88] -SignalExport.dataChannel<0089>=DATA[89] -SignalExport.dataChannel<0090>=DATA[90] -SignalExport.dataChannel<0091>=DATA[91] -SignalExport.dataChannel<0092>=DATA[92] -SignalExport.dataChannel<0093>=DATA[93] -SignalExport.dataChannel<0094>=DATA[94] -SignalExport.dataChannel<0095>=DATA[95] -SignalExport.dataChannel<0096>=DATA[96] -SignalExport.dataChannel<0097>=DATA[97] -SignalExport.dataChannel<0098>=DATA[98] -SignalExport.dataChannel<0099>=DATA[99] -SignalExport.dataChannel<0100>=DATA[100] -SignalExport.dataChannel<0101>=DATA[101] -SignalExport.dataChannel<0102>=DATA[102] -SignalExport.dataChannel<0103>=DATA[103] -SignalExport.dataChannel<0104>=DATA[104] -SignalExport.dataChannel<0105>=DATA[105] -SignalExport.dataChannel<0106>=DATA[106] -SignalExport.dataChannel<0107>=DATA[107] -SignalExport.dataChannel<0108>=DATA[108] -SignalExport.dataChannel<0109>=DATA[109] -SignalExport.dataChannel<0110>=DATA[110] -SignalExport.dataChannel<0111>=DATA[111] -SignalExport.dataChannel<0112>=DATA[112] -SignalExport.dataChannel<0113>=DATA[113] -SignalExport.dataChannel<0114>=DATA[114] -SignalExport.dataChannel<0115>=DATA[115] -SignalExport.dataChannel<0116>=DATA[116] -SignalExport.dataChannel<0117>=DATA[117] -SignalExport.dataChannel<0118>=DATA[118] -SignalExport.dataChannel<0119>=DATA[119] -SignalExport.dataChannel<0120>=DATA[120] -SignalExport.dataChannel<0121>=DATA[121] -SignalExport.dataChannel<0122>=DATA[122] -SignalExport.dataChannel<0123>=DATA[123] -SignalExport.dataChannel<0124>=DATA[124] -SignalExport.dataChannel<0125>=DATA[125] -SignalExport.dataChannel<0126>=DATA[126] -SignalExport.dataChannel<0127>=DATA[127] -SignalExport.dataChannel<0128>=DATA[128] -SignalExport.dataChannel<0129>=DATA[129] -SignalExport.dataChannel<0130>=DATA[130] -SignalExport.dataChannel<0131>=DATA[131] -SignalExport.dataChannel<0132>=DATA[132] -SignalExport.dataChannel<0133>=DATA[133] -SignalExport.dataChannel<0134>=DATA[134] -SignalExport.dataChannel<0135>=DATA[135] -SignalExport.dataChannel<0136>=DATA[136] -SignalExport.dataChannel<0137>=DATA[137] -SignalExport.dataChannel<0138>=DATA[138] -SignalExport.dataChannel<0139>=DATA[139] -SignalExport.dataChannel<0140>=DATA[140] -SignalExport.dataChannel<0141>=DATA[141] -SignalExport.dataChannel<0142>=DATA[142] -SignalExport.dataChannel<0143>=DATA[143] -SignalExport.dataChannel<0144>=DATA[144] -SignalExport.dataChannel<0145>=DATA[145] -SignalExport.dataChannel<0146>=DATA[146] -SignalExport.dataChannel<0147>=DATA[147] -SignalExport.dataChannel<0148>=DATA[148] -SignalExport.dataChannel<0149>=DATA[149] -SignalExport.dataChannel<0150>=DATA[150] -SignalExport.dataChannel<0151>=DATA[151] -SignalExport.dataChannel<0152>=DATA[152] -SignalExport.dataChannel<0153>=DATA[153] -SignalExport.dataChannel<0154>=DATA[154] -SignalExport.dataChannel<0155>=DATA[155] -SignalExport.dataChannel<0156>=DATA[156] -SignalExport.dataChannel<0157>=DATA[157] -SignalExport.dataChannel<0158>=DATA[158] -SignalExport.dataChannel<0159>=DATA[159] -SignalExport.dataChannel<0160>=DATA[160] -SignalExport.dataChannel<0161>=DATA[161] -SignalExport.dataChannel<0162>=DATA[162] -SignalExport.dataChannel<0163>=DATA[163] -SignalExport.dataChannel<0164>=DATA[164] -SignalExport.dataChannel<0165>=DATA[165] -SignalExport.dataChannel<0166>=DATA[166] -SignalExport.dataChannel<0167>=DATA[167] -SignalExport.dataChannel<0168>=DATA[168] -SignalExport.dataChannel<0169>=DATA[169] -SignalExport.dataChannel<0170>=DATA[170] -SignalExport.dataChannel<0171>=DATA[171] -SignalExport.dataChannel<0172>=DATA[172] -SignalExport.dataChannel<0173>=DATA[173] -SignalExport.dataChannel<0174>=DATA[174] -SignalExport.dataChannel<0175>=DATA[175] -SignalExport.dataChannel<0176>=DATA[176] -SignalExport.dataChannel<0177>=DATA[177] -SignalExport.dataChannel<0178>=DATA[178] -SignalExport.dataChannel<0179>=DATA[179] -SignalExport.dataChannel<0180>=DATA[180] -SignalExport.dataChannel<0181>=DATA[181] -SignalExport.dataChannel<0182>=DATA[182] -SignalExport.dataChannel<0183>=DATA[183] -SignalExport.dataChannel<0184>=DATA[184] -SignalExport.dataChannel<0185>=DATA[185] -SignalExport.dataChannel<0186>=DATA[186] -SignalExport.dataChannel<0187>=DATA[187] -SignalExport.dataChannel<0188>=DATA[188] -SignalExport.dataChannel<0189>=DATA[189] -SignalExport.dataChannel<0190>=DATA[190] -SignalExport.dataChannel<0191>=DATA[191] -SignalExport.dataChannel<0192>=DATA[192] -SignalExport.dataChannel<0193>=DATA[193] -SignalExport.dataChannel<0194>=DATA[194] -SignalExport.dataChannel<0195>=DATA[195] -SignalExport.dataChannel<0196>=DATA[196] -SignalExport.dataChannel<0197>=DATA[197] -SignalExport.dataChannel<0198>=DATA[198] -SignalExport.dataChannel<0199>=DATA[199] -SignalExport.dataChannel<0200>=DATA[200] -SignalExport.dataChannel<0201>=DATA[201] -SignalExport.dataChannel<0202>=DATA[202] -SignalExport.dataChannel<0203>=DATA[203] -SignalExport.dataChannel<0204>=DATA[204] -SignalExport.dataChannel<0205>=DATA[205] -SignalExport.dataChannel<0206>=DATA[206] -SignalExport.dataChannel<0207>=DATA[207] -SignalExport.dataChannel<0208>=DATA[208] -SignalExport.dataChannel<0209>=DATA[209] -SignalExport.dataChannel<0210>=DATA[210] -SignalExport.dataChannel<0211>=DATA[211] -SignalExport.dataChannel<0212>=DATA[212] -SignalExport.dataChannel<0213>=DATA[213] -SignalExport.dataChannel<0214>=DATA[214] -SignalExport.dataChannel<0215>=DATA[215] -SignalExport.dataChannel<0216>=DATA[216] -SignalExport.dataChannel<0217>=DATA[217] -SignalExport.dataChannel<0218>=DATA[218] -SignalExport.dataChannel<0219>=DATA[219] -SignalExport.dataChannel<0220>=DATA[220] -SignalExport.dataChannel<0221>=DATA[221] -SignalExport.dataChannel<0222>=DATA[222] -SignalExport.dataChannel<0223>=DATA[223] -SignalExport.dataChannel<0224>=DATA[224] -SignalExport.dataChannel<0225>=DATA[225] -SignalExport.dataChannel<0226>=DATA[226] -SignalExport.dataChannel<0227>=DATA[227] -SignalExport.dataChannel<0228>=DATA[228] -SignalExport.dataChannel<0229>=DATA[229] -SignalExport.dataChannel<0230>=DATA[230] -SignalExport.dataChannel<0231>=DATA[231] -SignalExport.dataChannel<0232>=DATA[232] -SignalExport.dataChannel<0233>=DATA[233] -SignalExport.dataChannel<0234>=DATA[234] -SignalExport.dataChannel<0235>=DATA[235] -SignalExport.dataChannel<0236>=DATA[236] -SignalExport.dataChannel<0237>=DATA[237] -SignalExport.dataChannel<0238>=DATA[238] -SignalExport.dataChannel<0239>=DATA[239] -SignalExport.dataChannel<0240>=DATA[240] -SignalExport.dataChannel<0241>=DATA[241] -SignalExport.dataChannel<0242>=DATA[242] -SignalExport.dataChannel<0243>=DATA[243] -SignalExport.dataChannel<0244>=DATA[244] -SignalExport.dataChannel<0245>=DATA[245] -SignalExport.dataChannel<0246>=DATA[246] -SignalExport.dataChannel<0247>=DATA[247] -SignalExport.dataChannel<0248>=DATA[248] -SignalExport.dataChannel<0249>=DATA[249] -SignalExport.dataChannel<0250>=DATA[250] -SignalExport.dataChannel<0251>=DATA[251] -SignalExport.dataChannel<0252>=DATA[252] -SignalExport.dataChannel<0253>=DATA[253] -SignalExport.dataChannel<0254>=DATA[254] -SignalExport.dataChannel<0255>=DATA[255] -SignalExport.dataEqualsTrigger=false -SignalExport.dataPortWidth=256 -SignalExport.triggerChannel<0000><0000>=TRIG0[0] -SignalExport.triggerChannel<0000><0001>=TRIG0[1] -SignalExport.triggerChannel<0000><0002>=TRIG0[2] -SignalExport.triggerChannel<0000><0003>=TRIG0[3] -SignalExport.triggerChannel<0000><0004>=TRIG0[4] -SignalExport.triggerChannel<0000><0005>=TRIG0[5] -SignalExport.triggerChannel<0000><0006>=TRIG0[6] -SignalExport.triggerChannel<0000><0007>=TRIG0[7] -SignalExport.triggerPort<0000>.name=TRIG0 -SignalExport.triggerPortCount=1 -SignalExport.triggerPortIsData<0000>=false -SignalExport.triggerPortWidth<0000>=8 -SignalExport.type=ila - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.ucf b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.ucf deleted file mode 100644 index 82f632d21..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.ucf +++ /dev/null @@ -1,17 +0,0 @@ -# -# Clock constraints -# -NET "CLK" TNM_NET = D_CLK ; -INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; -TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG; -TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; -TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; -TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; - -# -# Input keep/save net constraints -# -NET "TRIG0<*" S; -NET "TRIG0<*" KEEP; -NET "DATA<*" S; -NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.xdc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.xdc deleted file mode 100644 index 49e2b9e7b..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.constraints/chipscope_ila.xdc +++ /dev/null @@ -1,6 +0,0 @@ -# -# Clock constraints -# -set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] -set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.gise b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.gise deleted file mode 100644 index bf58d19ac..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.gise +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ncf b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ngc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ngc deleted file mode 100644 index f655fb58f..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ucf b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ucf deleted file mode 100644 index 82f632d21..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.ucf +++ /dev/null @@ -1,17 +0,0 @@ -# -# Clock constraints -# -NET "CLK" TNM_NET = D_CLK ; -INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; -TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG; -TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; -TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; -TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; - -# -# Input keep/save net constraints -# -NET "TRIG0<*" S; -NET "TRIG0<*" KEEP; -NET "DATA<*" S; -NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.v b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.v deleted file mode 100644 index 1c77ab89b..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.v +++ /dev/null @@ -1,33 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2013 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 14.4 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_ila.v -// /___/ /\ Timestamp : Wed Jan 30 10:07:41 PST 2013 -// \ \ / \ -// \___\/\___\ -// -// Design Name: Verilog Synthesis Wrapper -/////////////////////////////////////////////////////////////////////////////// -// This wrapper is used to integrate with Project Navigator and PlanAhead - -`timescale 1ns/1ps - -module chipscope_ila( - CONTROL, - CLK, - DATA, - TRIG0) /* synthesis syn_black_box syn_noprune=1 */; - - -inout [35 : 0] CONTROL; -input CLK; -input [255 : 0] DATA; -input [7 : 0] TRIG0; - -endmodule diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.veo b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.veo deleted file mode 100644 index 86140dddd..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.veo +++ /dev/null @@ -1,31 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 2013 Xilinx, Inc. -// All Rights Reserved -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 14.4 -// \ \ Application: Xilinx CORE Generator -// / / Filename : chipscope_ila.veo -// /___/ /\ Timestamp : Wed Jan 30 10:07:41 PST 2013 -// \ \ / \ -// \___\/\___\ -// -// Design Name: ISE Instantiation template -/////////////////////////////////////////////////////////////////////////////// - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -chipscope_ila YourInstanceName ( - .CONTROL(CONTROL), // INOUT BUS [35:0] - .CLK(CLK), // IN - .DATA(DATA), // IN BUS [255:0] - .TRIG0(TRIG0) // IN BUS [7:0] -); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xco b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xco deleted file mode 100644 index a197969f5..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xco +++ /dev/null @@ -1,141 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Wed Jan 30 18:05:25 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fbg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a -# END Select -# BEGIN Parameters -CSET check_bramcount=false -CSET component_name=chipscope_ila -CSET constraint_type=external -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET disable_save_keep=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET example_design=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic_with_edges -CSET match_type_11=basic_with_edges -CSET match_type_12=basic_with_edges -CSET match_type_13=basic_with_edges -CSET match_type_14=basic_with_edges -CSET match_type_15=basic_with_edges -CSET match_type_16=basic_with_edges -CSET match_type_2=basic_with_edges -CSET match_type_3=basic_with_edges -CSET match_type_4=basic_with_edges -CSET match_type_5=basic_with_edges -CSET match_type_6=basic_with_edges -CSET match_type_7=basic_with_edges -CSET match_type_8=basic_with_edges -CSET match_type_9=basic_with_edges -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=16384 -CSET sample_on=Rising -CSET trigger_port_width_1=8 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=false -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-12-18T02:47:40Z -# END Extra information -GENERATE -# CRC: 529ae269 diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xdc b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xdc deleted file mode 100644 index 49e2b9e7b..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xdc +++ /dev/null @@ -1,6 +0,0 @@ -# -# Clock constraints -# -set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] -set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xise b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xise deleted file mode 100644 index a7b6a4ff0..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila.xise +++ /dev/null @@ -1,72 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_flist.txt b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_flist.txt deleted file mode 100644 index fc7d41b56..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_flist.txt +++ /dev/null @@ -1,17 +0,0 @@ -# Output products list for -chipscope_ila.asy -chipscope_ila.cdc -chipscope_ila.constraints/chipscope_ila.ucf -chipscope_ila.constraints/chipscope_ila.xdc -chipscope_ila.gise -chipscope_ila.ncf -chipscope_ila.ngc -chipscope_ila.ucf -chipscope_ila.v -chipscope_ila.veo -chipscope_ila.xco -chipscope_ila.xdc -chipscope_ila.xise -chipscope_ila_flist.txt -chipscope_ila_readme.txt -chipscope_ila_xmdf.tcl diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_readme.txt b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_readme.txt deleted file mode 100644 index 42e95e1e7..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_readme.txt +++ /dev/null @@ -1,47 +0,0 @@ -The following files were generated for 'chipscope_ila' in directory -/home/jblum/coregen_chipscope/ - -XCO file generator: - Generate an XCO file for compatibility with legacy flows. - - * chipscope_ila.xco - -Creates an implementation netlist: - Creates an implementation netlist for the IP. - - * chipscope_ila.cdc - * chipscope_ila.constraints/chipscope_ila.ucf - * chipscope_ila.constraints/chipscope_ila.xdc - * chipscope_ila.ncf - * chipscope_ila.ngc - * chipscope_ila.ucf - * chipscope_ila.v - * chipscope_ila.veo - * chipscope_ila.xdc - * chipscope_ila_xmdf.tcl - -IP Symbol Generator: - Generate an IP symbol based on the current project options'. - - * chipscope_ila.asy - -Generate ISE subproject: - Create an ISE subproject for use when including this core in ISE designs - - * chipscope_ila.gise - * chipscope_ila.xise - -Deliver Readme: - Readme file for the IP. - - * chipscope_ila_readme.txt - -Generate FLIST file: - Text file listing all of the output files produced when a customized core was - generated in the CORE Generator. - - * chipscope_ila_flist.txt - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_xmdf.tcl b/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_xmdf.tcl deleted file mode 100755 index b18241e0b..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/chipscope_ila_xmdf.tcl +++ /dev/null @@ -1,87 +0,0 @@ -# The package naming convention is _xmdf -package provide chipscope_ila_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::chipscope_ila_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::chipscope_ila_xmdf::xmdfInit { instance } { -# Variable containing name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila -} -# ::chipscope_ila_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::chipscope_ila_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.cdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf -incr fcount - - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ncf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.xdc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams - diff --git a/fpga/usrp3/top/x300/coregen_chipscope/coregen.cgp b/fpga/usrp3/top/x300/coregen_chipscope/coregen.cgp deleted file mode 100644 index 593e2f179..000000000 --- a/fpga/usrp3/top/x300/coregen_chipscope/coregen.cgp +++ /dev/null @@ -1,9 +0,0 @@ -SET busformat = BusFormatAngleBracketNotRipped -SET designentry = Verilog -SET device = xc7k410t -SET devicefamily = kintex7 -SET flowvendor = Other -SET package = ffg900 -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = false diff --git a/fpga/usrp3/top/x300/coregen_dsp/.gitignore b/fpga/usrp3/top/x300/coregen_dsp/.gitignore index f497e08fb..dbc4e5588 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/.gitignore +++ b/fpga/usrp3/top/x300/coregen_dsp/.gitignore @@ -1,4 +1,4 @@ _xmsgs *.log - +*.ncf diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise index 61795798c..78285c865 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise index af99fb5fb..802546e7a 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise index 1af65c49d..51594434a 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise index ddfc071f2..10aaec131 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise index 471c12463..173aa9e79 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise index a608666d2..8ea2b2c80 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise @@ -12,7 +12,7 @@ - + diff --git a/fpga/usrp3/top/x300/gen_ddrlvds.v b/fpga/usrp3/top/x300/gen_ddrlvds.v index 680b10c84..7b0e4a6a1 100644 --- a/fpga/usrp3/top/x300/gen_ddrlvds.v +++ b/fpga/usrp3/top/x300/gen_ddrlvds.v @@ -1,7 +1,6 @@ -module gen_ddrlvds - ( +module gen_ddrlvds ( // 2X Radio clock input tx_clk_2x, // 1X Radio Clock @@ -23,76 +22,102 @@ module gen_ddrlvds input [15:0] q, // Rising edge sampled on sync_dacs triggers frame sync sequence input sync_dacs - ); - - reg [15:0] i_reg, q_reg; - reg [15:0] i_2x, q_2x; - reg phase, phase_2x; - reg rising_edge; - wire [15:0] i_and_q_2x; - reg sync_2x; - reg sync_dacs_reg; - - - - genvar z; - wire [7:0] tx_int; - wire tx_clk_2x_int; - wire tx_frame_int; - - (* keep = "true", max_fanout = 10 *) wire phase_eq_phase2x = (phase == phase_2x); +); + localparam SYNC_PULSE_WIDTH = 3'd2; + + // + // Figure out the 1X clock level + // + localparam TX_CLK_1X_LOW = 1'b0; + localparam TX_CLK_1X_HIGH = 1'b1; + + reg tx_clk_1x_level; + reg phase, phase_2x; + reg reset_2x; always @(posedge tx_clk_1x) - if (reset) - phase <= 1'b0; - else - phase <= ~phase; + if (reset) + phase <= 1'b0; + else + phase <= ~phase; + always @(posedge tx_clk_2x) + begin + phase_2x <= phase; + //Pipeline reset and tx_clk_1x_level + reset_2x <= reset; + tx_clk_1x_level <= (phase == phase_2x) ? TX_CLK_1X_HIGH : TX_CLK_1X_LOW; + end // // Pipeline input data so that 1x to 2x clock domain jump includes no logic external to this module. // + reg [15:0] i_reg, q_reg; + reg sync_dacs_reg; + always @(posedge tx_clk_1x) - begin - i_reg <= i; - q_reg <= q; - sync_dacs_reg <= sync_dacs; - end + begin + i_reg <= i; + q_reg <= q; + sync_dacs_reg <= sync_dacs; + end + + // + // Generate frame signal and interleave I and Q signals + // + reg [15:0] i_2x, q_2x; + reg [2:0] sync_count; + reg frame; always @(posedge tx_clk_2x) - begin - // Move 1x data to 2x domain, mostly just to add pipeline regs - // for timing closure. - i_2x <= i_reg; - q_2x <= q_reg; - // Sample phase to determine when 1x clock edges occur. - // To sync multiple AD9146 DAC's an extended assertion of FRAME is required, - // when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME, - // also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for. - sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */; - rising_edge <= (phase_eq_phase2x && ~sync_2x); - phase_2x <= phase; - end - - // Interleave I and Q as SDR signals - assign i_and_q_2x = rising_edge ? q_2x : i_2x; + begin + // Move 1x data to 2x domain, mostly just to add pipeline regs + // for timing closure. + i_2x <= i_reg; + q_2x <= q_reg; + + // Sample phase to determine when 1x clock edges occur. + // To sync multiple AD9146 DAC's an extended assertion of FRAME is required, + // when sync flag set, squash one frame assertion which causes a SYNC_PULSE_WIDTH+1 word assertion of FRAME, + // also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for. + if (reset_2x) begin + frame <= 0; + sync_count <= 3'd0; + end else begin + frame <= (tx_clk_1x_level == TX_CLK_1X_LOW) | (sync_count != 3'd0); + if ((tx_clk_1x_level == TX_CLK_1X_LOW) & sync_dacs_reg) + sync_count <= SYNC_PULSE_WIDTH; + else if (sync_count > 3'd0) + sync_count <= sync_count - 3'd1; + end + end + + wire [15:0] i_and_q_2x = frame ? i_2x : q_2x; + // + // Instantiate IO primitives for the source synchronous interface + // + wire [7:0] tx_int; + wire tx_clk_2x_int; + wire tx_frame_int; + + genvar z; generate for(z = 0; z < 8; z = z + 1) - begin : gen_pins - OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z])); - ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr - (.Q(tx_int[z]), .C(tx_clk_2x), - .CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0)); - end + begin : gen_pins + OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z])); + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr + (.Q(tx_int[z]), .C(tx_clk_2x), + .CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0)); + end endgenerate // Generate framing signal to identify I and Q OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n)); ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame (.Q(tx_frame_int), .C(tx_clk_2x), - .CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0)); + .CE(1'b1), .D1(frame), .D2(frame), .S(1'b0), .R(1'b0)); // Source synchronous clk OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n)); diff --git a/fpga/usrp3/top/x300/gen_ddrlvds_tb.v b/fpga/usrp3/top/x300/gen_ddrlvds_tb.v index 0d6a14317..f511772a8 100644 --- a/fpga/usrp3/top/x300/gen_ddrlvds_tb.v +++ b/fpga/usrp3/top/x300/gen_ddrlvds_tb.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ps +`timescale 1ps/1ps module gen_ddrlvds_tb(); @@ -6,19 +6,16 @@ module gen_ddrlvds_tb(); glbl glbl( ); reg clk = 1; + reg clk_2x = 1; reg reset = 1; - reg tx_strobe = 0; + reg sync_dacs_req = 0; always #100 clk = ~clk; - always #200 tx_strobe = ~tx_strobe; + always #50 clk_2x = ~clk_2x; - - initial $dumpfile("gen_ddrlvds_tb.vcd"); - initial $dumpvars(0,gen_ddrlvds_tb); - - wire [7:0] pins_p, pins_n; - wire frame_p, frame_n; - wire clk_p, clk_n; + wire [7:0] dac_pins_p, dac_pins_n; + wire dac_frame_p, dac_frame_n; + wire dac_clk_p, dac_clk_n; reg [7:0] count; @@ -26,45 +23,49 @@ module gen_ddrlvds_tb(); wire [15:0] q = {4'hB,count}; initial - begin - #10000 reset = 0; - BURST(4); - BURST(5); - #2000; - $finish; - end - + begin + #500 reset = 0; + @(posedge clk); + //#10 + sync_dacs_req <= 1; + #200 + sync_dacs_req <= 0; + +// BURST (4); +// BURST (5); + #20000; + end + task BURST; input [7:0] len; - + begin + sync_dacs_req <= 0; + count <= 0; + @ (posedge clk); + @ (posedge clk); + repeat (len) begin -// tx_strobe <= 0; - count <= 0; - @(posedge clk); - @(posedge clk); - repeat(len) - begin - // tx_strobe <= 1; - @(posedge clk); - // tx_strobe <= 0; - @(posedge clk); - count <= count + 1; - end -// tx_strobe <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); + sync_dacs_req <= 1; + @ (posedge clk); + sync_dacs_req <= 0; + @ (posedge clk); + count <= count + 1; end - endtask // BURST - - gen_ddrlvds gen_ddrlvds - (.rst(reset), - .tx_clk_p(clk_p), .tx_clk_n(clk_n), - .tx_frame_p(frame_p), .tx_frame_n(frame_n), - .tx_d_p(pins_p), .tx_d_n(pins_n), - .tx_clk(clk), .tx_strobe(tx_strobe), - .i(i), .q(q) - ); - - + sync_dacs_req <= 0; + @ (posedge clk); + @ (posedge clk); + @ (posedge clk); + end + endtask // + + gen_ddrlvds dut ( + .reset(reset), + .tx_clk_2x_p(dac_clk_p), .tx_clk_2x_n(dac_clk_n), + .tx_frame_p(dac_frame_p), .tx_frame_n(dac_frame_n), + .tx_d_p(dac_pins_p), .tx_d_n(dac_pins_n), + .tx_clk_2x(clk_2x), .tx_clk_1x(clk), + .i(i), .q(q), + .sync_dacs(sync_dacs_req) + ); + endmodule // gen_ddrlvds_tb diff --git a/fpga/usrp3/top/x300/gige_phy.v b/fpga/usrp3/top/x300/gige_phy.v deleted file mode 100644 index 685272b05..000000000 --- a/fpga/usrp3/top/x300/gige_phy.v +++ /dev/null @@ -1,116 +0,0 @@ - -module gige_phy - (input reset, - input independent_clock, -// input ETH_CLK_p, input ETH_CLK_n, - input sfp_clk, - input SFP_RX_p, input SFP_RX_n, - output SFP_TX_p, output SFP_TX_n, - output gmii_clk, - input [7:0] gmii_txd, input gmii_tx_en, input gmii_tx_er, - output [7:0] gmii_rxd, output gmii_rx_dv, output gmii_rx_er, - output [31:0] misc_debug, - output [15:0] int_data, - output [15:0] status_vector); - -// wire sfp_clk; - wire mmcm_locked, mmcm_reset, resetdone, clkfbout; - wire userclk, userclk2; - wire txoutclk, txoutclk_bufg; - assign gmii_clk = userclk2; // 125 MHz - -// IBUFDS_GTE2 clk_sfp_pin (.O(sfp_clk),.I(ETH_CLK_p),.IB(ETH_CLK_n), .CEB(1'b0)); - - // Route txoutclk input through a BUFG - // FIXME is this really necessary? It seems wasteful. - BUFG bufg_txoutclk (.I (txoutclk), .O (txoutclk_bufg)); - - // This 62.5MHz clock is placed onto global clock routing and is then used - // for tranceiver TXUSRCLK/RXUSRCLK. - BUFG bufg_userclk (.I (clkout1), .O (userclk)); - - // This 125MHz clock is placed onto global clock routing and is then used - // to clock all Ethernet core logic. - BUFG bufg_userclk2 (.I (clkout0), .O (userclk2)); - - // The GT transceiver provides a 62.5MHz clock to the FPGA fabric. This is - // routed to an MMCM module where it is used to create phase and frequency - // related 62.5MHz and 125MHz clock sources - MMCME2_ADV # - (.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (16.000), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (8.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.5), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (16), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.5), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (16.0), - .REF_JITTER1 (0.010) - ) mmcm_adv_inst - (// Output clocks - .CLKFBOUT (clkfbout), - .CLKFBOUTB (), - .CLKOUT0 (clkout0), - .CLKOUT0B (), - .CLKOUT1 (clkout1), - .CLKOUT1B (), - .CLKOUT2 (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - // Input clock control - .CLKFBIN (clkfbout), - .CLKIN1 (txoutclk_bufg), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (), - .DRDY (), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - // Other control and status signals - .LOCKED (mmcm_locked), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_reset) - ); - - assign mmcm_reset = reset | ~resetdone; - - gige_sfp_block gige_sfp_block - (.gtrefclk(sfp_clk), .txp(SFP_TX_p), .txn(SFP_TX_n), .rxp(SFP_RX_p), .rxn(SFP_RX_n), - .txoutclk(txoutclk), .resetdone(resetdone), .mmcm_locked(mmcm_locked), .userclk(userclk), .userclk2(userclk2), - .independent_clock_bufg(independent_clock), - .pma_reset(reset), - .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), - .gmii_rxd(gmii_rxd), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), - .gmii_isolate(), // unused - - .configuration_vector(5'b00000), - .status_vector(status_vector), .reset(reset), .signal_detect(1'b1), - .misc_debug(misc_debug), - .int_data(int_data)); - -endmodule // gige_phy diff --git a/fpga/usrp3/top/x300/gige_phy/README b/fpga/usrp3/top/x300/gige_phy/README new file mode 100644 index 000000000..3d030c51d --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/README @@ -0,0 +1 @@ +The files in this directory have been adapted from the "Ethernet 1000BASE-X PCS/PMA or SGMII" Xilinx IPCore example design. diff --git a/fpga/usrp3/top/x300/gige_phy/gige_phy_mdio.v b/fpga/usrp3/top/x300/gige_phy/gige_phy_mdio.v new file mode 100644 index 000000000..a86fee447 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/gige_phy_mdio.v @@ -0,0 +1,148 @@ + +module gige_phy_mdio + (input reset, + input independent_clock, + input sfp_clk, + input SFP_RX_p, + input SFP_RX_n, + output SFP_TX_p, + output SFP_TX_n, + output gmii_clk, + input [7:0] gmii_txd, + input gmii_tx_en, + input gmii_tx_er, + output [7:0] gmii_rxd, + output gmii_rx_dv, + output gmii_rx_er, + output [31:0] misc_debug, + output [15:0] int_data, + output [15:0] status_vector, + // MDIO signals + input [4:0] prtad, + input mdc, + input mdio_i, + output mdio_o, + output mdio_t + ); + + + wire mmcm_locked, mmcm_reset, resetdone, clkfbout; + wire userclk, userclk2; + wire txoutclk, txoutclk_bufg; + + assign gmii_clk = userclk2; // 125 MHz + + // Route txoutclk input through a BUFG + // FIXME is this really necessary? It seems wasteful. + BUFG bufg_txoutclk (.I (txoutclk), .O (txoutclk_bufg)); + + // This 62.5MHz clock is placed onto global clock routing and is then used + // for tranceiver TXUSRCLK/RXUSRCLK. + BUFG bufg_userclk (.I (clkout1), .O (userclk)); + + // This 125MHz clock is placed onto global clock routing and is then used + // to clock all Ethernet core logic. + BUFG bufg_userclk2 (.I (clkout0), .O (userclk2)); + + // The GT transceiver provides a 62.5MHz clock to the FPGA fabric. This is + // routed to an MMCM module where it is used to create phase and frequency + // related 62.5MHz and 125MHz clock sources + MMCME2_ADV # + (.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (16.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (8.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.5), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (16), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.5), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (16.0), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst + (// Output clocks + .CLKFBOUT (clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (clkout0), + .CLKOUT0B (), + .CLKOUT1 (clkout1), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN1 (txoutclk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + + assign mmcm_reset = reset | ~resetdone; + + + gige_sfp_mdio_block gige_sfp_mdio_block + ( + .gtrefclk (sfp_clk), + .txp (SFP_TX_p), + .txn (SFP_TX_n), + .rxp (SFP_RX_p), + .rxn (SFP_RX_n), + .txoutclk (txoutclk), + .resetdone (resetdone), + .mmcm_locked (mmcm_locked), + .userclk (userclk), + .userclk2 (userclk2), + .independent_clock_bufg(independent_clock), + .pma_reset (reset), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .gmii_isolate (), // Unused + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyad (prtad), + .configuration_vector (5'b00000), + .configuration_valid (1'b1), //default + .status_vector (status_vector), + .reset (reset), + .signal_detect (1'b1) + ); + + +endmodule // gige_phy diff --git a/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_block.v b/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_block.v new file mode 100644 index 000000000..b3304b31d --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_block.v @@ -0,0 +1,262 @@ +//------------------------------------------------------------------------------ +// File : gige_sfp_mdio_block.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This Core Block Level wrapper connects the core to a +// Series-7 Transceiver. +// +// +// ------------------------------------------------------------ +// | Core Block wrapper | +// | | +// | ------------------ ----------------- | +// | | Core | | Transceiver | | +// | | | | | | +// | | | | | | +// | | | | | | +// ---------->| GMII |--------->| TXP |--------> +// | | Tx | | TXN | | +// | | | | | | +// | | | | | | +// | | | | | | +// | | | | | | +// | | | | | | +// | | GMII | | RXP | | +// <----------| Rx |<---------| RXN |<-------- +// | | | | | | +// | ------------------ ----------------- | +// | | +// ------------------------------------------------------------ +// +// + + +`timescale 1 ps/1 ps + +//------------------------------------------------------------------------------ +// The module declaration for the Core Block wrapper. +//------------------------------------------------------------------------------ + +module gige_sfp_mdio_block + ( + // Transceiver Interface + //---------------------- + + input gtrefclk, // Very high quality 125MHz clock for GT transceiver. + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + output txoutclk, // txoutclk from GT transceiver (62.5MHz) + output resetdone, // The GT transceiver has completed its reset cycle + input mmcm_locked, // locked indication from MMCM + input userclk, // 62.5MHz global clock. + input userclk2, // 125MHz global clock. + input independent_clock_bufg,// 200MHz Independent clock, + input pma_reset, // transceiver PMA reset signal + + // GMII Interface + //--------------- + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output [7:0] gmii_rxd, // Received Data to client MAC. + output gmii_rx_dv, // Received control signal to client MAC. + output gmii_rx_er, // Received control signal to client MAC. + output gmii_isolate, // Tristate control to electrically isolate GMII. + + // Management: MDIO Interface + //--------------------------- + + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyad, // Port address for MDIO. + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect // Input from PMD to indicate presence of optical input. + + ); + + + //--------------------------------------------------------------------------- + // Internal signals used in this block level wrapper. + //--------------------------------------------------------------------------- + + // Core <=> Transceiver interconnect + wire plllock; // The PLL Locked status of the Transceiver + wire mgt_rx_reset; // Reset for the receiver half of the Transceiver + wire mgt_tx_reset; // Reset for the transmitter half of the Transceiver + wire [1:0] rxbufstatus; // Elastic Buffer Status (bit 1 asserted indicates overflow or underflow). + wire rxchariscomma; // Comma detected in RXDATA. + wire rxcharisk; // K character received (or extra data bit) in RXDATA. + wire [2:0] rxclkcorcnt; // Indicates clock correction. + wire [7:0] rxdata; // Data after 8B/10B decoding. + wire rxrundisp; // Running Disparity after current byte, becomes 9th data bit when RXNOTINTABLE='1'. + wire rxdisperr; // Disparity-error in RXDATA. + wire rxnotintable; // Non-existent 8B/10 code indicated. + wire txbuferr; // TX Buffer error (overflow or underflow). + wire loopback; // Set the Transceiver for loopback. + wire powerdown; // Powerdown the Transceiver + wire txchardispmode; // Set running disparity for current byte. + wire txchardispval; // Set running disparity value. + wire txcharisk; // K character transmitted in TXDATA. + wire [7:0] txdata; // Data for 8B/10B encoding. + wire enablealign; // Allow the transceivers to serially realign to a comma character. + + + + //--------------------------------------------------------------------------- + // Instantiate the core + //--------------------------------------------------------------------------- + gige_sfp_mdio gig_eth_pcs_pma_core + ( + .mgt_rx_reset (mgt_rx_reset), + .mgt_tx_reset (mgt_tx_reset), + .userclk (userclk2), + .userclk2 (userclk2), + .dcm_locked (mmcm_locked), + .rxbufstatus (rxbufstatus), + .rxchariscomma (rxchariscomma), + .rxcharisk (rxcharisk), + .rxclkcorcnt (rxclkcorcnt), + .rxdata (rxdata), + .rxdisperr (rxdisperr), + .rxnotintable (rxnotintable), + .rxrundisp (rxrundisp), + .txbuferr (txbuferr), + .powerdown (powerdown), + .txchardispmode (txchardispmode), + .txchardispval (txchardispval), + .txcharisk (txcharisk), + .txdata (txdata), + .enablealign (enablealign), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_in (mdio_i), + .mdio_out (mdio_o), + .mdio_tri (mdio_t), + .phyad (phyad), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect) + + ); + + + //--------------------------------------------------------------------------- + // Component Instantiation for the Series-7 Transceiver wrapper + //--------------------------------------------------------------------------- + + gige_sfp_mdio_transceiver transceiver_inst ( + .encommaalign (enablealign), + .loopback (loopback), + .powerdown (powerdown), + .usrclk (userclk), + .usrclk2 (userclk2), + .independent_clock (independent_clock_bufg), + .data_valid (status_vector[1]), + .txreset (mgt_tx_reset), + .txchardispmode (txchardispmode), + .txchardispval (txchardispval), + .txcharisk (txcharisk), + .txdata (txdata), + .rxreset (mgt_rx_reset), + .rxchariscomma (rxchariscomma), + .rxcharisk (rxcharisk), + .rxclkcorcnt (rxclkcorcnt), + .rxdata (rxdata), + .rxdisperr (rxdisperr), + .rxnotintable (rxnotintable), + .rxrundisp (rxrundisp), + .rxbuferr (rxbufstatus[1]), + .txbuferr (txbuferr), + .plllkdet (plllock), + .txoutclk (txoutclk), + .txn (txn), + .txp (txp), + .rxn (rxn), + .rxp (rxp), + .gtrefclk (gtrefclk), + .pmareset (pma_reset), + .mmcm_locked (mmcm_locked), + .resetdone (resetdone) + ); + + + // Unused + assign rxbufstatus[0] = 1'b0; + + + + // Loopback is performed in the core itself. To alternatively use + // Transceiver loopback, please drive this port appropriately. + assign loopback = 1'b0; + + + +endmodule // gige_sfp_mdio_block + diff --git a/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_reset_sync.v b/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_reset_sync.v new file mode 100644 index 000000000..454538769 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_reset_sync.v @@ -0,0 +1,101 @@ +//------------------------------------------------------------------------------ +// File : gige_sfp_mdio_reset_sync.v +// Author : Xilinx, Inc. +//------------------------------------------------------------------------------ +// Description: Both flip-flops have the same asynchronous reset signal. +// Together the flops create a minimum of a 1 clock period +// duration pulse which is used for synchronous reset. +// +// The flops are placed, using RLOCs, into the same slice. +//------------------------------------------------------------------------------ +// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ + +`timescale 1ps/1ps + +module gige_sfp_mdio_reset_sync #( + parameter INITIALISE = 2'b11 +) +( + input reset_in, + input clk, + output reset_out +); + + + (* shreg_extract = "no", ASYNC_REG = "TRUE" *) + wire reset_stage1; + + (* shreg_extract = "no", ASYNC_REG = "TRUE" *) + wire reset_stage2; + + FDP #( + .INIT (INITIALISE[0]) + ) reset_sync1 ( + .C (clk), + .PRE(reset_in), + .D (1'b0), + .Q (reset_stage1) + ); + + FDP #( + .INIT (INITIALISE[1]) + ) reset_sync2 ( + .C (clk), + .PRE(reset_in), + .D (reset_stage1), + .Q (reset_stage2) + ); + + +assign reset_out = reset_stage2; + + + +endmodule diff --git a/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_sync_block.v b/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_sync_block.v new file mode 100644 index 000000000..638e012c3 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_sync_block.v @@ -0,0 +1,101 @@ +//------------------------------------------------------------------------------ +// File : gige_sfp_mdio_sync_block.vhd +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// Description: Used on signals crossing from one clock domain to +// another, this is a flip-flop pair, with both flops +// placed together with RLOCs into the same slice. Thus +// the routing delay between the two is minimum to safe- +// guard against metastability issues. +//------------------------------------------------------------------------------ +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ + +`timescale 1ps / 1ps + +module gige_sfp_mdio_sync_block #( + parameter INITIALISE = 2'b00 +) +( + input clk, // clock to be sync'ed to + input data_in, // Data to be 'synced' + output data_out // synced data +); + + // Internal Signals + wire data_sync1; + wire data_sync2; + + + (* shreg_extract = "no", ASYNC_REG = "TRUE", RLOC = "X0Y0" *) + FD #( + .INIT (INITIALISE[0]) + ) data_sync ( + .C (clk), + .D (data_in), + .Q (data_sync1) + ); + + + (* shreg_extract = "no", RLOC = "X0Y0" *) + FD #( + .INIT (INITIALISE[1]) + ) data_sync_reg ( + .C (clk), + .D (data_sync1), + .Q (data_sync2) + ); + + + assign data_out = data_sync2; + + +endmodule + + diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard.v new file mode 100644 index 000000000..cfa9b7eeb --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard.v @@ -0,0 +1,405 @@ +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 2.4 +// \ \ Application : 7 Series FPGAs Transceivers Wizard +// / / Filename : gige_sfp_mdio_gtwizard.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +// +// Module GTWIZARD (a GT Wrapper) +// Generated by Xilinx 7 Series FPGAs Transceivers Wizard +// +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +`default_nettype wire + +`timescale 1ns / 1ps +`define DLY #1 + +//***************************** Entity Declaration **************************** + +(* CORE_GENERATION_INFO = "gige_sfp_mdio_GTWIZARD,gtwizard_v2_4,{protocol_file=gigabit_ethernet_CC}" *) module gige_sfp_mdio_GTWIZARD # +( + // Simulation attributes + parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset + parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C, + parameter PMA_RSV_IN = 32'h00018480, + parameter SIM_VERSION = "4.0" +) +( + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + input [8:0] GT0_DRPADDR_IN, + input GT0_DRPCLK_IN, + input [15:0] GT0_DRPDI_IN, + output [15:0] GT0_DRPDO_OUT, + input GT0_DRPEN_IN, + output GT0_DRPRDY_OUT, + input GT0_DRPWE_IN, + //_________________________________________________________________________ + //_________________________________________________________________________ + //GT0 (X0Y4) + //____________________________CHANNEL PORTS________________________________ + //----------------------- Channel - Ref Clock Ports ------------------------ + input GT0_GTREFCLK0_IN, + //------------------------------ Channel PLL ------------------------------- + output GT0_CPLLFBCLKLOST_OUT, + output GT0_CPLLLOCK_OUT, + input GT0_CPLLLOCKDETCLK_IN, + output GT0_CPLLREFCLKLOST_OUT, + input GT0_CPLLRESET_IN, + //----------------------------- Eye Scan Ports ----------------------------- + output GT0_EYESCANDATAERROR_OUT, + //---------------------- Loopback and Powerdown Ports ---------------------- + input [2:0] GT0_LOOPBACK_IN, + input [1:0] GT0_RXPD_IN, + input [1:0] GT0_TXPD_IN, + //----------------------------- Receive Ports ------------------------------ + input GT0_RXUSERRDY_IN, + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + output [1:0] GT0_RXCHARISCOMMA_OUT, + output [1:0] GT0_RXCHARISK_OUT, + output [1:0] GT0_RXDISPERR_OUT, + output [1:0] GT0_RXNOTINTABLE_OUT, + //----------------- Receive Ports - Clock Correction Ports ----------------- + output [1:0] GT0_RXCLKCORCNT_OUT, + //------------- Receive Ports - Comma Detection and Alignment -------------- + input GT0_RXMCOMMAALIGNEN_IN, + input GT0_RXPCOMMAALIGNEN_IN, + //----------------- Receive Ports - RX Data Path interface ----------------- + input GT0_GTRXRESET_IN, + output [15:0] GT0_RXDATA_OUT, + output GT0_RXOUTCLK_OUT, + input GT0_RXPCSRESET_IN, + input GT0_RXPMARESET_IN, + input GT0_RXUSRCLK_IN, + input GT0_RXUSRCLK2_IN, + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + input GT0_RXDFEAGCHOLD_IN, + input GT0_RXDFELPMRESET_IN, + output [6:0] GT0_RXMONITOROUT_OUT, + input [1:0] GT0_RXMONITORSEL_IN, + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + input GT0_GTXRXN_IN, + input GT0_GTXRXP_IN, + output GT0_RXCDRLOCK_OUT, + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + input GT0_RXBUFRESET_IN, + output [2:0] GT0_RXBUFSTATUS_OUT, + //---------------------- Receive Ports - RX PLL Ports ---------------------- + output GT0_RXRESETDONE_OUT, + //----------------------------- Transmit Ports ----------------------------- + input GT0_TXUSERRDY_IN, + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + input [1:0] GT0_TXCHARDISPMODE_IN, + input [1:0] GT0_TXCHARDISPVAL_IN, + input [1:0] GT0_TXCHARISK_IN, + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + output [1:0] GT0_TXBUFSTATUS_OUT, + //---------------- Transmit Ports - TX Data Path interface ----------------- + input GT0_GTTXRESET_IN, + input [15:0] GT0_TXDATA_IN, + output GT0_TXOUTCLK_OUT, + output GT0_TXOUTCLKFABRIC_OUT, + output GT0_TXOUTCLKPCS_OUT, + input GT0_TXPCSRESET_IN, + input GT0_TXUSRCLK_IN, + input GT0_TXUSRCLK2_IN, + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + output GT0_GTXTXN_OUT, + output GT0_GTXTXP_OUT, + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + output GT0_TXRESETDONE_OUT, + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + input GT0_TXELECIDLE_IN, + + + //____________________________COMMON PORTS________________________________ + //-------------------- Common Block - Ref Clock Ports --------------------- + input GT0_GTREFCLK0_COMMON_IN, + //----------------------- Common Block - QPLL Ports ------------------------ + output GT0_QPLLLOCK_OUT, + input GT0_QPLLLOCKDETCLK_IN, + output GT0_QPLLREFCLKLOST_OUT, + input GT0_QPLLRESET_IN + +); +//***************************** Parameter Declarations ************************ + parameter QPLL_FBDIV_TOP = 16; + + parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 : + (QPLL_FBDIV_TOP == 20) ? 10'b0000110000 : + (QPLL_FBDIV_TOP == 32) ? 10'b0001100000 : + (QPLL_FBDIV_TOP == 40) ? 10'b0010000000 : + (QPLL_FBDIV_TOP == 64) ? 10'b0011100000 : + (QPLL_FBDIV_TOP == 66) ? 10'b0101000000 : + (QPLL_FBDIV_TOP == 80) ? 10'b0100100000 : + (QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000; + + parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 : + (QPLL_FBDIV_TOP == 20) ? 1'b1 : + (QPLL_FBDIV_TOP == 32) ? 1'b1 : + (QPLL_FBDIV_TOP == 40) ? 1'b1 : + (QPLL_FBDIV_TOP == 64) ? 1'b1 : + (QPLL_FBDIV_TOP == 66) ? 1'b0 : + (QPLL_FBDIV_TOP == 80) ? 1'b1 : + (QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1; +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + + wire gt0_qplloutclk_i; + wire gt0_qplloutrefclk_i; + + wire gt0_qpllclk_i; + wire gt0_qpllrefclk_i; + + +//********************************* Main Body of Code************************** + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + assign gt0_qpllclk_i = gt0_qplloutclk_i; + assign gt0_qpllrefclk_i = gt0_qplloutrefclk_i; + + + + +//------------------------- GT Instances ------------------------------- + //_________________________________________________________________________ + //_________________________________________________________________________ + //GT0 (X0Y4) + + gige_sfp_mdio_GTWIZARD_GT # + ( + // Simulation attributes + .GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION), + .RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN), + .PCS_RSVD_ATTR_IN (48'h000000000000), + .PMA_RSV_IN (PMA_RSV_IN) + ) + gt0_GTWIZARD_i + ( + //-------------------------------- Channel --------------------------------- + .QPLLCLK_IN (gt0_qpllclk_i), + .QPLLREFCLK_IN (gt0_qpllrefclk_i), + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + .DRPADDR_IN (GT0_DRPADDR_IN), + .DRPCLK_IN (GT0_DRPCLK_IN), + .DRPDI_IN (GT0_DRPDI_IN), + .DRPDO_OUT (GT0_DRPDO_OUT), + .DRPEN_IN (GT0_DRPEN_IN), + .DRPRDY_OUT (GT0_DRPRDY_OUT), + .DRPWE_IN (GT0_DRPWE_IN), + //----------------------- Channel - Ref Clock Ports ------------------------ + .GTREFCLK0_IN (GT0_GTREFCLK0_IN), + //------------------------------ Channel PLL ------------------------------- + .CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT), + .CPLLLOCK_OUT (GT0_CPLLLOCK_OUT), + .CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN), + .CPLLREFCLKLOST_OUT (GT0_CPLLREFCLKLOST_OUT), + .CPLLRESET_IN (GT0_CPLLRESET_IN), + //----------------------------- Eye Scan Ports ----------------------------- + .EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT), + //---------------------- Loopback and Powerdown Ports ---------------------- + .LOOPBACK_IN (GT0_LOOPBACK_IN), + .RXPD_IN (GT0_RXPD_IN), + .TXPD_IN (GT0_TXPD_IN), + //----------------------------- Receive Ports ------------------------------ + .RXUSERRDY_IN (GT0_RXUSERRDY_IN), + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + .RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT), + .RXCHARISK_OUT (GT0_RXCHARISK_OUT), + .RXDISPERR_OUT (GT0_RXDISPERR_OUT), + .RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT), + //----------------- Receive Ports - Clock Correction Ports ----------------- + .RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT), + //------------- Receive Ports - Comma Detection and Alignment -------------- + .RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN), + .RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN), + //----------------- Receive Ports - RX Data Path interface ----------------- + .GTRXRESET_IN (GT0_GTRXRESET_IN), + .RXDATA_OUT (GT0_RXDATA_OUT), + .RXOUTCLK_OUT (GT0_RXOUTCLK_OUT), + .RXPCSRESET_IN (GT0_RXPCSRESET_IN), + .RXPMARESET_IN (GT0_RXPMARESET_IN), + .RXUSRCLK_IN (GT0_RXUSRCLK_IN), + .RXUSRCLK2_IN (GT0_RXUSRCLK2_IN), + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + .RXDFEAGCHOLD_IN (GT0_RXDFEAGCHOLD_IN), + .RXDFELPMRESET_IN (GT0_RXDFELPMRESET_IN), + .RXMONITOROUT_OUT (GT0_RXMONITOROUT_OUT), + .RXMONITORSEL_IN (GT0_RXMONITORSEL_IN), + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + .GTXRXN_IN (GT0_GTXRXN_IN), + .GTXRXP_IN (GT0_GTXRXP_IN), + .RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + .RXBUFRESET_IN (GT0_RXBUFRESET_IN), + .RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT), + //---------------------- Receive Ports - RX PLL Ports ---------------------- + .RXRESETDONE_OUT (GT0_RXRESETDONE_OUT), + //----------------------------- Transmit Ports ----------------------------- + .TXUSERRDY_IN (GT0_TXUSERRDY_IN), + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + .TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN), + .TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN), + .TXCHARISK_IN (GT0_TXCHARISK_IN), + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + .TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .GTTXRESET_IN (GT0_GTTXRESET_IN), + .TXDATA_IN (GT0_TXDATA_IN), + .TXOUTCLK_OUT (GT0_TXOUTCLK_OUT), + .TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT), + .TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT), + .TXPCSRESET_IN (GT0_TXPCSRESET_IN), + .TXUSRCLK_IN (GT0_TXUSRCLK_IN), + .TXUSRCLK2_IN (GT0_TXUSRCLK2_IN), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GTXTXN_OUT (GT0_GTXTXN_OUT), + .GTXTXP_OUT (GT0_GTXTXP_OUT), + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + .TXRESETDONE_OUT (GT0_TXRESETDONE_OUT), + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + .TXELECIDLE_IN (GT0_TXELECIDLE_IN) + + ); + + + //_________________________________________________________________________ + //_________________________________________________________________________ + //_________________________GTXE2_COMMON____________________________________ + + GTXE2_COMMON # + ( + // Simulation attributes + .SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION (SIM_VERSION), + + + //----------------COMMON BLOCK Attributes--------------- + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (27'h06801C1), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV_IN), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (1) + + ) + gtxe2_common_0_i + ( + //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + .DRPADDR (tied_to_ground_vec_i[7:0]), + .DRPCLK (tied_to_ground_i), + .DRPDI (tied_to_ground_vec_i[15:0]), + .DRPDO (), + .DRPEN (tied_to_ground_i), + .DRPRDY (), + .DRPWE (tied_to_ground_i), + //-------------------- Common Block - Ref Clock Ports --------------------- + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN), + .GTREFCLK1 (tied_to_ground_i), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //----------------------- Common Block - QPLL Ports ------------------------ + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .QPLLLOCK (GT0_QPLLLOCK_OUT), + .QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN), + .QPLLLOCKEN (tied_to_vcc_i), + .QPLLOUTCLK (gt0_qplloutclk_i), + .QPLLOUTREFCLK (gt0_qplloutrefclk_i), + .QPLLOUTRESET (tied_to_ground_i), + .QPLLPD (tied_to_ground_i), + .QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT), + .QPLLREFCLKSEL (3'b001), + .QPLLRESET (GT0_QPLLRESET_IN), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + .REFCLKOUTMONITOR (), + //--------------------------- Common Block Ports --------------------------- + .BGBYPASSB (tied_to_vcc_i), + .BGMONITORENB (tied_to_vcc_i), + .BGPDB (tied_to_vcc_i), + .BGRCALOVRD (5'b00000), + .PMARSVD (8'b00000000), + .RCALENB (tied_to_vcc_i) + + ); + + + + +endmodule diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v new file mode 100644 index 000000000..4a70d3cf0 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v @@ -0,0 +1,763 @@ +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 2.4 +// \ \ Application : GT Wizard +// / / Filename : gige_sfp_mdio_gtwizard_gt.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +// +// Module GTWIZARD_GT (a GT Wrapper) +// Generated by Xilinx GT Wizard +// +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +`default_nettype wire + +`timescale 1ns / 1ps + + +//***************************** Entity Declaration **************************** + +module gige_sfp_mdio_GTWIZARD_GT # +( + // Simulation attributes + parameter GT_SIM_GTRESET_SPEEDUP = "false", // Set to 1 to speed up sim reset; + parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C, + parameter PMA_RSV_IN = 32'h00018480, + parameter PCS_RSVD_ATTR_IN = 48'h000000000000, + parameter SIM_VERSION = "4.0" +) +( + //-------------------------------- Channel --------------------------------- + input QPLLCLK_IN, + input QPLLREFCLK_IN, + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + input [8:0] DRPADDR_IN, + input DRPCLK_IN, + input [15:0] DRPDI_IN, + output [15:0] DRPDO_OUT, + input DRPEN_IN, + output DRPRDY_OUT, + input DRPWE_IN, + //----------------------- Channel - Ref Clock Ports ------------------------ + input GTREFCLK0_IN, + //------------------------------ Channel PLL ------------------------------- + output CPLLFBCLKLOST_OUT, + output CPLLLOCK_OUT, + input CPLLLOCKDETCLK_IN, + output CPLLREFCLKLOST_OUT, + input CPLLRESET_IN, + //----------------------------- Eye Scan Ports ----------------------------- + output EYESCANDATAERROR_OUT, + //---------------------- Loopback and Powerdown Ports ---------------------- + input [2:0] LOOPBACK_IN, + input [1:0] RXPD_IN, + input [1:0] TXPD_IN, + //----------------------------- Receive Ports ------------------------------ + input RXUSERRDY_IN, + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + output [1:0] RXCHARISCOMMA_OUT, + output [1:0] RXCHARISK_OUT, + output [1:0] RXDISPERR_OUT, + output [1:0] RXNOTINTABLE_OUT, + //----------------- Receive Ports - Clock Correction Ports ----------------- + output [1:0] RXCLKCORCNT_OUT, + //------------- Receive Ports - Comma Detection and Alignment -------------- + input RXMCOMMAALIGNEN_IN, + input RXPCOMMAALIGNEN_IN, + //----------------- Receive Ports - RX Data Path interface ----------------- + input GTRXRESET_IN, + output [15:0] RXDATA_OUT, + output RXOUTCLK_OUT, + input RXPCSRESET_IN, + input RXPMARESET_IN, + input RXUSRCLK_IN, + input RXUSRCLK2_IN, + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + input RXDFEAGCHOLD_IN, + input RXDFELPMRESET_IN, + output [6:0] RXMONITOROUT_OUT, + input [1:0] RXMONITORSEL_IN, + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + input GTXRXN_IN, + input GTXRXP_IN, + output RXCDRLOCK_OUT, + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + input RXBUFRESET_IN, + output [2:0] RXBUFSTATUS_OUT, + //---------------------- Receive Ports - RX PLL Ports ---------------------- + output RXRESETDONE_OUT, + //----------------------------- Transmit Ports ----------------------------- + input TXUSERRDY_IN, + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + input [1:0] TXCHARDISPMODE_IN, + input [1:0] TXCHARDISPVAL_IN, + input [1:0] TXCHARISK_IN, + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + output [1:0] TXBUFSTATUS_OUT, + //---------------- Transmit Ports - TX Data Path interface ----------------- + input GTTXRESET_IN, + input [15:0] TXDATA_IN, + output TXOUTCLK_OUT, + output TXOUTCLKFABRIC_OUT, + output TXOUTCLKPCS_OUT, + input TXPCSRESET_IN, + input TXUSRCLK_IN, + input TXUSRCLK2_IN, + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + output GTXTXN_OUT, + output GTXTXP_OUT, + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + output TXRESETDONE_OUT, + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + input TXELECIDLE_IN + + +); + + +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + + + //RX Datapath signals + wire [63:0] rxdata_i; + wire [5:0] rxchariscomma_float_i; + wire [5:0] rxcharisk_float_i; + wire [5:0] rxdisperr_float_i; + wire [5:0] rxnotintable_float_i; + wire [5:0] rxrundisp_float_i; + + + //TX Datapath signals + wire [63:0] txdata_i; + wire [5:0] txkerr_float_i; + wire [5:0] txrundisp_float_i; + +// +//********************************* Main Body of Code************************** + + //------------------------- Static signal Assigments --------------------- + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + //------------------- GT Datapath byte mapping ----------------- + assign RXDATA_OUT = rxdata_i[15:0]; + + + assign txdata_i = {tied_to_ground_vec_i[47:0],TXDATA_IN}; + + + + + //------------------------- GT Instantiations -------------------------- + GTXE2_CHANNEL # + ( + //_______________________ Simulation-Only Attributes __________________ + + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), + .SIM_RESET_SPEEDUP (GT_SIM_GTRESET_SPEEDUP), + .SIM_CPLLREFCLK_SEL (3'b001), + .SIM_VERSION (SIM_VERSION), + + + //----------------RX Byte and Word Alignment Attributes--------------- + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b0001111111), + .ALIGN_COMMA_WORD (2), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .SHOW_REALIGN_COMMA ("TRUE"), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RX_SIG_VALID_DLY (10), + + //----------------RX 8B/10B Decoder Attributes--------------- + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + + //----------------------RX Clock Correction Attributes---------------------- + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CLK_COR_SEQ_2_USE ("TRUE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (36), + .CLK_COR_MIN_LAT (33), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_LEN (2), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_1_1 (10'b0110111100), + .CLK_COR_SEQ_1_2 (10'b0001010000), + .CLK_COR_SEQ_1_3 (10'b0000000000), + .CLK_COR_SEQ_1_4 (10'b0000000000), + .CLK_CORRECT_USE ("TRUE"), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0110111100), + .CLK_COR_SEQ_2_2 (10'b0010110101), + .CLK_COR_SEQ_2_3 (10'b0000000000), + .CLK_COR_SEQ_2_4 (10'b0000000000), + + //----------------------RX Channel Bonding Attributes---------------------- + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_LEN (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + + //-------------------------RX Margin Analysis Attributes---------------------------- + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("FALSE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER (80'h00000000000000000000), + .ES_QUAL_MASK (80'h00000000000000000000), + .ES_SDATA_MASK (80'h00000000000000000000), + .ES_VERT_OFFSET (9'b000000000), + + //-----------------------FPGA RX Interface Attributes------------------------- + .RX_DATA_WIDTH (20), + + //-------------------------PMA Attributes---------------------------- + .OUTREFCLK_SEL_INV (2'b11), + .PMA_RSV (PMA_RSV_IN), + .PMA_RSV2 (16'h2050), + .PMA_RSV3 (2'b00), + .PMA_RSV4 (32'h00000000), + .RX_BIAS_CFG (12'b000000000100), + .DMONITOR_CFG (24'h000A00), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (3'b010), + .RX_DEBUG_CFG (12'b000000000000), + .RX_OS_CFG (13'b0000010000000), + .TERM_RCAL_CFG (5'b10000), + .TERM_RCAL_OVRD (1'b0), + .TST_RSV (32'h00000000), + .RX_CLK25_DIV (5), + .TX_CLK25_DIV (5), + .UCODEER_CLR (1'b0), + + //-------------------------PCI Express Attributes---------------------------- + .PCS_PCIE_EN ("FALSE"), + + //-------------------------PCS Attributes---------------------------- + .PCS_RSVD_ATTR (PCS_RSVD_ATTR_IN), + + //-----------RX Buffer Attributes------------ + .RXBUF_ADDR_MODE ("FULL"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RX_BUFFER_CFG (6'b000000), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUFRESET_TIME (5'b00001), + .RXBUF_THRESH_OVFLW (61), + .RXBUF_THRESH_OVRD ("FALSE"), + .RXBUF_THRESH_UNDFLW (8), + .RXDLY_CFG (16'h001F), + .RXDLY_LCFG (9'h030), + .RXDLY_TAP_CFG (16'h0000), + .RXPH_CFG (24'h000000), + .RXPHDLY_CFG (24'h084020), + .RXPH_MONITOR_SEL (5'b00000), + .RX_XCLK_SEL ("RXREC"), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + + //---------------------CDR Attributes------------------------- + + //For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002 + + //For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h03000023ff10200020 + .RXCDR_CFG (72'h03000023ff40080020), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCDR_LOCK_CFG (6'b010101), + + //-----------------RX Initialization and Reset Attributes------------------- + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXISCANRESET_TIME (5'b00001), + .RXPCSRESET_TIME (5'b00001), + .RXPMARESET_TIME (5'b00011), + + //-----------------RX OOB Signaling Attributes------------------- + .RXOOB_CFG (7'b0000110), + + //-----------------------RX Gearbox Attributes--------------------------- + .RXGEARBOX_EN ("FALSE"), + .GEARBOX_MODE (3'b000), + + //-----------------------PRBS Detection Attribute----------------------- + .RXPRBS_ERR_LOOPBACK (1'b0), + + //-----------Power-Down Attributes---------- + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h19), + .PD_TRANS_TIME_TO_P2 (8'h64), + + //-----------RX OOB Signaling Attributes---------- + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + + //-----------RX Fabric Clock Output Control Attributes---------- + .TRANS_TIME_RATE (8'h0E), + + //------------TX Buffer Attributes---------------- + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h001F), + .TXDLY_LCFG (9'h030), + .TXDLY_TAP_CFG (16'h0000), + .TXPH_CFG (16'h0780), + .TXPHDLY_CFG (24'h084020), + .TXPH_MONITOR_SEL (5'b00000), + .TX_XCLK_SEL ("TXOUT"), + + //-----------------------FPGA TX Interface Attributes------------------------- + .TX_DATA_WIDTH (20), + + //-----------------------TX Configurable Driver Attributes------------------------- + .TX_DEEMPH0 (5'b00000), + .TX_DEEMPH1 (5'b00000), + .TX_EIDLE_ASSERT_DELAY (3'b110), + .TX_EIDLE_DEASSERT_DELAY (3'b100), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_DRIVE_MODE ("DIRECT"), + .TX_MARGIN_FULL_0 (7'b1001110), + .TX_MARGIN_FULL_1 (7'b1001001), + .TX_MARGIN_FULL_2 (7'b1000101), + .TX_MARGIN_FULL_3 (7'b1000010), + .TX_MARGIN_FULL_4 (7'b1000000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000100), + .TX_MARGIN_LOW_2 (7'b1000010), + .TX_MARGIN_LOW_3 (7'b1000000), + .TX_MARGIN_LOW_4 (7'b1000000), + + //-----------------------TX Gearbox Attributes-------------------------- + .TXGEARBOX_EN ("FALSE"), + + //-----------------------TX Initialization and Reset Attributes-------------------------- + .TXPCSRESET_TIME (5'b00001), + .TXPMARESET_TIME (5'b00001), + + //-----------------------TX Receiver Detection Attributes-------------------------- + .TX_RXDETECT_CFG (14'h1832), + .TX_RXDETECT_REF (3'b100), + + //--------------------------CPLL Attributes---------------------------- + .CPLL_CFG (24'hBC07DC), + .CPLL_FBDIV (4), + .CPLL_FBDIV_45 (5), + .CPLL_INIT_CFG (24'h00001E), + .CPLL_LOCK_CFG (16'h01E8), + .CPLL_REFCLK_DIV (1), + .RXOUT_DIV (4), + .TXOUT_DIV (4), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + + //------------RX Initialization and Reset Attributes------------- + .RXDFELPMRESET_TIME (7'b0001111), + + //------------RX Equalizer Attributes------------- + .RXLPM_HF_CFG (14'b00000011110000), + .RXLPM_LF_CFG (14'b00000011110000), + .RX_DFE_GAIN_CFG (23'h020FEA), + .RX_DFE_H2_CFG (12'b000000000000), + .RX_DFE_H3_CFG (12'b000001000000), + .RX_DFE_H4_CFG (11'b00011110000), + .RX_DFE_H5_CFG (11'b00011100000), + .RX_DFE_KL_CFG (13'b0000011111110), + .RX_DFE_LPM_CFG (16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DFE_UT_CFG (17'b10001111000000000), + .RX_DFE_VP_CFG (17'b00011111100000011), + + //-----------------------Power-Down Attributes------------------------- + .RX_CLKMUX_PD (1'b1), + .TX_CLKMUX_PD (1'b1), + + //-----------------------FPGA RX Interface Attribute------------------------- + .RX_INT_DATAWIDTH (0), + + //-----------------------FPGA TX Interface Attribute------------------------- + .TX_INT_DATAWIDTH (0), + + //----------------TX Configurable Driver Attributes--------------- + .TX_QPI_STATUS_EN (1'b0), + + //-----------------------RX Equalizer Attributes-------------------------- + .RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2_IN), + .RX_DFE_XYD_CFG (13'b0000000000000), + + //-----------------------TX Configurable Driver Attributes-------------------------- + .TX_PREDRIVER_MODE (1'b0) + + + ) + gtxe2_i + ( + + //-------------------------------- Channel --------------------------------- + .CFGRESET (tied_to_ground_i), + .CLKRSVD (4'b0000), + .DMONITOROUT (), + .GTRESETSEL (tied_to_ground_i), + .GTRSVD (16'b0000000000000000), + .QPLLCLK (QPLLCLK_IN), + .QPLLREFCLK (QPLLREFCLK_IN), + .RESETOVRD (tied_to_ground_i), + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + .DRPADDR (DRPADDR_IN), + .DRPCLK (DRPCLK_IN), + .DRPDI (DRPDI_IN), + .DRPDO (DRPDO_OUT), + .DRPEN (DRPEN_IN), + .DRPRDY (DRPRDY_OUT), + .DRPWE (DRPWE_IN), + //----------------------- Channel - Ref Clock Ports ------------------------ + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (GTREFCLK0_IN), + .GTREFCLK1 (tied_to_ground_i), + .GTREFCLKMONITOR (), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //------------------------------ Channel PLL ------------------------------- + .CPLLFBCLKLOST (CPLLFBCLKLOST_OUT), + .CPLLLOCK (CPLLLOCK_OUT), + .CPLLLOCKDETCLK (CPLLLOCKDETCLK_IN), + .CPLLLOCKEN (tied_to_vcc_i), + .CPLLPD (tied_to_ground_i), + .CPLLREFCLKLOST (CPLLREFCLKLOST_OUT), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (CPLLRESET_IN), + //----------------------------- Eye Scan Ports ----------------------------- + .EYESCANDATAERROR (EYESCANDATAERROR_OUT), + .EYESCANMODE (tied_to_ground_i), + .EYESCANRESET (tied_to_ground_i), + .EYESCANTRIGGER (tied_to_ground_i), + //---------------------- Loopback and Powerdown Ports ---------------------- + .LOOPBACK (LOOPBACK_IN), + .RXPD (RXPD_IN), + .TXPD (TXPD_IN), + //--------------------------- PCS Reserved Ports --------------------------- + .PCSRSVDIN (16'b0000000000000000), + .PCSRSVDIN2 (5'b00000), + .PCSRSVDOUT (), + //--------------------------- PMA Reserved Ports --------------------------- + .PMARSVDIN (5'b00000), + .PMARSVDIN2 (5'b00000), + //----------------------------- Receive Ports ------------------------------ + .RXQPIEN (tied_to_ground_i), + .RXQPISENN (), + .RXQPISENP (), + .RXSYSCLKSEL (2'b00), + .RXUSERRDY (RXUSERRDY_IN), + //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- + .RXDATAVALID (), + .RXGEARBOXSLIP (tied_to_ground_i), + .RXHEADER (), + .RXHEADERVALID (), + .RXSTARTOFSEQ (), + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + .RX8B10BEN (tied_to_vcc_i), + .RXCHARISCOMMA ({rxchariscomma_float_i,RXCHARISCOMMA_OUT}), + .RXCHARISK ({rxcharisk_float_i,RXCHARISK_OUT}), + .RXDISPERR ({rxdisperr_float_i,RXDISPERR_OUT}), + .RXNOTINTABLE ({rxnotintable_float_i,RXNOTINTABLE_OUT}), + //----------------- Receive Ports - Channel Bonding Ports ------------------ + .RXCHANBONDSEQ (), + .RXCHBONDEN (tied_to_ground_i), + .RXCHBONDI (5'b00000), + .RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]), + .RXCHBONDMASTER (tied_to_ground_i), + .RXCHBONDO (), + .RXCHBONDSLAVE (tied_to_ground_i), + //----------------- Receive Ports - Channel Bonding Ports ----------------- + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + //----------------- Receive Ports - Clock Correction Ports ----------------- + .RXCLKCORCNT (RXCLKCORCNT_OUT), + //------------- Receive Ports - Comma Detection and Alignment -------------- + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCOMMADET (), + .RXCOMMADETEN (tied_to_vcc_i), + .RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_IN), + .RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_IN), + .RXSLIDE (tied_to_ground_i), + //--------------------- Receive Ports - PRBS Detection --------------------- + .RXPRBSCNTRESET (tied_to_ground_i), + .RXPRBSERR (), + .RXPRBSSEL (tied_to_ground_vec_i[2:0]), + //----------------- Receive Ports - RX Data Path interface ----------------- + .GTRXRESET (GTRXRESET_IN), + .RXDATA (rxdata_i), + .RXOUTCLK (RXOUTCLK_OUT), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (3'b010), + .RXPCSRESET (RXPCSRESET_IN), + .RXPMARESET (RXPMARESET_IN), + .RXUSRCLK (RXUSRCLK_IN), + .RXUSRCLK2 (RXUSRCLK2_IN), + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + .RXDFEAGCHOLD (RXDFEAGCHOLD_IN), + .RXDFEAGCOVRDEN (tied_to_ground_i), + .RXDFECM1EN (tied_to_ground_i), + .RXDFELFHOLD (tied_to_ground_i), + .RXDFELFOVRDEN (tied_to_vcc_i), + .RXDFELPMRESET (RXDFELPMRESET_IN), + .RXDFETAP2HOLD (tied_to_ground_i), + .RXDFETAP2OVRDEN (tied_to_ground_i), + .RXDFETAP3HOLD (tied_to_ground_i), + .RXDFETAP3OVRDEN (tied_to_ground_i), + .RXDFETAP4HOLD (tied_to_ground_i), + .RXDFETAP4OVRDEN (tied_to_ground_i), + .RXDFETAP5HOLD (tied_to_ground_i), + .RXDFETAP5OVRDEN (tied_to_ground_i), + .RXDFEUTHOLD (tied_to_ground_i), + .RXDFEUTOVRDEN (tied_to_ground_i), + .RXDFEVPHOLD (tied_to_ground_i), + .RXDFEVPOVRDEN (tied_to_ground_i), + .RXDFEVSEN (tied_to_ground_i), + .RXDFEXYDEN (tied_to_ground_i), + .RXDFEXYDHOLD (tied_to_ground_i), + .RXDFEXYDOVRDEN (tied_to_ground_i), + .RXMONITOROUT (RXMONITOROUT_OUT), + .RXMONITORSEL (RXMONITORSEL_IN), + .RXOSHOLD (tied_to_ground_i), + .RXOSOVRDEN (tied_to_ground_i), + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + .GTXRXN (GTXRXN_IN), + .GTXRXP (GTXRXP_IN), + .RXCDRFREQRESET (tied_to_ground_i), + .RXCDRHOLD (tied_to_ground_i), + .RXCDRLOCK (RXCDRLOCK_OUT), + .RXCDROVRDEN (tied_to_ground_i), + .RXCDRRESET (tied_to_ground_i), + .RXCDRRESETRSV (tied_to_ground_i), + .RXELECIDLE (), + .RXELECIDLEMODE (2'b11), + .RXLPMHFHOLD (tied_to_ground_i), + .RXLPMHFOVRDEN (tied_to_ground_i), + .RXLPMLFHOLD (tied_to_ground_i), + .RXLPMLFKLOVRDEN (tied_to_ground_i), + .RXOOBRESET (tied_to_ground_i), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + .RXBUFRESET (RXBUFRESET_IN), + .RXBUFSTATUS (RXBUFSTATUS_OUT), + .RXDDIEN (tied_to_ground_i), + .RXDLYBYPASS (tied_to_vcc_i), + .RXDLYEN (tied_to_ground_i), + .RXDLYOVRDEN (tied_to_ground_i), + .RXDLYSRESET (tied_to_ground_i), + .RXDLYSRESETDONE (), + .RXPHALIGN (tied_to_ground_i), + .RXPHALIGNDONE (), + .RXPHALIGNEN (tied_to_ground_i), + .RXPHDLYPD (tied_to_ground_i), + .RXPHDLYRESET (tied_to_ground_i), + .RXPHMONITOR (), + .RXPHOVRDEN (tied_to_ground_i), + .RXPHSLIPMONITOR (), + .RXSTATUS (), + //---------------------- Receive Ports - RX Equalizer ---------------------- + .RXLPMEN (tied_to_ground_i), + //---------------------- Receive Ports - RX PLL Ports ---------------------- + .RXRATE (tied_to_ground_vec_i[2:0]), + .RXRATEDONE (), + .RXRESETDONE (RXRESETDONE_OUT), + //------------ Receive Ports - RX Pipe Control for PCI Express ------------- + .PHYSTATUS (), + .RXVALID (), + //--------------- Receive Ports - RX Polarity Control Ports ---------------- + .RXPOLARITY (tied_to_ground_i), + //------------------- Receive Ports - RX Ports for SATA -------------------- + .RXCOMINITDET (), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + //----------------------------- Transmit Ports ----------------------------- + .SETERRSTATUS (tied_to_ground_i), + .TSTIN (20'b11111111111111111111), + .TSTOUT (), + .TXPHDLYTSTCLK (tied_to_ground_i), + .TXPOSTCURSOR (5'b00000), + .TXPOSTCURSORINV (tied_to_ground_i), + .TXPRECURSOR (tied_to_ground_vec_i[4:0]), + .TXPRECURSORINV (tied_to_ground_i), + .TXQPIBIASEN (tied_to_ground_i), + .TXQPISENN (), + .TXQPISENP (), + .TXQPISTRONGPDOWN (tied_to_ground_i), + .TXQPIWEAKPUP (tied_to_ground_i), + .TXSYSCLKSEL (2'b00), + .TXUSERRDY (TXUSERRDY_IN), + //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ + .TXGEARBOXREADY (), + .TXHEADER (tied_to_ground_vec_i[2:0]), + .TXSEQUENCE (tied_to_ground_vec_i[6:0]), + .TXSTARTSEQ (tied_to_ground_i), + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + .TX8B10BBYPASS (tied_to_ground_vec_i[7:0]), + .TX8B10BEN (tied_to_vcc_i), + .TXCHARDISPMODE ({tied_to_ground_vec_i[5:0],TXCHARDISPMODE_IN}), + .TXCHARDISPVAL ({tied_to_ground_vec_i[5:0],TXCHARDISPVAL_IN}), + .TXCHARISK ({tied_to_ground_vec_i[5:0],TXCHARISK_IN}), + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + .TXBUFSTATUS (TXBUFSTATUS_OUT), + .TXDLYBYPASS (tied_to_vcc_i), + .TXDLYEN (tied_to_ground_i), + .TXDLYHOLD (tied_to_ground_i), + .TXDLYOVRDEN (tied_to_ground_i), + .TXDLYSRESET (tied_to_ground_i), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (tied_to_ground_i), + .TXPHALIGN (tied_to_ground_i), + .TXPHALIGNDONE (), + .TXPHALIGNEN (tied_to_ground_i), + .TXPHDLYPD (tied_to_ground_i), + .TXPHDLYRESET (tied_to_ground_i), + .TXPHINIT (tied_to_ground_i), + .TXPHINITDONE (), + .TXPHOVRDEN (tied_to_ground_i), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .GTTXRESET (GTTXRESET_IN), + .TXDATA (txdata_i), + .TXOUTCLK (TXOUTCLK_OUT), + .TXOUTCLKFABRIC (TXOUTCLKFABRIC_OUT), + .TXOUTCLKPCS (TXOUTCLKPCS_OUT), + .TXOUTCLKSEL (3'b100), + .TXPCSRESET (TXPCSRESET_IN), + .TXPMARESET (tied_to_ground_i), + .TXUSRCLK (TXUSRCLK_IN), + .TXUSRCLK2 (TXUSRCLK2_IN), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GTXTXN (GTXTXN_OUT), + .GTXTXP (GTXTXP_OUT), + .TXBUFDIFFCTRL (3'b100), + .TXDIFFCTRL (4'b1010), + .TXDIFFPD (tied_to_ground_i), + .TXINHIBIT (tied_to_ground_i), + .TXMAINCURSOR (7'b0000000), + .TXPDELECIDLEMODE (tied_to_ground_i), + .TXPISOPD (tied_to_ground_i), + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + .TXRATE (tied_to_ground_vec_i[2:0]), + .TXRATEDONE (), + .TXRESETDONE (TXRESETDONE_OUT), + //------------------- Transmit Ports - TX PRBS Generator ------------------- + .TXPRBSFORCEERR (tied_to_ground_i), + .TXPRBSSEL (tied_to_ground_vec_i[2:0]), + //------------------ Transmit Ports - TX Polarity Control ------------------ + .TXPOLARITY (tied_to_ground_i), + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + .TXDEEMPH (tied_to_ground_i), + .TXDETECTRX (tied_to_ground_i), + .TXELECIDLE (TXELECIDLE_IN), + .TXMARGIN (tied_to_ground_vec_i[2:0]), + .TXSWING (tied_to_ground_i), + //------------------- Transmit Ports - TX Ports for SATA ------------------- + .TXCOMFINISH (), + .TXCOMINIT (tied_to_ground_i), + .TXCOMSAS (tied_to_ground_i), + .TXCOMWAKE (tied_to_ground_i) + + ); + +endmodule + + diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v new file mode 100644 index 000000000..cd3a65135 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v @@ -0,0 +1,617 @@ +//------------------------------------------------------------------------------ +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 2.4 +// \ \ Application : 7 Series FPGAs Transceivers Wizard +// / / Filename : gige_sfp_mdio_gtwizard_init.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +// Description : This module instantiates the modules required for +// reset and initialisation of the Transceiver +// +// Module GTWIZARD_init +// Generated by Xilinx 7 Series FPGAs Transceivers Wizard +// +// +// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +`timescale 1ns / 1ps +`define DLY #1 + +//***********************************Entity Declaration************************ + +module gige_sfp_mdio_GTWIZARD_init # +( + parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE", // Simulation setting for GT SecureIP model + parameter EXAMPLE_SIMULATION = 0, // Set to 1 for simulation + parameter EQ_MODE = "DFE", + parameter EXAMPLE_USE_CHIPSCOPE = 0 // Set to 1 to use Chipscope to drive resets + +) +( + + input SYSCLK_IN, + input SOFT_RESET_IN, + output GT0_TX_FSM_RESET_DONE_OUT, + output GT0_RX_FSM_RESET_DONE_OUT, + input GT0_DATA_VALID_IN, + + //_________________________________________________________________________ + //GT0 (X1Y4) + //____________________________CHANNEL PORTS________________________________ + //----------------------- Channel - Ref Clock Ports ------------------------ + input GT0_GTREFCLK0_IN, + //------------------------------ Channel PLL ------------------------------- + output GT0_CPLLFBCLKLOST_OUT, + output GT0_CPLLLOCK_OUT, + input GT0_CPLLLOCKDETCLK_IN, + input GT0_CPLLRESET_IN, + //----------------------------- Eye Scan Ports ----------------------------- + output GT0_EYESCANDATAERROR_OUT, + //---------------------- Loopback and Powerdown Ports ---------------------- + input [2:0] GT0_LOOPBACK_IN, + input [1:0] GT0_RXPD_IN, + input [1:0] GT0_TXPD_IN, + //----------------------------- Receive Ports ------------------------------ + input GT0_RXUSERRDY_IN, + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + output [1:0] GT0_RXCHARISCOMMA_OUT, + output [1:0] GT0_RXCHARISK_OUT, + output [1:0] GT0_RXDISPERR_OUT, + output [1:0] GT0_RXNOTINTABLE_OUT, + //----------------- Receive Ports - Clock Correction Ports ----------------- + output [1:0] GT0_RXCLKCORCNT_OUT, + //------------- Receive Ports - Comma Detection and Alignment -------------- + input GT0_RXMCOMMAALIGNEN_IN, + input GT0_RXPCOMMAALIGNEN_IN, + //----------------- Receive Ports - RX Data Path interface ----------------- + input GT0_GTRXRESET_IN, + output [15:0] GT0_RXDATA_OUT, + output GT0_RXOUTCLK_OUT, + input GT0_RXUSRCLK_IN, + input GT0_RXUSRCLK2_IN, + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + input GT0_RXDFELPMRESET_IN, + output [6:0] GT0_RXMONITOROUT_OUT, + input [1:0] GT0_RXMONITORSEL_IN, + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + input GT0_GTXRXN_IN, + input GT0_GTXRXP_IN, + output GT0_RXCDRLOCK_OUT, + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + input GT0_RXBUFRESET_IN, + output [2:0] GT0_RXBUFSTATUS_OUT, + //---------------------- Receive Ports - RX PLL Ports ---------------------- + output GT0_RXRESETDONE_OUT, + //----------------------------- Transmit Ports ----------------------------- + input GT0_TXUSERRDY_IN, + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + input [1:0] GT0_TXCHARDISPMODE_IN, + input [1:0] GT0_TXCHARDISPVAL_IN, + input [1:0] GT0_TXCHARISK_IN, + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + output [1:0] GT0_TXBUFSTATUS_OUT, + //---------------- Transmit Ports - TX Data Path interface ----------------- + input GT0_GTTXRESET_IN, + input [15:0] GT0_TXDATA_IN, + output GT0_TXOUTCLK_OUT, + output GT0_TXOUTCLKFABRIC_OUT, + output GT0_TXOUTCLKPCS_OUT, + input GT0_TXUSRCLK_IN, + input GT0_TXUSRCLK2_IN, + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + output GT0_GTXTXN_OUT, + output GT0_GTXTXP_OUT, + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + output GT0_TXRESETDONE_OUT, + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + input GT0_TXELECIDLE_IN, + + + //____________________________COMMON PORTS________________________________ + //-------------------- Common Block - Ref Clock Ports --------------------- + input GT0_GTREFCLK0_COMMON_IN, + //----------------------- Common Block - QPLL Ports ------------------------ + output GT0_QPLLLOCK_OUT, + input GT0_QPLLLOCKDETCLK_IN, + input GT0_QPLLRESET_IN + + + +); + + + +//***********************************Parameter Declarations******************** + + parameter STABLE_CLOCK_PERIOD = 5; //Period of the stable clock driving this state-machine, unit is [ns] + + //Typical CDRLOCK Time is 50,000UI, as per DS183 + parameter RX_CDRLOCK_TIME = (EXAMPLE_SIMULATION == 1) ? 1000 : 50000/1.25; + + integer WAIT_TIME_CDRLOCK = RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; + + parameter integer LPM_ADAPT_LOCK_TIMER = (EXAMPLE_SIMULATION == 1) ? 5 : (13*100)/1.25; + + parameter integer DFE_ADAPT_LOCK_TIMER = (13*100)/1.25; + +//-------------------------- GT Wrapper Wires ------------------------------ + wire gt0_cpllreset_i; + wire gt0_cpllreset_t; + wire gt0_cpllrefclklost_i; + wire gt0_cplllock_i; + wire gt0_txresetdone_i; + wire gt0_rxresetdone_i; + wire gt0_gttxreset_i; + wire gt0_gttxreset_t; + wire gt0_gtrxreset_i; + wire gt0_gtrxreset_t; + wire gt0_txpcsreset_i; + wire gt0_rxpcsreset_i; + wire gt0_rxpmareset_i; + wire gt0_rxdfelpmreset_i; + wire gt0_txuserrdy_i; + wire gt0_txuserrdy_t; + wire gt0_rxuserrdy_i; + wire gt0_rxuserrdy_t; + + wire gt0_rxdfeagchold_i; + wire gt0_rxdfelfhold_i; + wire gt0_rxlpmlfhold_i; + wire gt0_rxlpmhfhold_i; + + + + wire [8:0] gt0_drpaddr_i; + wire [15:0] gt0_drpdi_i; + wire [15:0] gt0_drpdo_o; + wire gt0_drpen_i; + wire gt0_drpwe_i; + wire gt0_drprdy_o; + + wire [8:0] gt0_drpaddr_int; + wire [15:0] gt0_drpdi_int; + wire [15:0] gt0_drpdo_int; + wire gt0_drpen_int; + wire gt0_drpwe_int; + wire gt0_drprdy_int; + + wire [6:0] gt0_rxmonitorout_o; + wire [1:0] gt0_rxmonitorsel_i; + wire gt0_adapt_done; + + + wire gt0_qpllreset_i; + wire gt0_qpllreset_t; + wire gt0_qpllrefclklost_i; + wire gt0_qplllock_i; + +//------------------------------- Global Signals ----------------------------- + wire tied_to_ground_i; + wire tied_to_vcc_i; + + wire gt0_rxoutclk_i; + wire gt0_rxoutclk_i_buf; + wire gt0_rxoutclk_i_bufmr; + wire gt0_recclk_stable_i; + wire gt0_recclk_mon_i; + wire gt0_recclk_monitor_restart_i; + + integer rx_cdrlock_counter= 0; + reg rx_cdrlocked; + + wire gt0_gttxreset_gt; + wire gt0_gtrxreset_gt; + +//**************************** Main Body of Code ******************************* + // Static signal Assigments + assign tied_to_ground_i = 1'b0; + assign tied_to_vcc_i = 1'b1; + assign gt0_gttxreset_gt = gt0_gttxreset_t || GT0_GTTXRESET_IN; + assign gt0_gtrxreset_gt = gt0_gtrxreset_t || GT0_GTRXRESET_IN; + // Place the Rx recovered clock on a Global Clock Buffer (it may be possible + // to switch this for a BUFHCE) + BUFG rxrecclkbufg ( + .I (gt0_rxoutclk_i), + .O (gt0_rxoutclk_i_buf) + ); +// ----------------------------- The GT Wrapper ----------------------------- + + // Use the instantiation template in the example directory to add the GT wrapper to your design. + // In this example, the wrapper is wired up for basic operation with a frame generator and frame + // checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is + // enabled, bonding should occur after alignment. + + + gige_sfp_mdio_GTWIZARD # + ( + .WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP) + ) + GTWIZARD_i + ( + + //_____________________________________________________________________ + //_____________________________________________________________________ + //GT0 (X1Y4) + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + .GT0_DRPADDR_IN (9'b0), + .GT0_DRPCLK_IN (1'b0), + .GT0_DRPDI_IN (16'b0), + .GT0_DRPDO_OUT (), + .GT0_DRPEN_IN (1'b0), + .GT0_DRPRDY_OUT (), + .GT0_DRPWE_IN (1'b0), + + //----------------------- Channel - Ref Clock Ports ------------------------ + .GT0_GTREFCLK0_IN (GT0_GTREFCLK0_IN), + //------------------------------ Channel PLL ------------------------------- + .GT0_CPLLFBCLKLOST_OUT (GT0_CPLLFBCLKLOST_OUT), + .GT0_CPLLLOCK_OUT (gt0_cplllock_i), + .GT0_CPLLLOCKDETCLK_IN (GT0_CPLLLOCKDETCLK_IN), + .GT0_CPLLREFCLKLOST_OUT (gt0_cpllrefclklost_i), + .GT0_CPLLRESET_IN (gt0_cpllreset_i), + //----------------------------- Eye Scan Ports ----------------------------- + .GT0_EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT), + //---------------------- Loopback and Powerdown Ports ---------------------- + .GT0_LOOPBACK_IN (GT0_LOOPBACK_IN), + .GT0_RXPD_IN (GT0_RXPD_IN), + .GT0_TXPD_IN (GT0_TXPD_IN), + //----------------------------- Receive Ports ------------------------------ + .GT0_RXUSERRDY_IN (gt0_rxuserrdy_i), + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + .GT0_RXCHARISCOMMA_OUT (GT0_RXCHARISCOMMA_OUT), + .GT0_RXCHARISK_OUT (GT0_RXCHARISK_OUT), + .GT0_RXDISPERR_OUT (GT0_RXDISPERR_OUT), + .GT0_RXNOTINTABLE_OUT (GT0_RXNOTINTABLE_OUT), + //----------------- Receive Ports - Clock Correction Ports ----------------- + .GT0_RXCLKCORCNT_OUT (GT0_RXCLKCORCNT_OUT), + //------------- Receive Ports - Comma Detection and Alignment -------------- + .GT0_RXMCOMMAALIGNEN_IN (GT0_RXMCOMMAALIGNEN_IN), + .GT0_RXPCOMMAALIGNEN_IN (GT0_RXPCOMMAALIGNEN_IN), + //----------------- Receive Ports - RX Data Path interface ----------------- + .GT0_GTRXRESET_IN (gt0_gtrxreset_gt), + .GT0_RXDATA_OUT (GT0_RXDATA_OUT), + .GT0_RXOUTCLK_OUT (gt0_rxoutclk_i), + .GT0_RXPCSRESET_IN (gt0_rxpcsreset_i), + .GT0_RXPMARESET_IN (gt0_rxpmareset_i), + .GT0_RXUSRCLK_IN (GT0_RXUSRCLK_IN), + .GT0_RXUSRCLK2_IN (GT0_RXUSRCLK2_IN), + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + .GT0_RXDFEAGCHOLD_IN (gt0_rxdfeagchold_i), + .GT0_RXDFELPMRESET_IN (gt0_rxdfelpmreset_i), + .GT0_RXMONITOROUT_OUT (gt0_rxmonitorout_o), + .GT0_RXMONITORSEL_IN (2'b0), + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + .GT0_GTXRXN_IN (GT0_GTXRXN_IN), + .GT0_GTXRXP_IN (GT0_GTXRXP_IN), + .GT0_RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + .GT0_RXBUFRESET_IN (GT0_RXBUFRESET_IN), + .GT0_RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT), + //---------------------- Receive Ports - RX PLL Ports ---------------------- + .GT0_RXRESETDONE_OUT (gt0_rxresetdone_i), + //----------------------------- Transmit Ports ----------------------------- + .GT0_TXUSERRDY_IN (gt0_txuserrdy_i), + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + .GT0_TXCHARDISPMODE_IN (GT0_TXCHARDISPMODE_IN), + .GT0_TXCHARDISPVAL_IN (GT0_TXCHARDISPVAL_IN), + .GT0_TXCHARISK_IN (GT0_TXCHARISK_IN), + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + .GT0_TXBUFSTATUS_OUT (GT0_TXBUFSTATUS_OUT), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .GT0_GTTXRESET_IN (gt0_gttxreset_gt), + .GT0_TXDATA_IN (GT0_TXDATA_IN), + .GT0_TXOUTCLK_OUT (GT0_TXOUTCLK_OUT), + .GT0_TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT), + .GT0_TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT), + .GT0_TXPCSRESET_IN (gt0_txpcsreset_i), + .GT0_TXUSRCLK_IN (GT0_TXUSRCLK_IN), + .GT0_TXUSRCLK2_IN (GT0_TXUSRCLK2_IN), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GT0_GTXTXN_OUT (GT0_GTXTXN_OUT), + .GT0_GTXTXP_OUT (GT0_GTXTXP_OUT), + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + .GT0_TXRESETDONE_OUT (gt0_txresetdone_i), + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + .GT0_TXELECIDLE_IN (GT0_TXELECIDLE_IN), + + + + + //____________________________COMMON PORTS________________________________ + //-------------------- Common Block - Ref Clock Ports --------------------- + .GT0_GTREFCLK0_COMMON_IN (GT0_GTREFCLK0_COMMON_IN), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (gt0_qplllock_i), + .GT0_QPLLLOCKDETCLK_IN (GT0_QPLLLOCKDETCLK_IN), + .GT0_QPLLREFCLKLOST_OUT (gt0_qpllrefclklost_i), + .GT0_QPLLRESET_IN (gt0_qpllreset_i) + + + + ); + + assign gt0_rxpcsreset_i = tied_to_ground_i; + assign gt0_txpcsreset_i = tied_to_ground_i; + + assign gt0_rxpmareset_i = tied_to_ground_i; + assign gt0_rxdfelpmreset_i = tied_to_ground_i; + + + + assign GT0_CPLLLOCK_OUT = gt0_cplllock_i; + assign GT0_TXRESETDONE_OUT = gt0_txresetdone_i; + assign GT0_RXRESETDONE_OUT = gt0_rxresetdone_i; + assign GT0_RXOUTCLK_OUT = gt0_rxoutclk_i_buf; + assign GT0_QPLLLOCK_OUT = gt0_qplllock_i; +generate +if (EXAMPLE_USE_CHIPSCOPE == 1) +begin : chipscope + assign gt0_cpllreset_i = GT0_CPLLRESET_IN; + assign gt0_gttxreset_i = GT0_GTTXRESET_IN; + assign gt0_gtrxreset_i = GT0_GTRXRESET_IN; + assign gt0_txuserrdy_i = GT0_TXUSERRDY_IN; + assign gt0_rxuserrdy_i = GT0_RXUSERRDY_IN; + assign gt0_qpllreset_i = GT0_QPLLRESET_IN; +end +endgenerate + +generate +if (EXAMPLE_USE_CHIPSCOPE == 0) +begin : no_chipscope + assign gt0_cpllreset_i = gt0_cpllreset_t; + assign gt0_gttxreset_i = gt0_gttxreset_t; + assign gt0_gtrxreset_i = gt0_gtrxreset_t; + assign gt0_txuserrdy_i = gt0_txuserrdy_t; + assign gt0_rxuserrdy_i = gt0_rxuserrdy_t; + assign gt0_qpllreset_i = gt0_qpllreset_t; +end +endgenerate + + +gige_sfp_mdio_TX_STARTUP_FSM # + ( + .GT_TYPE ("GTX"), //GTX or GTH or GTP + .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD), // Period of the stable clock driving this state-machine, unit is [ns] + .RETRY_COUNTER_BITWIDTH (8), + .TX_QPLL_USED ("FALSE"), // the TX and RX Reset FSMs must + .RX_QPLL_USED ("FALSE"), // share these two generic values + .PHASE_ALIGNMENT_MANUAL ("FALSE") // Decision if a manual phase-alignment is necessary or the automatic + // is enough. For single-lane applications the automatic alignment is + // sufficient + ) +gt0_txresetfsm_i + ( + .STABLE_CLOCK (SYSCLK_IN), + .TXUSERCLK (GT0_TXUSRCLK_IN), + .SOFT_RESET (SOFT_RESET_IN), + .QPLLREFCLKLOST (tied_to_ground_i), + .CPLLREFCLKLOST (gt0_cpllrefclklost_i), + .QPLLLOCK (tied_to_vcc_i), + .CPLLLOCK (gt0_cplllock_i), + .TXRESETDONE (gt0_txresetdone_i), + .MMCM_LOCK (tied_to_vcc_i), + .GTTXRESET (gt0_gttxreset_t), + .MMCM_RESET (), + .QPLL_RESET (), + .CPLL_RESET (gt0_cpllreset_t), + .TX_FSM_RESET_DONE (GT0_TX_FSM_RESET_DONE_OUT), + .TXUSERRDY (gt0_txuserrdy_t), + .RUN_PHALIGNMENT (), + .RESET_PHALIGNMENT (), + .PHALIGNMENT_DONE (tied_to_vcc_i), + .RETRY_COUNTER () + ); + + + + + + +gige_sfp_mdio_RX_STARTUP_FSM # + ( + .EXAMPLE_SIMULATION (EXAMPLE_SIMULATION), + .GT_TYPE ("GTX"), //GTX or GTH or GTP + .EQ_MODE (EQ_MODE), //Rx Equalization Mode - Set to DFE or LPM + .STABLE_CLOCK_PERIOD (STABLE_CLOCK_PERIOD), //Period of the stable clock driving this state-machine, unit is [ns] + .RETRY_COUNTER_BITWIDTH (8), + .TX_QPLL_USED ("FALSE"), // the TX and RX Reset FSMs must + .RX_QPLL_USED ("FALSE"), // share these two generic values + .PHASE_ALIGNMENT_MANUAL ("FALSE") // Decision if a manual phase-alignment is necessary or the automatic + // is enough. For single-lane applications the automatic alignment is + // sufficient + ) +gt0_rxresetfsm_i + ( + .STABLE_CLOCK (SYSCLK_IN), + .RXUSERCLK (GT0_RXUSRCLK_IN), + .SOFT_RESET (SOFT_RESET_IN), + .QPLLREFCLKLOST (tied_to_ground_i), + .CPLLREFCLKLOST (gt0_cpllrefclklost_i), + .QPLLLOCK (tied_to_vcc_i), + .CPLLLOCK (gt0_cplllock_i), + .RXRESETDONE (gt0_rxresetdone_i), + .MMCM_LOCK (tied_to_vcc_i), + .RECCLK_STABLE (gt0_recclk_stable_i), + .RECCLK_MONITOR_RESTART (gt0_recclk_monitor_restart_i), + .DATA_VALID (GT0_DATA_VALID_IN), + .TXUSERRDY (tied_to_vcc_i), + .GTRXRESET (gt0_gtrxreset_t), + .MMCM_RESET (), + .QPLL_RESET (), + .CPLL_RESET (), + .RX_FSM_RESET_DONE (GT0_RX_FSM_RESET_DONE_OUT), + .RXUSERRDY (gt0_rxuserrdy_t), + .RUN_PHALIGNMENT (), + .RESET_PHALIGNMENT (), + .PHALIGNMENT_DONE (tied_to_vcc_i), + .RXDFEAGCHOLD (gt0_rxdfeagchold_i), + .RXDFELFHOLD (gt0_rxdfelfhold_i), + .RXLPMLFHOLD (gt0_rxlpmlfhold_i), + .RXLPMHFHOLD (gt0_rxlpmhfhold_i), + .RETRY_COUNTER () + ); + + +//generate +//if (EQ_MODE=="DFE") +//GTWIZARD_ADAPT_TOP_DFE # +// ( +// .AGC_TIMER (DFE_ADAPT_LOCK_TIMER) +// ) +//gt0_adapt_dfe_i +// ( +// .EN(1'b1), +// .CTLE3_COMP_EN(1'b1), +// .GTRXRESET(gt0_gtrxreset_i), //reset going to the GT, coming from either chipscope or TB +// .RXPMARESET(gt0_rxpmareset_i),//tied to ground, going to GT +// .RXDFELPMRESET(gt0_rxdfelpmreset_i),//tied to groun, going to GT +// .DCLK(GT0_DRPCLK_IN), +// .DO(gt0_drpdo_int), +// .DRDY(gt0_drprdy_int), +// .DADDR(gt0_drpaddr_int),//out 8:0 +// .DI(gt0_drpdi_int), //out +// .DEN(gt0_drpen_int), //out +// .DWE(gt0_drpwe_int), //out +// .RXMONITOR(gt0_rxmonitorout_o), +// .RXMONITORSEL(gt0_rxmonitorsel_i), //out +// .AGCHOLD(gt0_rxdfeagchold_i),//out +// .KLHOLD(), //out +// .KHHOLD(),//out +// .DONE(gt0_adapt_done),//out +// .DEBUG()//out +// ); +//else if (EQ_MODE=="LPM") +//GTWIZARD_ADAPT_TOP_LPM # +// ( +// .TIMER (LPM_ADAPT_LOCK_TIMER) +// ) +//gt0_adapt_lpm_i +// ( +// .EN(1'b1), +// .GTRXRESET(gt0_gtrxreset_i), //reset going to the GT, coming from either chipscope or TB +// .RXPMARESET(gt0_rxpmareset_i),//tied to ground, going to GT +// .RXDFELPMRESET(gt0_rxdfelpmreset_i),//tied to groun, going to GT +// .DCLK(GT0_DRPCLK_IN), +// .DO(gt0_drpdo_int), +// .DRDY(gt0_drprdy_int), +// .DADDR(gt0_drpaddr_int), +// .DI(gt0_drpdi_int), +// .DEN(gt0_drpen_int), +// .DWE(gt0_drpwe_int), +// .KLHOLD(), +// .KHHOLD(), +// .DONE(gt0_adapt_done), +// .DEBUG() +// ); +//endgenerate +// +// assign gt0_drpaddr_i = gt0_adapt_done ? GT0_DRPADDR_IN : gt0_drpaddr_int; +// assign gt0_drpdi_i = gt0_adapt_done ? GT0_DRPDI_IN : gt0_drpdi_int; +// assign gt0_drpen_i = gt0_adapt_done ? GT0_DRPEN_IN : gt0_drpen_int; +// assign gt0_drpwe_i = gt0_adapt_done ? GT0_DRPWE_IN : gt0_drpwe_int; +// assign GT0_DRPDO_OUT = gt0_adapt_done ? gt0_drpdo_o : 16'b0; +// assign GT0_DRPRDY_OUT = gt0_adapt_done ? gt0_drprdy_o : 1'b0; +// +// assign gt0_drpdo_int = gt0_drpdo_o; +// assign gt0_drprdy_int = gt0_drprdy_o; +// + + + always @(posedge SYSCLK_IN) + begin + if(gt0_gtrxreset_i) + begin + rx_cdrlocked <= `DLY 1'b0; + rx_cdrlock_counter <= `DLY 0; + end + else if (rx_cdrlock_counter == WAIT_TIME_CDRLOCK) + begin + rx_cdrlocked <= `DLY 1'b1; + rx_cdrlock_counter <= `DLY rx_cdrlock_counter; + end + else + rx_cdrlock_counter <= `DLY rx_cdrlock_counter + 1; + end + +//The Recovered Clock Monitor can be used, only when the +//Reference Clock frequency matches the Recovered Clock Frequency. +//For all other cases, CDR Lock time of 50,000UI is used as an +//indicator for Recovered Clock stable +gige_sfp_mdio_RECCLK_MONITOR # + ( + .COUNTER_UPPER_VALUE (15), //ppm counter. For 2^20 cntr. + .GCLK_COUNTER_UPPER_VALUE (15), //ppm counter. For 2^20 cntr. + .CLOCK_PULSES (5000), + .EXAMPLE_SIMULATION (EXAMPLE_SIMULATION) + ) +gt0_rx_recclk_mon_i + ( + .GT_RST (gt0_gtrxreset_i), + .REF_CLK (GT0_GTREFCLK0_IN), + .RX_REC_CLK0 (gt0_rxoutclk_i_buf), + .SYSTEM_CLK (SYSCLK_IN), + .PLL_LK_DET (tied_to_vcc_i), + .RECCLK_STABLE (gt0_recclk_mon_i), + .EXEC_RESTART (gt0_recclk_monitor_restart_i) + ); + +assign gt0_recclk_stable_i = rx_cdrlocked; + + + + + + + +endmodule + + diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v new file mode 100644 index 000000000..caa0e4c26 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v @@ -0,0 +1,410 @@ +////////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 2.4 +// \ \ Application : 7 Series FPGAs Transceivers Wizard +// / / Filename : recclk_monitor.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +// +// Description : This module is the ppm monitor between the +// GT RxRecClk and the reference clock +// +// This module will declare that the Rx RECCLK is stable if the +// recovered clock is within +/-5000PPM of the reference clock. +// +// +// There are 3 counters running on local clocks for both +// recovered clocks and one for the reference clock. The +// COUNTER_UPPER_VALUE parameter is the width of these +// counters. The PPM offset is checked when these counters +// roll over. +// +// There is also a counter running on the system clock. +// This can be running at a much lower frequency and is +// running on a BUFG. +// +// To set the parameters correctly here is what you need to +// do. Lets assume taht the reference and recovered +// clocks are running at 156MHz and the system clock is +// running at 50MHz. +// +// To ensure that the interval is long enough we want to +// to make the COUNTER_UPPER_VALUE to be reasonable. The +// CLOCK_PULSES is the number of sytem clock cycles we can +// expect to be off based on these frequencies: +// +// Example: Rec Clk and Ref Clk 156MHz, System clock 50MHz +// PPM Offset to tolerate +/- 5000PPM +// +// COUNTER_UPPER_VALUE = 15 -> 2^15 counter = 32768 +// GCLK_COUNTER_UPPER_VALUE = 15 -> 2^15 counter = 32768 +// +// PPM OFFSET = 5000 => 32768 * 5000/1000000 = 164 +// +// Now we are using the system clock to do the +// calculations, therfore we need to scale the PPM_OFFSET +// accordingly. +// +// CLOCK_PULSES = PPM_OFFSET * sysclk_freq/refclk_freq +// = 164 * 50/156 = 52 +// +// +// When the counters are checked if they are off by less +// than 52, we can delcare that the particular RECCLK is +// stable. +// +// All FFs that have the _meta are metastability FFs and +// can be ignored from a timing perspective. The following +// constraint can be added to the UCF to ensure that they +// are ignored: +// +// INST "*_meta" TNM = "METASTABILITY_FFS"; +// TIMESPEC "TS_METASTABILITY" = FROM FFS TO "METASTABILITY_FFS" TIG; +// +// Module gige_sfp_mdio_RECCLK_MONITOR +// Generated by Xilinx 7 Series FPGAs Transceivers Wizard +// +// +// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +//******************************************************************************* + + +`timescale 1ns / 1ps +`define DLY #1 + + +module gige_sfp_mdio_RECCLK_MONITOR # +( + parameter COUNTER_UPPER_VALUE = 20, //ppm counter. For 2^20 counter. + parameter GCLK_COUNTER_UPPER_VALUE = 20, //ppm counter. For 2^20 counter. + parameter CLOCK_PULSES = 5000, + parameter EXAMPLE_SIMULATION = 0 +) +( + input wire GT_RST, // Active high async reset. + input wire REF_CLK, + input wire RX_REC_CLK0, + input wire SYSTEM_CLK, + input wire PLL_LK_DET, + output wire RECCLK_STABLE, + output reg EXEC_RESTART +); + + +//=============================================================================== +// Register/Wire declaration +//=============================================================================== +localparam WAIT_FOR_LOCK = 6'b00_0001; +localparam REFCLK_EVENT = 6'b00_0010; +localparam CALC_PPM_DIFF = 6'b00_0100; +localparam CHECK_SIGN = 6'b00_1000; +localparam COMP_CNTR = 6'b01_0000; +localparam RESTART = 6'b10_0000; + +reg [COUNTER_UPPER_VALUE -1 :0] ref_clk_cnt; +reg [COUNTER_UPPER_VALUE -1 :0] rec_clk0_cnt; +reg [2:1] rec_clk0_msb; +reg [2:1] ref_clk_msb; +reg rec_clk_0_msb_meta /*synthesis syn_keep = 1 */; +reg ref_clk_msb_meta /*synthesis syn_keep = 1 */; +reg [GCLK_COUNTER_UPPER_VALUE -1 :0] sys_clk_counter; +reg [GCLK_COUNTER_UPPER_VALUE -1 :0] rec_clk0_compare_cnt_latch; +reg [GCLK_COUNTER_UPPER_VALUE -1 :0] ref_clk_compare_cnt_latch; + +reg g_clk_rst_meta /*synthesis syn_keep = 1 */; +reg g_clk_rst_sync; +reg gt_pll_locked_meta /*synthesis syn_keep = 1 */; +reg gt_pll_locked_sync; + +reg reset_logic_rec0_meta /*synthesis syn_keep = 1 */; +reg reset_logic_rec0_sync; +reg reset_logic_ref_meta /*synthesis syn_keep = 1 */; +reg reset_logic_ref_sync; + + +reg [5:0] state; + +reg rec_clk0_edge_event; +reg [1:0] ref_clk_edge_event; +reg [GCLK_COUNTER_UPPER_VALUE -1 : 0] ppm0; +reg recclk_stable0_int; +reg recclk_stable0; +reg [3:0] reset_logic; +wire rec_clk0_edge; +wire ref_clk_edge; +reg [1:0] ref_clk_edge_rt; + +wire g_clk_rst; + + +//=============================================================================== +// Main Logic +//=============================================================================== +always @ (posedge RX_REC_CLK0) begin + reset_logic_rec0_meta <= `DLY reset_logic[3]; + reset_logic_rec0_sync <= `DLY reset_logic_rec0_meta; +end + +always @ (posedge RX_REC_CLK0) begin + if (reset_logic_rec0_sync) begin + rec_clk0_cnt <= `DLY 'h0; + end + else begin + rec_clk0_cnt <= `DLY rec_clk0_cnt +1; + end +end + + +always @ (posedge REF_CLK) begin + reset_logic_ref_meta <= `DLY reset_logic[3]; + reset_logic_ref_sync <= `DLY reset_logic_ref_meta; +end + +always @ (posedge REF_CLK) begin + if (reset_logic_ref_sync) + ref_clk_cnt <= `DLY 'h0; + else begin + ref_clk_cnt <= `DLY ref_clk_cnt +1; + end +end +//=============================================================================== +// PPM Monitor +//=============================================================================== +/* +We will also need 3 counters running on a global clock, one corresponding to each of the local counters. For this example I will use a 50MHz clock, but it can be anything. We use the global clock to sample the 20th bit of the local counter, it has to be sampled twice for metastability. Whenever we detect a falling edge on that signal, it means that the counter has rolled over. We use this to latch the current count value to FFs and reset the counter. Now you have the amount of time it took to count ~1M clock cycles. In an ideal world, this would be 6.7ms or 335,602 50MHz clock periods. You would do the same for the reference clock and then you could compare both counts and ensure that the difference is less than 1,678 (33.55us), if its not then you know you have exceeded your PPM limit. All the counts could be set as parameters and could easily be adjusted based on the global clock frequency and the PPM offset required. +*/ + +// Synchronize reset to global Clock domain +always @ (posedge SYSTEM_CLK) begin + g_clk_rst_meta <= `DLY GT_RST; + g_clk_rst_sync <= `DLY g_clk_rst_meta; + + gt_pll_locked_meta <= `DLY PLL_LK_DET; + gt_pll_locked_sync <= `DLY gt_pll_locked_meta; + +end + +assign g_clk_rst = g_clk_rst_sync; +assign gt_pll_locked = gt_pll_locked_sync; + +generate +if (EXAMPLE_SIMULATION==0 ) +begin : HW_CIRCUITRY + +// Main FSM +always @ (posedge SYSTEM_CLK) +begin + if (g_clk_rst) begin + state <= `DLY WAIT_FOR_LOCK; + ppm0 <= `DLY {GCLK_COUNTER_UPPER_VALUE-1 {1'b1}}; + recclk_stable0 <= `DLY 1'b0; + EXEC_RESTART <= `DLY 1'b0; + end + else begin + EXEC_RESTART <= `DLY 1'b0; + case (state) + WAIT_FOR_LOCK: begin + if (gt_pll_locked) begin + if (ref_clk_edge_event == 2'b01) state <= `DLY REFCLK_EVENT; + else state <= `DLY WAIT_FOR_LOCK; + end + else begin + state <= `DLY WAIT_FOR_LOCK; + end + end + REFCLK_EVENT: begin + if (ref_clk_edge_event == 2'b11) begin // two reference couter periods + state <= `DLY CALC_PPM_DIFF; + end + else begin + state <= `DLY REFCLK_EVENT; + end + end + CALC_PPM_DIFF: begin + if (rec_clk0_edge_event) begin + ppm0 <= `DLY rec_clk0_compare_cnt_latch + ref_clk_compare_cnt_latch; + end + state <= `DLY CHECK_SIGN; + + end + CHECK_SIGN: begin + //check the sign bit - if 1'b1, then convert to binary. + if (ppm0[GCLK_COUNTER_UPPER_VALUE-1]) ppm0 <= `DLY ~ppm0 +1; + state <= `DLY COMP_CNTR; + + end + COMP_CNTR: begin + if (ppm0 < CLOCK_PULSES) + recclk_stable0 <= `DLY 1'b1; + else + recclk_stable0 <= `DLY 1'b0; + + state <= `DLY RESTART; + end + RESTART: begin + state <= `DLY WAIT_FOR_LOCK; + EXEC_RESTART <= `DLY 1'b1; + end + default: begin + state <= `DLY WAIT_FOR_LOCK; + ppm0 <= `DLY {GCLK_COUNTER_UPPER_VALUE-1 {1'b1}}; + recclk_stable0 <= `DLY 1'b0; + end + endcase + end + +end + + +// On clock roll-over, latch counter value once and event occurance. +always @ (posedge SYSTEM_CLK) +begin + if (reset_logic[3]) begin + rec_clk0_edge_event <= `DLY 1'b0; + ref_clk_edge_event <= `DLY 2'b00; + rec_clk0_compare_cnt_latch <= `DLY 'h0; + ref_clk_compare_cnt_latch <= `DLY 'h0; + ref_clk_edge_rt <= `DLY 2'b00; + end + else begin + if (rec_clk0_edge & (~rec_clk0_edge_event) ) begin + rec_clk0_edge_event <= `DLY 1'b1; + rec_clk0_compare_cnt_latch <= `DLY sys_clk_counter; + end + if (ref_clk_edge) begin + ref_clk_edge_event <= `DLY {ref_clk_edge_event,1'b1}; + //only latch it the first time around + if (~ref_clk_edge_event[0]) + ref_clk_compare_cnt_latch <= `DLY sys_clk_counter; + end + ref_clk_edge_rt <= `DLY {ref_clk_edge_rt[0],ref_clk_edge}; + //take the 2's complement number after we latched it + if ((ref_clk_edge_event == 2'b01) && (ref_clk_edge_rt==2'b01)) + ref_clk_compare_cnt_latch <= `DLY (~ref_clk_compare_cnt_latch) +1; + end +end + +// increment clock counters' +always @ (posedge SYSTEM_CLK) +begin + if (reset_logic[3]) begin + sys_clk_counter <= `DLY {GCLK_COUNTER_UPPER_VALUE{1'b0}}; + end + else begin + sys_clk_counter <= `DLY sys_clk_counter + 1; + end +end + +always @ (posedge SYSTEM_CLK) +begin + if (reset_logic[3]) begin + + rec_clk_0_msb_meta <= `DLY 1'b0; + ref_clk_msb_meta <= `DLY 1'b0; + rec_clk0_msb <= `DLY 2'b00; + ref_clk_msb <= `DLY 2'b00; + end + else begin // double flop msb count bit to system clock domain + rec_clk_0_msb_meta <= `DLY rec_clk0_cnt[COUNTER_UPPER_VALUE-1]; + rec_clk0_msb <= `DLY {rec_clk0_msb[1],rec_clk_0_msb_meta}; + + ref_clk_msb_meta <= `DLY ref_clk_cnt[COUNTER_UPPER_VALUE-1]; + ref_clk_msb <= `DLY {ref_clk_msb[1],ref_clk_msb_meta}; + end +end +//falling edge detect +assign rec_clk0_edge = (rec_clk0_msb[2] && ~rec_clk0_msb[1]); +assign ref_clk_edge = (ref_clk_msb[2] && ~ref_clk_msb[1]); + +// Manage counter reset/restart +always @ (posedge SYSTEM_CLK) +begin + if (g_clk_rst) begin + reset_logic <= `DLY 'hf; + end + else begin + if (state == RESTART) reset_logic <= `DLY 4'b1111; + else reset_logic <= `DLY reset_logic << 1; + + end + +end + + assign RECCLK_STABLE = recclk_stable0; + +end +endgenerate + +generate + if (EXAMPLE_SIMULATION == 1) + begin:sim + + //This Generate-branch is ONLY FOR SIMULATION and is not implemented in HW. + //The whole purpose of this shortcut-branch is to avoid huge simulation- + //times. + always @(posedge SYSTEM_CLK) + begin + if( GT_RST) + recclk_stable0_int <= `DLY 1'b0; + else + recclk_stable0_int <= `DLY PLL_LK_DET; + end + + assign RECCLK_STABLE = recclk_stable0_int; + + end +endgenerate + + +endmodule + diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v new file mode 100644 index 000000000..5f44c9fb2 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v @@ -0,0 +1,727 @@ +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 2.4 +// \ \ Application : 7 Series FPGAs Transceivers Wizard +// / / Filename : gige_sfp_mdio_rx_startup_fsm.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +// +// Description : This module performs RX reset and initialization. +// +// +// +// Module gige_sfp_mdio_rx_startup_fsm +// Generated by Xilinx 7 Series FPGAs Transceivers Wizard +// +// +// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +//***************************************************************************** + +`timescale 1ns / 1ps +`define DLY #1 + + +module gige_sfp_mdio_RX_STARTUP_FSM # + ( + parameter EXAMPLE_SIMULATION = 0, // Set to 1 for Simulation + parameter GT_TYPE = "GTX", + parameter EQ_MODE = "DFE", //Rx Equalization Mode - Set to DFE or LPM + parameter STABLE_CLOCK_PERIOD = 8, //Period of the stable clock driving this state-machine, unit is [ns] + parameter RETRY_COUNTER_BITWIDTH = 8, + parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must + parameter RX_QPLL_USED = "FALSE", // share these two generic values + + parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic + // is enough. For single-lane applications the automatic alignment is + // sufficient + ) + ( + input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB + //or reference-clock present at startup. + input wire RXUSERCLK, //RXUSERCLK as used in the design + input wire SOFT_RESET, //User Reset, can be pulled any time + input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost + input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost + input wire QPLLLOCK, //Lock Detect from the QPLL of the GT + input wire CPLLLOCK, //Lock Detect from the CPLL of the GT + input wire RXRESETDONE, + input wire MMCM_LOCK, + input wire RECCLK_STABLE, + input wire RECCLK_MONITOR_RESTART, + input wire DATA_VALID, + input wire TXUSERRDY, //TXUSERRDY from GT + output reg GTRXRESET = 1'b0, + output reg MMCM_RESET = 1'b1, + output reg QPLL_RESET = 1'b0, //Reset QPLL (only if RX usese QPLL) + output reg CPLL_RESET = 1'b0, //Reset CPLL (only if RX usese CPLL) + output RX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished. + output reg RXUSERRDY = 1'b0, + output wire RUN_PHALIGNMENT, + input wire PHALIGNMENT_DONE, + output reg RESET_PHALIGNMENT = 1'b0, + output reg RXDFEAGCHOLD = 1'b0, + output reg RXDFELFHOLD = 1'b0, + output reg RXLPMLFHOLD = 1'b0, + output reg RXLPMHFHOLD = 1'b0, + output wire [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of + // Retries it took to get the transceiver up and running + ); + + +//Interdependencies: +// * Timing depends on the frequency of the stable clock. Hence counters-sizes +// are calculated at design-time based on the Generics +// +// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX +// => signal which PLL has been reset +// * + + + + localparam [3:0] + INIT = 4'b0000, + ASSERT_ALL_RESETS = 4'b0001, + RELEASE_PLL_RESET = 4'b0010, + VERIFY_RECCLK_STABLE = 4'b0011, + RELEASE_MMCM_RESET = 4'b0100, + WAIT_RESET_DONE = 4'b0101, + DO_PHASE_ALIGNMENT = 4'b0110, + MONITOR_DATA_VALID = 4'b0111, + FSM_DONE = 4'b1000; + + reg [3:0] rx_state = INIT; + + //This function decides how many clock-cycle need to be waited until + // a time-out occurs for bypassing the TX-Buffer + function [12:0] get_max_wait_bypass; + input manual_mode; + reg [12:0] max_wait_cnt; + begin + if (manual_mode == "TRUE") + max_wait_cnt = 5000; + else + max_wait_cnt = 3100; + get_max_wait_bypass = max_wait_cnt; + end + endfunction + + localparam MMCM_LOCK_CNT_MAX = 1024; + localparam STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration + localparam WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration + localparam WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin + + localparam WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD; //2 ms time-out + localparam WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD; //100 us time-out + localparam WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD; //500 us time-out + localparam WAIT_TIMEOUT_1us = 1000 / STABLE_CLOCK_PERIOD; //1 us time-out + localparam WAIT_TIMEOUT_100us = 100000 / STABLE_CLOCK_PERIOD; //100us time-out + integer WAIT_TIME_ADAPT = (37000000 /1.25)/STABLE_CLOCK_PERIOD; + + reg [7:0] init_wait_count = 0; + reg init_wait_done = 1'b0; + reg pll_reset_asserted = 1'b0; + + reg rx_fsm_reset_done_int = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg rx_fsm_reset_done_int_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg rx_fsm_reset_done_int_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg rx_fsm_reset_done_int_s3 = 1'b0; + + localparam MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1; + reg [7:0] retry_counter_int = 0; + reg [18:0] time_out_counter = 0; + reg [1:0] recclk_mon_restart_count = 0 ; + reg recclk_mon_count_reset = 0; + + reg reset_time_out = 1'b0; + reg time_out_2ms = 1'b0; //--\Flags that the various time-out points + reg time_tlock_max = 1'b0; //--|have been reached. + reg time_out_500us = 1'b0; //--| + reg time_out_1us = 1'b0; //--| + reg time_out_100us = 1'b0; //--/ + reg check_tlock_max = 1'b0; + + reg [9:0] mmcm_lock_count = 1'b0; + reg mmcm_lock_int = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg [3:0] mmcm_lock_reclocked = 1'b0; + + reg run_phase_alignment_int = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg run_phase_alignment_int_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg run_phase_alignment_int_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg run_phase_alignment_int_s3 = 1'b0; + + + localparam MAX_WAIT_BYPASS = 5000;//5000 RXUSRCLK cycles is the max time for Multi Lane designs + + reg [12:0] wait_bypass_count = 0; + reg time_out_wait_bypass = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg time_out_wait_bypass_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg time_out_wait_bypass_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg time_out_wait_bypass_s3 = 1'b0; + + wire refclk_lost; + + (* ASYNC_REG = "TRUE" *) + reg rxresetdone_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg rxresetdone_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg rxresetdone_s3 = 1'b0; + + + integer adapt_count = 0; + reg time_out_adapt = 1'b0; + reg adapt_count_reset = 1'b0; + + //Alias section, signals used within this module mapped to output ports: + assign RETRY_COUNTER = retry_counter_int; + assign RUN_PHALIGNMENT = run_phase_alignment_int; + assign RX_FSM_RESET_DONE = rx_fsm_reset_done_int; + + always @(posedge STABLE_CLOCK) + begin + // The counter starts running when configuration has finished and + // the clock is stable. When its maximum count-value has been reached, + // the 500 ns from Answer Record 43482 have been passed. + if (init_wait_count == WAIT_MAX) + init_wait_done <= `DLY 1'b1; + else + init_wait_count <= `DLY init_wait_count + 1; + end + + + + always @(posedge STABLE_CLOCK) + begin + //This counter monitors, how many retries the CDR Lock Detection + //runs. If during startup too many retries are necessary, the whole + //initialisation-process of the transceivers gets restarted. + if (recclk_mon_count_reset == 1) + recclk_mon_restart_count <= `DLY 0; + else if (RECCLK_MONITOR_RESTART == 1) + begin + if (recclk_mon_restart_count == 3) + recclk_mon_restart_count <= `DLY 0; + else + recclk_mon_restart_count <= `DLY recclk_mon_restart_count + 1; + end + end + +generate + if(EXAMPLE_SIMULATION == 1) + begin + always @(posedge STABLE_CLOCK) + begin + time_out_adapt <= `DLY 1'b1; + end + end + + else + begin + always @(posedge STABLE_CLOCK) + begin + if (adapt_count_reset == 1'b1) + begin + adapt_count <= `DLY 0; + time_out_adapt <= `DLY 1'b0; + end + else + begin + if (adapt_count >= WAIT_TIME_ADAPT) + time_out_adapt <= `DLY 1'b1; + else + adapt_count <= `DLY adapt_count + 1; + end + end + + end +endgenerate + + always @(posedge STABLE_CLOCK) + begin + // One common large counter for generating three time-out signals. + // Intermediate time-outs are derived from calculated values, based + // on the period of the provided clock. + if (reset_time_out == 1) + begin + time_out_counter <= `DLY 0; + time_out_2ms <= `DLY 1'b0; + time_tlock_max <= `DLY 1'b0; + time_out_500us <= `DLY 1'b0; + time_out_1us <= `DLY 1'b0; + time_out_100us <= `DLY 1'b0; + end + else + begin + if (time_out_counter == WAIT_TIMEOUT_2ms) + time_out_2ms <= `DLY 1'b1; + else + time_out_counter <= `DLY time_out_counter + 1; + + if (time_out_counter > WAIT_TLOCK_MAX && check_tlock_max == 1) + begin + time_tlock_max <= `DLY 1'b1; + end + + if (time_out_counter == WAIT_TIMEOUT_500us) + begin + time_out_500us <= `DLY 1'b1; + end + + if (time_out_counter == WAIT_TIMEOUT_1us) + begin + time_out_1us <= `DLY 1'b1; + end + + if (time_out_counter == WAIT_TIMEOUT_100us) + begin + time_out_100us <= `DLY 1'b1; + end + + end + end + + always @(posedge RXUSERCLK) + begin + //The lock-signal from the MMCM is not immediately used but + //enabling a counter. Only when the counter hits its maximum, + //the MMCM is considered as "really" locked. + //The counter avoids that the FSM already starts on only a + //coarse lock of the MMCM (=toggling of the LOCK-signal). + if (MMCM_LOCK == 1'b0) + begin + mmcm_lock_count <= `DLY 0; + mmcm_lock_int <= `DLY 1'b0; + end + else + begin + if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1) + mmcm_lock_count <= `DLY mmcm_lock_count + 1; + else + mmcm_lock_int <= `DLY 1'b1; + end + end + + always @(posedge STABLE_CLOCK) + //Reclocking onto the FSM-clock. + begin + if (MMCM_LOCK == 1'b0) + //The reset-signal is here on purpose. This avoids + //getting the shift-register targetted to an SRL. + //The reason for this is that an SRL will not help + //on the cross-clock domain but "real" Flip-flops will. + + mmcm_lock_reclocked <= `DLY 4'b0000; + else + begin + mmcm_lock_reclocked[3] <= `DLY mmcm_lock_int; + mmcm_lock_reclocked[2:0] <= `DLY mmcm_lock_reclocked[3:1]; + end + end + + //Clock Domain Crossing + + always @(posedge RXUSERCLK) + begin + run_phase_alignment_int_s1 <= `DLY run_phase_alignment_int; + run_phase_alignment_int_s2 <= `DLY run_phase_alignment_int_s1; + run_phase_alignment_int_s3 <= `DLY run_phase_alignment_int_s2; + + rx_fsm_reset_done_int_s1 <= `DLY rx_fsm_reset_done_int; + rx_fsm_reset_done_int_s2 <= `DLY rx_fsm_reset_done_int_s1; + rx_fsm_reset_done_int_s3 <= `DLY rx_fsm_reset_done_int_s2; + end + + + always @(posedge STABLE_CLOCK) + begin + time_out_wait_bypass_s1 <= `DLY time_out_wait_bypass; + time_out_wait_bypass_s2 <= `DLY time_out_wait_bypass_s1; + time_out_wait_bypass_s3 <= `DLY time_out_wait_bypass_s2; + + rxresetdone_s1 <= `DLY RXRESETDONE; + rxresetdone_s2 <= `DLY rxresetdone_s1; + rxresetdone_s3 <= `DLY rxresetdone_s2; + end + + + + + always @(posedge RXUSERCLK) + begin + if (run_phase_alignment_int_s3 == 1'b0) + begin + wait_bypass_count <= `DLY 0; + time_out_wait_bypass <= `DLY 1'b0; + end + else if ((run_phase_alignment_int_s3 == 1'b1) && (rx_fsm_reset_done_int_s3 == 1'b0)) + begin + if (wait_bypass_count == MAX_WAIT_BYPASS - 1) + time_out_wait_bypass <= `DLY 1'b1; + else + wait_bypass_count <= `DLY wait_bypass_count + 1; + end + end + + assign refclk_lost = ( RX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b1) ? 1'b1 : + ( RX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b1) ? 1'b1 : 1'b0; + + + //FSM for resetting the GTX/GTH/GTP in the 7-series. + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // + // Following steps are performed: + // 1) After configuration wait for approximately 500 ns as specified in + // answer-record 43482 + // 2) Assert all resets on the GT and on an MMCM potentially connected. + // After that wait until a reference-clock has been detected. + // 3) Release the reset to the GT and wait until the GT-PLL has locked. + // 4) Release the MMCM-reset and wait until the MMCM has signalled lock. + // Also get info from the TX-side which PLL has been reset. + // 5) Wait for the RESET_DONE-signal from the GT. + // 6) Signal to start the phase-alignment procedure and wait for it to + // finish. + // 7) Reset-sequence has successfully run through. Signal this to the + // rest of the design by asserting RX_FSM_RESET_DONE. + + always @(posedge STABLE_CLOCK) + begin + if (SOFT_RESET == 1'b1 || (rx_state != INIT && rx_state != ASSERT_ALL_RESETS && refclk_lost == 1'b1)) + begin + rx_state <= `DLY INIT; + RXUSERRDY <= `DLY 1'b0; + GTRXRESET <= `DLY 1'b0; + MMCM_RESET <= `DLY 1'b1; + rx_fsm_reset_done_int <= `DLY 1'b0; + QPLL_RESET <= `DLY 1'b0; + CPLL_RESET <= `DLY 1'b0; + pll_reset_asserted <= `DLY 1'b0; + reset_time_out <= `DLY 1'b1; + retry_counter_int <= `DLY 0; + run_phase_alignment_int <= `DLY 1'b0; + check_tlock_max <= `DLY 1'b0; + RESET_PHALIGNMENT <= `DLY 1'b1; + recclk_mon_count_reset <= `DLY 1'b1; + adapt_count_reset <= `DLY 1'b1; + RXDFEAGCHOLD <= `DLY 1'b0; + RXDFELFHOLD <= `DLY 1'b0; + RXLPMLFHOLD <= `DLY 1'b0; + RXLPMHFHOLD <= `DLY 1'b0; + end + else + begin + + case (rx_state) + INIT : + begin + //Initial state after configuration. This state will be left after + //approx. 500 ns and not be re-entered. + if (init_wait_done == 1'b1) + rx_state <= `DLY ASSERT_ALL_RESETS; + end + + ASSERT_ALL_RESETS : + begin + //This is the state into which the FSM will always jump back if any + //time-outs will occur. + //The number of retries is reported on the output RETRY_COUNTER. In + //case the transceiver never comes up for some reason, this machine + //will still continue its best and rerun until the FPGA is turned off + //or the transceivers come up correctly. + if (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE") + begin + if (pll_reset_asserted == 1'b0) + begin + QPLL_RESET <= `DLY 1'b1; + pll_reset_asserted <= `DLY 1'b1; + end + else + QPLL_RESET <= `DLY 1'b0; + end + else if (RX_QPLL_USED == "FALSE" && TX_QPLL_USED) + begin + if (pll_reset_asserted == 1'b0) + begin + CPLL_RESET <= `DLY 1'b1; + pll_reset_asserted <= `DLY 1'b1; + end + else + CPLL_RESET <= `DLY 1'b0; + end + RXUSERRDY <= `DLY 1'b0; + GTRXRESET <= `DLY 1'b1; + MMCM_RESET <= `DLY 1'b1; + run_phase_alignment_int <= `DLY 1'b0; + RESET_PHALIGNMENT <= `DLY 1'b1; + check_tlock_max <= `DLY 1'b0; + recclk_mon_count_reset <= `DLY 1'b1; + adapt_count_reset <= `DLY 1'b1; + + if ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE" && QPLLREFCLKLOST == 1'b0 && pll_reset_asserted) || + (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "TRUE" && CPLLREFCLKLOST == 1'b0 && pll_reset_asserted) || + (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b0 ) || + (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b0 ) + ) + begin + rx_state <= `DLY RELEASE_PLL_RESET; + reset_time_out <= `DLY 1'b1; + end + end + + RELEASE_PLL_RESET : + begin + //PLL-Reset of the GTX gets released and the time-out counter + //starts running. + pll_reset_asserted <= `DLY 1'b0; + reset_time_out <= `DLY 1'b0; + + if ((RX_QPLL_USED == "TRUE" && QPLLLOCK == 1'b1) || + (RX_QPLL_USED == "FALSE" && CPLLLOCK == 1'b1)) + begin + rx_state <= `DLY VERIFY_RECCLK_STABLE; + reset_time_out <= `DLY 1'b1; + recclk_mon_count_reset <= `DLY 1'b0; + adapt_count_reset <= `DLY 1'b0; + end + + if (time_out_2ms == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + begin + retry_counter_int <= `DLY retry_counter_int + 1; + end + rx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + VERIFY_RECCLK_STABLE : + begin + //reset_time_out <= `DLY '0'; + //Time-out counter is not released in this state as here the FSM + //does not wait for a certain period of time but checks on the number + //of retries in the CDR PPM detector. + GTRXRESET <= `DLY 1'b0; + if (RECCLK_STABLE == 1'b1) + begin + rx_state <= `DLY RELEASE_MMCM_RESET; + reset_time_out <= `DLY 1'b1; + end + + if (recclk_mon_restart_count == 2) + begin + //If two retries are performed in the CDR "Lock" (=CDR PPM-detector) + //the whole initialisation-sequence gets restarted. + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + begin + retry_counter_int <= `DLY retry_counter_int + 1; + end + rx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + RELEASE_MMCM_RESET : + begin + //Release of the MMCM-reset. Waiting for the MMCM to lock. + reset_time_out <= `DLY 1'b0; + check_tlock_max <= `DLY 1'b1; + + MMCM_RESET <= `DLY 1'b0; + if (mmcm_lock_reclocked[0] == 1'b1) + begin + rx_state <= `DLY WAIT_RESET_DONE; + reset_time_out <= `DLY 1'b1; + end + + if (time_tlock_max == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + begin + retry_counter_int <= `DLY retry_counter_int + 1; + end + rx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + WAIT_RESET_DONE : + begin + //When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY + //If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1' + + if(TXUSERRDY) + RXUSERRDY <= `DLY 1'b1; + + reset_time_out <= `DLY 1'b0; + if (rxresetdone_s3 == 1'b1) + begin + rx_state <= `DLY DO_PHASE_ALIGNMENT; + reset_time_out <= `DLY 1'b1; + end + + if (time_out_500us == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + begin + retry_counter_int <= `DLY retry_counter_int + 1; + end + rx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + DO_PHASE_ALIGNMENT : + begin + //The direct handling of the signals for the Phase Alignment is done outside + //this state-machine. + RESET_PHALIGNMENT <= `DLY 1'b0; + run_phase_alignment_int <= `DLY 1'b1; + reset_time_out <= `DLY 1'b0; + + if (PHALIGNMENT_DONE == 1'b1) + begin + rx_state <= `DLY MONITOR_DATA_VALID; + reset_time_out <= `DLY 1'b1; + end + + if (time_out_wait_bypass_s3 == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + begin + retry_counter_int <= `DLY retry_counter_int + 1; + end + rx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + MONITOR_DATA_VALID : + begin + reset_time_out <= `DLY 1'b0; + + if (DATA_VALID == 1'b0 && time_out_100us == 1'b1) + begin + rx_state <= `DLY ASSERT_ALL_RESETS; + rx_fsm_reset_done_int <= `DLY 1'b0; + end + else if (DATA_VALID == 1'b1) + begin + rx_state <= `DLY FSM_DONE; + rx_fsm_reset_done_int <= `DLY 1'b0; + reset_time_out <= `DLY 1'b1; + end + + end + + FSM_DONE : + begin + reset_time_out <= `DLY 1'b0; + + if (DATA_VALID == 1'b0) + begin + rx_fsm_reset_done_int <= `DLY 1'b0; + reset_time_out <= `DLY 1'b1; + rx_state <= `DLY MONITOR_DATA_VALID; + end + else if(time_out_1us == 1'b1) + rx_fsm_reset_done_int <= `DLY 1'b1; + + if(time_out_adapt) + begin + if((GT_TYPE == "GTX" || GT_TYPE == "GTH") && EQ_MODE == "DFE") + begin + RXDFEAGCHOLD <= `DLY 1'b1; + RXDFELFHOLD <= `DLY 1'b1; + end + else if(GT_TYPE == "GTH" && EQ_MODE == "LPM") + begin + RXLPMHFHOLD <= `DLY 1'b1; + RXLPMLFHOLD <= `DLY 1'b1; + end + end + + + end + + endcase + end + end + +endmodule + + diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_transceiver.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_transceiver.v new file mode 100644 index 000000000..493944b29 --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_transceiver.v @@ -0,0 +1,527 @@ +//------------------------------------------------------------------------------ +// Title : Top-level Transceiver GT wrapper for Ethernet +// Project : Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE +// File : gige_sfp_mdio_transceiver.v +// Author : Xilinx +//------------------------------------------------------------------------------ +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This is the top-level Transceiver GT wrapper. It +// instantiates the lower-level wrappers produced by +// the Series-7 FPGA Transceiver GT Wrapper Wizard. +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module gige_sfp_mdio_transceiver ( + input encommaalign, + input loopback, + input powerdown, + input usrclk, + input usrclk2, + input data_valid, + input independent_clock, + input txreset, + input [7:0] txdata, + input txchardispmode, + input txchardispval, + input txcharisk, + input rxreset, + output reg rxchariscomma, + output reg rxcharisk, + output reg [2:0] rxclkcorcnt, + output reg [7:0] rxdata, + output reg rxdisperr, + output reg rxnotintable, + output reg rxrundisp, + output reg rxbuferr, + output reg txbuferr, + output plllkdet, + output txoutclk, + output txn, + output txp, + input rxn, + input rxp, + input gtrefclk, + input pmareset, + input mmcm_locked, + output resetdone + +); + + + //---------------------------------------------------------------------------- + // Signal declarations + //---------------------------------------------------------------------------- + + wire cplllock; + wire gt_reset_rx; + wire gt_reset_tx; + wire resetdone_tx; + wire resetdone_rx; + wire pcsreset; + (* KEEP = "TRUE" *) reg data_valid_reg; + wire data_valid_reg2; + + wire [2:0] rxbufstatus; + wire [1:0] txbufstatus; + reg [2:0] rxbufstatus_reg; + reg [1:0] txbufstatus_reg; + wire [1:0] rxclkcorcnt_int; + reg txpowerdown_reg = 1'b0; + reg txpowerdown_double = 1'b0; + reg txpowerdown = 1'b0; + wire [1:0] txpowerdown_int; + + // signal used to control sampling during bus width conversions + reg toggle; + + // signals reclocked onto the 62.5MHz userclk source of the GT transceiver + wire encommaalign_int; + wire txreset_int; + wire rxreset_int; + + // Register transmitter signals from the core + reg [7:0] txdata_reg; + reg txchardispmode_reg; + reg txchardispval_reg; + reg txcharisk_reg; + + // Signals for data bus width doubling on the transmitter path from the core + // to the GT transceiver + reg [15:0] txdata_double; + reg [1:0] txchardispmode_double; + reg [1:0] txchardispval_double; + reg [1:0] txcharisk_double; + + // Double width signals reclocked onto the 62.5MHz userclk source of the GT + // transceiver + reg [15:0] txdata_int; + reg [1:0] txchardispmode_int; + reg [1:0] txchardispval_int; + reg [1:0] txcharisk_int; + + // Double width signals output from the GT transceiver on the 62.5MHz clock + // source + wire [1:0] rxchariscomma_int; + wire [1:0] rxcharisk_int; + wire [15:0] rxdata_int; + wire [1:0] rxdisperr_int; + wire [1:0] rxnotintable_int; + wire [1:0] rxrundisp_int; + + // Double width signals reclocked on the GT's 62.5MHz clock source + reg [1:0] rxchariscomma_reg; + reg [1:0] rxcharisk_reg; + reg [15:0] rxdata_reg; + reg [1:0] rxdisperr_reg; + reg [1:0] rxnotintable_reg; + reg [1:0] rxrundisp_reg; + reg rxpowerdown_reg = 1'b0; + + // Double width signals reclocked onto the 125MHz clock source + reg [1:0] rxchariscomma_double; + reg [1:0] rxcharisk_double; + reg [15:0] rxdata_double; + reg [1:0] rxdisperr_double; + reg [1:0] rxnotintable_double; + reg [1:0] rxrundisp_double; + reg rxpowerdown_double = 1'b0; + + reg rxpowerdown = 1'b0; + wire [1:0] rxpowerdown_int; + + + assign txpowerdown_int = {2{txpowerdown}}; + assign rxpowerdown_int = {2{rxpowerdown}}; + + //--------------------------------------------------------------------------- + // The core works from a 125MHz clock source, the GT transceiver fabric + // interface works from a 62.5MHz clock source. The following signals + // sourced by the core therefore need to be reclocked onto the 62.5MHz + // clock + //--------------------------------------------------------------------------- + + // Reclock encommaalign + gige_sfp_mdio_reset_sync reclock_encommaalign + ( + .clk (usrclk), + .reset_in (encommaalign), + .reset_out (encommaalign_int) + ); + + + // Reclock txreset + gige_sfp_mdio_reset_sync reclock_txreset + ( + .clk (usrclk), + .reset_in (txreset), + .reset_out (txreset_int) + ); + + + // Reclock rxreset + gige_sfp_mdio_reset_sync reclock_rxreset + ( + .clk (usrclk), + .reset_in (rxreset), + .reset_out (rxreset_int) + ); + + + //--------------------------------------------------------------------------- + // toggle signal used to control sampling during bus width conversions + //--------------------------------------------------------------------------- + + always @(posedge usrclk2) + begin + if (txreset) begin + toggle <= 1'b0; + end + else begin + toggle <= !toggle; + end + end + + + //--------------------------------------------------------------------------- + // The core works from a 125MHz clock source, the GT transceiver fabric + // interface works from a 62.5MHz clock source. The following signals + // sourced by the core therefore need to be converted to double width, then + // resampled on the GT's 62.5MHz clock + //--------------------------------------------------------------------------- + + // Reclock the transmitter signals + always @(posedge usrclk2) + begin + if (txreset) begin + txdata_reg <= 8'b0; + txchardispmode_reg <= 1'b0; + txchardispval_reg <= 1'b0; + txcharisk_reg <= 1'b0; + txpowerdown_reg <= 1'b0; + end + else begin + txdata_reg <= txdata; + txchardispmode_reg <= txchardispmode; + txchardispval_reg <= txchardispval; + txcharisk_reg <= txcharisk; + txpowerdown_reg <= powerdown; + end + end + + + // Double the data width + always @(posedge usrclk2) + begin + if (txreset) begin + txdata_double <= 16'b0; + txchardispmode_double <= 2'b0; + txchardispval_double <= 2'b0; + txcharisk_double <= 2'b0; + txpowerdown_double <= 1'b0; + end + else begin + if (!toggle) begin + txdata_double[7:0] <= txdata_reg; + txchardispmode_double[0] <= txchardispmode_reg; + txchardispval_double[0] <= txchardispval_reg; + txcharisk_double[0] <= txcharisk_reg; + txdata_double[15:8] <= txdata; + txchardispmode_double[1] <= txchardispmode; + txchardispval_double[1] <= txchardispval; + txcharisk_double[1] <= txcharisk; + end + txpowerdown_double <= txpowerdown_reg; + end + end + + + // Cross the clock domain + always @(posedge usrclk) + begin + txdata_int <= txdata_double; + txchardispmode_int <= txchardispmode_double; + txchardispval_int <= txchardispval_double; + txcharisk_int <= txcharisk_double; + txbufstatus_reg <= txbufstatus; + txpowerdown <= txpowerdown_double; + end + + + + //--------------------------------------------------------------------------- + // The core works from a 125MHz clock source, the GT transceiver fabric + // interface works from a 62.5MHz clock source. The following signals + // sourced by the GT transceiver therefore need to converted to half width + //--------------------------------------------------------------------------- + + // Sample the double width received data from the GT transsciever on the GT's + // 62.5MHz clock + always @(posedge usrclk) + begin + rxchariscomma_reg <= rxchariscomma_int; + rxcharisk_reg <= rxcharisk_int; + rxdata_reg <= rxdata_int; + rxdisperr_reg <= rxdisperr_int; + rxnotintable_reg <= rxnotintable_int; + rxrundisp_reg <= rxrundisp_int; + rxbufstatus_reg <= rxbufstatus; + rxpowerdown <= rxpowerdown_reg; + end + + + // Reclock the double width received data from the GT transsciever onto the + // 125MHz clock source. Both clock domains are frequency related and are + // derived from the same MMCM: the Xilinx tools will accont for this. + + always @(posedge usrclk2) + begin + if (rxreset) begin + rxchariscomma_double <= 2'b0; + rxcharisk_double <= 2'b0; + rxdata_double <= 16'b0; + rxdisperr_double <= 2'b0; + rxnotintable_double <= 2'b0; + rxrundisp_double <= 2'b0; + rxpowerdown_double <= 1'b0; + end + else if (toggle) begin + rxchariscomma_double <= rxchariscomma_reg; + rxcharisk_double <= rxcharisk_reg; + rxdata_double <= rxdata_reg; + rxdisperr_double <= rxdisperr_reg; + rxnotintable_double <= rxnotintable_reg; + rxrundisp_double <= rxrundisp_reg; + end + rxpowerdown_double <= powerdown; + end + + + // Halve the bus width + always @(posedge usrclk2) + begin + if (rxreset) begin + rxchariscomma <= 1'b0; + rxcharisk <= 1'b0; + rxdata <= 8'b0; + rxdisperr <= 1'b0; + rxnotintable <= 1'b0; + rxrundisp <= 1'b0; + rxpowerdown_reg <= 1'b0; + end + else begin + if (!toggle) begin + rxchariscomma <= rxchariscomma_double[0]; + rxcharisk <= rxcharisk_double[0]; + rxdata <= rxdata_double[7:0]; + rxdisperr <= rxdisperr_double[0]; + rxnotintable <= rxnotintable_double[0]; + rxrundisp <= rxrundisp_double[0]; + end + else begin + rxchariscomma <= rxchariscomma_double[1]; + rxcharisk <= rxcharisk_double[1]; + rxdata <= rxdata_double[15:8]; + rxdisperr <= rxdisperr_double[1]; + rxnotintable <= rxnotintable_double[1]; + rxrundisp <= rxrundisp_double[1]; + end + rxpowerdown_reg <= rxpowerdown_double; + end + end + + + //--------------------------------------------------------------------------- + // Instantiate the Series-7 GTX + //--------------------------------------------------------------------------- + // Direct from the Transceiver Wizard output + gige_sfp_mdio_GTWIZARD_init # + ( + .EXAMPLE_SIM_GTRESET_SPEEDUP ("TRUE") + ) + gtwizard_inst + ( + .SYSCLK_IN (independent_clock), + .SOFT_RESET_IN (pmareset), + .GT0_TX_FSM_RESET_DONE_OUT (), + .GT0_RX_FSM_RESET_DONE_OUT (), + .GT0_DATA_VALID_IN (data_valid_reg2), + //----------------------- Channel - Ref Clock Ports //------------------ + .GT0_GTREFCLK0_IN (gtrefclk), + //------------------------------ Channel PLL //------------------------- + .GT0_CPLLFBCLKLOST_OUT (), + .GT0_CPLLLOCK_OUT (cplllock), + .GT0_CPLLLOCKDETCLK_IN (independent_clock), + .GT0_CPLLRESET_IN (pmareset), + //----------------------------- Eye Scan Ports //----------------------- + .GT0_EYESCANDATAERROR_OUT (), + //---------------------- Loopback and Powerdown Ports //---------------- + .GT0_LOOPBACK_IN (3'b0), + .GT0_RXPD_IN (rxpowerdown_int), + .GT0_TXPD_IN (txpowerdown_int), + //----------------------------- Receive Ports -------------------------- + .GT0_RXUSERRDY_IN (mmcm_locked), + //--------------------- Receive Ports - 8b10b Decoder //---------------- + .GT0_RXCHARISCOMMA_OUT (rxchariscomma_int), + .GT0_RXCHARISK_OUT (rxcharisk_int), + .GT0_RXDISPERR_OUT (rxdisperr_int), + .GT0_RXNOTINTABLE_OUT (rxnotintable_int), + //----------------- Receive Ports - Clock Correction Ports //----------- + .GT0_RXCLKCORCNT_OUT (rxclkcorcnt_int), + //------------- Receive Ports - Comma Detection and Alignment //-------- + .GT0_RXMCOMMAALIGNEN_IN (encommaalign_int), + .GT0_RXPCOMMAALIGNEN_IN (encommaalign_int), + //----------------- Receive Ports - RX Data Path interface //----------- + .GT0_GTRXRESET_IN (gt_reset_rx), +// .GT0_GTRXRESET_IN (rxreset_int), + .GT0_RXDATA_OUT (rxdata_int), + .GT0_RXOUTCLK_OUT (), + .GT0_RXUSRCLK_IN (usrclk), + .GT0_RXUSRCLK2_IN (usrclk), + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + .GT0_RXDFELPMRESET_IN (1'b0), + .GT0_RXMONITOROUT_OUT (), + .GT0_RXMONITORSEL_IN (2'b0), + //----- Receive Ports - RX Driver),OOB signalling),Coupling and Eq.),CDR // + .GT0_GTXRXN_IN (rxn), + .GT0_GTXRXP_IN (rxp), + .GT0_RXCDRLOCK_OUT (), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports //- + .GT0_RXBUFRESET_IN (rxreset_int), + .GT0_RXBUFSTATUS_OUT (rxbufstatus), + //---------------------- Receive Ports - RX PLL Ports //---------------- + .GT0_RXRESETDONE_OUT (resetdone_rx), + //----------------------------- Transmit Ports ------------------------- + .GT0_TXUSERRDY_IN (mmcm_locked), + //-------------- Transmit Ports - 8b10b Encoder Control Ports //-------- + .GT0_TXCHARDISPMODE_IN (txchardispmode_int), + .GT0_TXCHARDISPVAL_IN (txchardispval_int), + .GT0_TXCHARISK_IN (txcharisk_int), + //---------------- Transmit Ports - TX Data Path interface //----------- + .GT0_GTTXRESET_IN (gt_reset_tx), +// .GT0_GTTXRESET_IN (txreset_int), + .GT0_TXDATA_IN (txdata_int), + .GT0_TXOUTCLK_OUT (txoutclk), + .GT0_TXOUTCLKFABRIC_OUT (), + .GT0_TXOUTCLKPCS_OUT (), + //.GT0_TXPCSRESET_IN (pcsreset), + .GT0_TXUSRCLK_IN (usrclk), + .GT0_TXUSRCLK2_IN (usrclk), + //-------------- Transmit Ports - TX Driver and OOB signaling //-------- + .GT0_GTXTXN_OUT (txn), + .GT0_GTXTXP_OUT (txp), + //--------- Transmit Ports - TX Elastic Buffer and Phase Alignment //--- + .GT0_TXBUFSTATUS_OUT (txbufstatus), + //--------------------- Transmit Ports - TX PLL Ports //---------------- + .GT0_TXRESETDONE_OUT (resetdone_tx), + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + .GT0_TXELECIDLE_IN (txpowerdown), + //____________________________COMMON PORTS________________________________ + //-------------------- Common Block - Ref Clock Ports --------------------- + .GT0_GTREFCLK0_COMMON_IN (gtrefclk), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT () , + .GT0_QPLLLOCKDETCLK_IN (independent_clock), + .GT0_QPLLRESET_IN (1'b0) + + ); + + + // Hold the transmitter and receiver paths of the GT transceiver in reset + // until the PLL has locked. + assign gt_reset_rx = (rxreset_int & resetdone_rx); + assign gt_reset_tx = (txreset_int & resetdone_tx); + + + // Output the PLL locked status + assign plllkdet = cplllock; + + + // Report overall status for both transmitter and receiver reset done signals + assign resetdone = cplllock ; + + + // reset to PCS part of GT + assign pcsreset = !mmcm_locked; + + // temporary + assign rxrundisp_int = 2'b0; + + + // Decode the GT transceiver buffer status signals + always @(posedge usrclk2) + begin + rxbuferr <= rxbufstatus_reg[2]; + txbuferr <= txbufstatus_reg[1]; + rxclkcorcnt <= {1'b0, rxclkcorcnt_int}; + end + + //--------------------------------------------------------------------------- + // The core works from a 125MHz clock source userclk2, the init statemachines + // work at 200 MHz. + //--------------------------------------------------------------------------- + + // Cross the clock domain + always @(posedge usrclk2) + begin + data_valid_reg <= data_valid; + end + + + gige_sfp_mdio_sync_block sync_block_data_valid + ( + .clk (independent_clock), + .data_in (data_valid_reg), + .data_out (data_valid_reg2) + ); + + + +endmodule diff --git a/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v new file mode 100644 index 000000000..53145a26f --- /dev/null +++ b/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v @@ -0,0 +1,509 @@ +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 2.4 +// \ \ Application : 7 Series FPGAs Transceivers Wizard +// / / Filename : gige_sfp_mdio_tx_startup_fsm.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +// +// Description : This module performs TX reset and initialization. +// +// +// +// Module gige_sfp_mdio_TX_STARTUP_FSM +// Generated by Xilinx 7 Series FPGAs Transceivers Wizard +// +// +// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +//***************************************************************************** + +`timescale 1ns / 1ps +`define DLY #1 + + +module gige_sfp_mdio_TX_STARTUP_FSM # + ( + parameter GT_TYPE = "GTX", + parameter STABLE_CLOCK_PERIOD = 8, // Period of the stable clock driving this state-machine, unit is [ns] + parameter RETRY_COUNTER_BITWIDTH = 8, + parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must + parameter RX_QPLL_USED = "FALSE", // share these two generic values + parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic + // is enough. For single-lane applications the automatic alignment is + // sufficient + ) + ( + input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB + input wire TXUSERCLK, //TXUSERCLK as used in the design + input wire SOFT_RESET, //User Reset, can be pulled any time + input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost + input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost + input wire QPLLLOCK, //Lock Detect from the QPLL of the GT + input wire CPLLLOCK , //Lock Detect from the CPLL of the GT + input wire TXRESETDONE, + input wire MMCM_LOCK, + output reg GTTXRESET = 1'b0, + output reg MMCM_RESET = 1'b1, + output reg QPLL_RESET = 1'b0, //Reset QPLL + output reg CPLL_RESET = 1'b0, //Reset CPLL + output TX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished. + output reg TXUSERRDY = 1'b0, + output RUN_PHALIGNMENT, + output reg RESET_PHALIGNMENT = 1'b0, + input wire PHALIGNMENT_DONE, + + output [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of + // Retries it took to get the transceiver up and running + ); + + +//Interdependencies: +// * Timing depends on the frequency of the stable clock. Hence counters-sizes +// are calculated at design-time based on the Generics +// +// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX +// => signal which PLL has been reset +// * + + + localparam [2:0] + INIT = 3'b000, + ASSERT_ALL_RESETS = 3'b001, + RELEASE_PLL_RESET = 3'b010, + RELEASE_MMCM_RESET = 3'b011, + WAIT_RESET_DONE = 3'b100, + DO_PHASE_ALIGNMENT = 3'b101, + RESET_FSM_DONE = 3'b110; + + reg [2:0] tx_state = INIT; + + + parameter MMCM_LOCK_CNT_MAX = 1024; + parameter STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration + parameter WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration + parameter WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin + + parameter WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD;// 2 ms time-out + parameter WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD;//100 us time-out + parameter WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD;//100 us time-out + + reg [7:0] init_wait_count = 0; + reg init_wait_done = 1'b0; + reg pll_reset_asserted = 1'b0; + + reg tx_fsm_reset_done_int = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg tx_fsm_reset_done_int_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg tx_fsm_reset_done_int_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg tx_fsm_reset_done_int_s3 = 1'b0; + + parameter MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1; + reg [7:0] retry_counter_int = 0; + reg [18:0] time_out_counter = 0; + + reg reset_time_out = 1'b0; + reg time_out_2ms = 1'b0; //--\Flags that the various time-out points + reg time_tlock_max = 1'b0; //--|have been reached. + reg time_out_500us = 1'b0; //--/ + + reg [9:0] mmcm_lock_count = 0; + reg mmcm_lock_int = 1'b0; + reg [3:0] mmcm_lock_reclocked = 3'b0; + + reg run_phase_alignment_int = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg run_phase_alignment_int_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg run_phase_alignment_int_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg run_phase_alignment_int_s3 = 1'b0; + + parameter MAX_WAIT_BYPASS = 110000; //110000 TXUSRCLK cycles is the max time needed for Multilane designs + + reg [16:0] wait_bypass_count = 0; + reg time_out_wait_bypass = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg time_out_wait_bypass_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg time_out_wait_bypass_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg time_out_wait_bypass_s3 = 1'b0; + + (* ASYNC_REG = "TRUE" *) + reg txresetdone_s1 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg txresetdone_s2 = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg txresetdone_s3 = 1'b0; + + wire refclk_lost; + + //Alias section, signals used within this module mapped to output ports: + assign RETRY_COUNTER = retry_counter_int; + assign RUN_PHALIGNMENT = run_phase_alignment_int; + assign TX_FSM_RESET_DONE = tx_fsm_reset_done_int; + + + always @(posedge STABLE_CLOCK) + begin + // The counter starts running when configuration has finished and + // the clock is stable. When its maximum count-value has been reached, + // the 500 ns from Answer Record 43482 have been passed. + if (init_wait_count == WAIT_MAX) + init_wait_done <= `DLY 1'b1; + else + init_wait_count <= `DLY init_wait_count + 1; + end + + + always @(posedge STABLE_CLOCK) + begin + // One common large counter for generating three time-out signals. + // Intermediate time-outs are derived from calculated values, based + // on the period of the provided clock. + if (reset_time_out == 1'b1) + begin + time_out_counter <= `DLY 0; + time_out_2ms <= `DLY 1'b0; + time_tlock_max <= `DLY 1'b0; + time_out_500us <= `DLY 1'b0; + end + else + begin + if (time_out_counter == WAIT_TIMEOUT_2ms) + time_out_2ms <= `DLY 1'b1; + else + time_out_counter <= `DLY time_out_counter + 1; + + if (time_out_counter == WAIT_TLOCK_MAX) + time_tlock_max <= `DLY 1'b1; + + if (time_out_counter == WAIT_TIMEOUT_500us) + time_out_500us <= `DLY 1'b1; + end + end + + always @(posedge TXUSERCLK) + begin + if (MMCM_LOCK == 1'b0) + begin + mmcm_lock_count <= `DLY 0; + mmcm_lock_int <= `DLY 1'b0; + end + else + begin + if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1) + mmcm_lock_count <= `DLY mmcm_lock_count + 1; + else + mmcm_lock_int <= `DLY 1'b1; + end + end + + always @(posedge STABLE_CLOCK) + //Reclocking onto the FSM-clock. + begin + if (MMCM_LOCK == 1'b0) + //The reset-signal is here on purpose. This avoids + //getting the shift-register targetted to an SRL. + //The reason for this is that an SRL will not help + //on the cross-clock domain but "real" Flip-flops will. + + mmcm_lock_reclocked <= `DLY 4'b0000; + else + begin + mmcm_lock_reclocked[3] <= `DLY mmcm_lock_int; + mmcm_lock_reclocked[2:0] <= `DLY mmcm_lock_reclocked[3:1]; + end + end + + + //Clock Domain Crossing + + always @(posedge TXUSERCLK) + begin + run_phase_alignment_int_s1 <= `DLY run_phase_alignment_int; + run_phase_alignment_int_s2 <= `DLY run_phase_alignment_int_s1; + run_phase_alignment_int_s3 <= `DLY run_phase_alignment_int_s2; + + tx_fsm_reset_done_int_s1 <= `DLY tx_fsm_reset_done_int; + tx_fsm_reset_done_int_s2 <= `DLY tx_fsm_reset_done_int_s1; + tx_fsm_reset_done_int_s3 <= `DLY tx_fsm_reset_done_int_s2; + end + + + always @(posedge STABLE_CLOCK) + begin + time_out_wait_bypass_s1 <= `DLY time_out_wait_bypass; + time_out_wait_bypass_s2 <= `DLY time_out_wait_bypass_s1; + time_out_wait_bypass_s3 <= `DLY time_out_wait_bypass_s2; + + txresetdone_s1 <= `DLY TXRESETDONE; + txresetdone_s2 <= `DLY txresetdone_s1; + txresetdone_s3 <= `DLY txresetdone_s2; + end + + always @(posedge TXUSERCLK) + begin + if (run_phase_alignment_int_s3 == 1'b0) + begin + wait_bypass_count <= `DLY 0; + time_out_wait_bypass <= `DLY 1'b0; + end + else if (run_phase_alignment_int_s3 == 1'b1 && tx_fsm_reset_done_int_s3 == 1'b0) + begin + if (wait_bypass_count == MAX_WAIT_BYPASS - 1) + time_out_wait_bypass <= `DLY 1'b1; + else + wait_bypass_count <= `DLY wait_bypass_count + 1; + end + end + + assign refclk_lost = ( TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b1) ? 1'b1 : + ( TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b1) ? 1'b1 : 1'b0; + + + + //FSM for resetting the GTX/GTH/GTP in the 7-series. + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // + // Following steps are performed: + // 1) Only for GTX - After configuration wait for approximately 500 ns as specified in + // answer-record 43482 + // 2) Assert all resets on the GT and on an MMCM potentially connected. + // After that wait until a reference-clock has been detected. + // 3) Release the reset to the GT and wait until the GT-PLL has locked. + // 4) Release the MMCM-reset and wait until the MMCM has signalled lock. + // Also signal to the RX-side which PLL has been reset. + // 5) Wait for the RESET_DONE-signal from the GTX. + // 6) Signal to start the phase-alignment procedure and wait for it to + // finish. + // 7) Reset-sequence has successfully run through. Signal this to the + // rest of the design by asserting TX_FSM_RESET_DONE. + + always @(posedge STABLE_CLOCK) + begin + if (SOFT_RESET == 1'b1 || (tx_state != INIT && tx_state != ASSERT_ALL_RESETS && refclk_lost == 1'b1)) + begin + tx_state <= `DLY INIT; + TXUSERRDY <= `DLY 1'b0; + GTTXRESET <= `DLY 1'b0; + MMCM_RESET <= `DLY 1'b1; + tx_fsm_reset_done_int <= `DLY 1'b0; + QPLL_RESET <= `DLY 1'b0; + CPLL_RESET <= `DLY 1'b0; + pll_reset_asserted <= `DLY 1'b0; + reset_time_out <= `DLY 1'b0; + retry_counter_int <= `DLY 0; + run_phase_alignment_int <= `DLY 1'b0; + RESET_PHALIGNMENT <= `DLY 1'b1; + end + else + begin + case (tx_state) + INIT : + begin + //Initial state after configuration. This state will be left after + //approx. 500 ns and not be re-entered. + if (init_wait_done == 1'b1) + tx_state <= `DLY ASSERT_ALL_RESETS; + reset_time_out <= `DLY 1'b1; + end + + ASSERT_ALL_RESETS : + begin + //This is the state into which the FSM will always jump back if any + //time-outs will occur. + //The number of retries is reported on the output RETRY_COUNTER. In + //case the transceiver never comes up for some reason, this machine + //will still continue its best and rerun until the FPGA is turned off + //or the transceivers come up correctly. + if (TX_QPLL_USED == "TRUE") + begin + if (pll_reset_asserted == 1'b0) + begin + QPLL_RESET <= `DLY 1'b1; + pll_reset_asserted <= `DLY 1'b1; + end + else + QPLL_RESET <= `DLY 1'b0; + end + else + begin + if (pll_reset_asserted == 1'b0) + begin + CPLL_RESET <= `DLY 1'b1; + pll_reset_asserted <= `DLY 1'b1; + end + else + CPLL_RESET <= `DLY 1'b0; + end + TXUSERRDY <= `DLY 1'b0; + GTTXRESET <= `DLY 1'b1; + MMCM_RESET <= `DLY 1'b1; + reset_time_out <= `DLY 1'b0; + run_phase_alignment_int <= `DLY 1'b0; + RESET_PHALIGNMENT <= `DLY 1'b1; + + if ((TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b0 && pll_reset_asserted) || + (TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b0 && pll_reset_asserted)) + tx_state <= `DLY RELEASE_PLL_RESET; + + end + + RELEASE_PLL_RESET : + begin + //PLL-Reset of the GTX gets released and the time-out counter + //starts running. + pll_reset_asserted <= `DLY 1'b1; + + if ((TX_QPLL_USED == "TRUE" && QPLLLOCK == 1'b1) || + (TX_QPLL_USED == "FALSE" && CPLLLOCK == 1'b1)) + begin + tx_state <= `DLY RELEASE_MMCM_RESET; + reset_time_out <= `DLY 1'b1; + end + + if (time_out_2ms == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + retry_counter_int <= `DLY retry_counter_int + 1; + tx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + RELEASE_MMCM_RESET : + begin + GTTXRESET <= `DLY 1'b0; + reset_time_out <= `DLY 1'b0; + //Release of the MMCM-reset. Waiting for the MMCM to lock. + MMCM_RESET <= `DLY 1'b0; + if (mmcm_lock_reclocked[0] == 1'b1) + begin + tx_state <= `DLY WAIT_RESET_DONE; + reset_time_out <= `DLY 1'b1; + end + + if (time_tlock_max == 1'b1 && mmcm_lock_reclocked[0] == 1'b0) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + retry_counter_int <= `DLY retry_counter_int + 1; + tx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + WAIT_RESET_DONE : + begin + TXUSERRDY <= `DLY 1'b1; + reset_time_out <= `DLY 1'b0; + if (txresetdone_s3 == 1'b1) + begin + tx_state <= `DLY DO_PHASE_ALIGNMENT; + reset_time_out <= `DLY 1'b1; + end + + if (time_out_500us == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + retry_counter_int <= `DLY retry_counter_int + 1; + tx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + DO_PHASE_ALIGNMENT : + begin + //The direct handling of the signals for the Phase Alignment is done outside + //this state-machine. + RESET_PHALIGNMENT <= `DLY 1'b0; + run_phase_alignment_int <= `DLY 1'b1; + reset_time_out <= `DLY 1'b0; + + if (PHALIGNMENT_DONE == 1'b1) + tx_state <= `DLY RESET_FSM_DONE; + + if (time_out_wait_bypass_s3 == 1'b1) + begin + if (retry_counter_int == MAX_RETRIES) + // If too many retries are performed compared to what is specified in + // the generic, the counter simply wraps around. + retry_counter_int <= `DLY 0; + else + retry_counter_int <= `DLY retry_counter_int + 1; + tx_state <= `DLY ASSERT_ALL_RESETS; + end + end + + RESET_FSM_DONE : + begin + reset_time_out <= `DLY 1'b1; + tx_fsm_reset_done_int <= `DLY 1'b1; + end + + endcase + end + end + +endmodule diff --git a/fpga/usrp3/top/x300/gige_phy_mdio.v b/fpga/usrp3/top/x300/gige_phy_mdio.v deleted file mode 100644 index a86fee447..000000000 --- a/fpga/usrp3/top/x300/gige_phy_mdio.v +++ /dev/null @@ -1,148 +0,0 @@ - -module gige_phy_mdio - (input reset, - input independent_clock, - input sfp_clk, - input SFP_RX_p, - input SFP_RX_n, - output SFP_TX_p, - output SFP_TX_n, - output gmii_clk, - input [7:0] gmii_txd, - input gmii_tx_en, - input gmii_tx_er, - output [7:0] gmii_rxd, - output gmii_rx_dv, - output gmii_rx_er, - output [31:0] misc_debug, - output [15:0] int_data, - output [15:0] status_vector, - // MDIO signals - input [4:0] prtad, - input mdc, - input mdio_i, - output mdio_o, - output mdio_t - ); - - - wire mmcm_locked, mmcm_reset, resetdone, clkfbout; - wire userclk, userclk2; - wire txoutclk, txoutclk_bufg; - - assign gmii_clk = userclk2; // 125 MHz - - // Route txoutclk input through a BUFG - // FIXME is this really necessary? It seems wasteful. - BUFG bufg_txoutclk (.I (txoutclk), .O (txoutclk_bufg)); - - // This 62.5MHz clock is placed onto global clock routing and is then used - // for tranceiver TXUSRCLK/RXUSRCLK. - BUFG bufg_userclk (.I (clkout1), .O (userclk)); - - // This 125MHz clock is placed onto global clock routing and is then used - // to clock all Ethernet core logic. - BUFG bufg_userclk2 (.I (clkout0), .O (userclk2)); - - // The GT transceiver provides a 62.5MHz clock to the FPGA fabric. This is - // routed to an MMCM module where it is used to create phase and frequency - // related 62.5MHz and 125MHz clock sources - MMCME2_ADV # - (.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (16.000), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (8.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.5), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (16), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.5), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (16.0), - .REF_JITTER1 (0.010) - ) mmcm_adv_inst - (// Output clocks - .CLKFBOUT (clkfbout), - .CLKFBOUTB (), - .CLKOUT0 (clkout0), - .CLKOUT0B (), - .CLKOUT1 (clkout1), - .CLKOUT1B (), - .CLKOUT2 (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - // Input clock control - .CLKFBIN (clkfbout), - .CLKIN1 (txoutclk_bufg), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (), - .DRDY (), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - // Other control and status signals - .LOCKED (mmcm_locked), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_reset) - ); - - assign mmcm_reset = reset | ~resetdone; - - - gige_sfp_mdio_block gige_sfp_mdio_block - ( - .gtrefclk (sfp_clk), - .txp (SFP_TX_p), - .txn (SFP_TX_n), - .rxp (SFP_RX_p), - .rxn (SFP_RX_n), - .txoutclk (txoutclk), - .resetdone (resetdone), - .mmcm_locked (mmcm_locked), - .userclk (userclk), - .userclk2 (userclk2), - .independent_clock_bufg(independent_clock), - .pma_reset (reset), - .gmii_txd (gmii_txd), - .gmii_tx_en (gmii_tx_en), - .gmii_tx_er (gmii_tx_er), - .gmii_rxd (gmii_rxd), - .gmii_rx_dv (gmii_rx_dv), - .gmii_rx_er (gmii_rx_er), - .gmii_isolate (), // Unused - .mdc (mdc), - .mdio_i (mdio_i), - .mdio_o (mdio_o), - .mdio_t (mdio_t), - .phyad (prtad), - .configuration_vector (5'b00000), - .configuration_valid (1'b1), //default - .status_vector (status_vector), - .reset (reset), - .signal_detect (1'b1) - ); - - -endmodule // gige_phy diff --git a/fpga/usrp3/top/x300/ten_gige_phy/README b/fpga/usrp3/top/x300/ten_gige_phy/README new file mode 100644 index 000000000..217e6571a --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/README @@ -0,0 +1 @@ +The files in this directory have been adapted from the "Ten Gigabit EthernetPCS/PMA or SGMII (10GBASE-R/KR)" Xilinx IPCore example design. diff --git a/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v b/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v new file mode 100755 index 000000000..8f608bcaf --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v @@ -0,0 +1,131 @@ +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +`timescale 1ns / 1ps + +//***********************************Entity Declaration******************************* +module ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE +( + // IJB. Remove IBUFDS_GTE2 from 10G PHY hierarchy so that it can be shared. + // + //input wire Q1_CLK0_GTREFCLK_PAD_N_IN, + //input wire Q1_CLK0_GTREFCLK_PAD_P_IN, + //output wire Q1_CLK0_GTREFCLK_OUT, + + output GT0_TXUSRCLK_OUT, + output GT0_TXUSRCLK2_OUT, + input GT0_TXOUTCLK_IN, + output GT0_RXUSRCLK_OUT, + output GT0_RXUSRCLK2_OUT, + input GT0_RXOUTCLK_IN, + input DRPCLK_IN, + output DRPCLK_OUT + +); + + +`define DLY #1 + +//*********************************Wire Declarations********************************** + + wire tied_to_ground_i; + wire tied_to_vcc_i; + + wire gt0_txoutclk_i; + wire gt0_rxoutclk_i; + +// wire q1_clk0_gtrefclk; + + wire gt0_txusrclk_i; + wire gt0_rxusrclk_i; + +//*********************************** Beginning of Code ******************************* + + // Static signal Assigments + assign tied_to_ground_i = 1'b0; + assign tied_to_vcc_i = 1'b1; + assign gt0_txoutclk_i = GT0_TXOUTCLK_IN; + assign gt0_rxoutclk_i = GT0_RXOUTCLK_IN; + +// assign Q1_CLK0_GTREFCLK_OUT = q1_clk0_gtrefclk; + + //IBUFDS_GTE2 +/* -----\/----- EXCLUDED -----\/----- + IBUFDS_GTE2 ibufds_instQ1_CLK0 + ( + .O (q1_clk0_gtrefclk), + .ODIV2 (), + .CEB (tied_to_ground_i), + .I (Q1_CLK0_GTREFCLK_PAD_P_IN), + .IB (Q1_CLK0_GTREFCLK_PAD_N_IN) + ); + -----/\----- EXCLUDED -----/\----- */ + + BUFG txoutclk_bufg0_i + ( + .I (gt0_txoutclk_i), + .O (gt0_txusrclk_i) + ); + + + BUFG rxoutclk_bufg1_i + ( + .I (gt0_rxoutclk_i), + .O (gt0_rxusrclk_i) + ); + + + + + + assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i; + assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i; + assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i; + assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i; + +endmodule + diff --git a/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v b/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v new file mode 100755 index 000000000..06b9caeda --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v @@ -0,0 +1,367 @@ +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +`default_nettype wire + +`timescale 1ns / 1ps +`define DLY #1 + +//***************************** Entity Declaration **************************** + +module ten_gig_eth_pcs_pma_gtwizard_10gbaser # +( + // Simulation attributes + parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false", // Set to "true" to speed up sim reset + parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C, + parameter PMA_RSV_IN = 32'h001E7080, + parameter SIM_VERSION = "4.0" +) +( + //_________________________________________________________________________ + //_________________________________________________________________________ + //GT0 (X0Y0) + //____________________________CHANNEL PORTS________________________________ + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + input [8:0] GT0_DRPADDR_IN, + input GT0_DRPCLK_IN, + input [15:0] GT0_DRPDI_IN, + output [15:0] GT0_DRPDO_OUT, + input GT0_DRPEN_IN, + output GT0_DRPRDY_OUT, + input GT0_DRPWE_IN, + //----------------------------- Eye Scan Ports ----------------------------- + output GT0_EYESCANDATAERROR_OUT, + //---------------------- Loopback and Powerdown Ports ---------------------- + input [2:0] GT0_LOOPBACK_IN, + //----------------------------- Receive Ports ------------------------------ + input GT0_RXUSERRDY_IN, + //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- + output GT0_RXDATAVALID_OUT, + input GT0_RXGEARBOXSLIP_IN, + output [1:0] GT0_RXHEADER_OUT, + output GT0_RXHEADERVALID_OUT, + //--------------------- Receive Ports - PRBS Detection --------------------- + input GT0_RXPRBSCNTRESET_IN, + output GT0_RXPRBSERR_OUT, + input [2:0] GT0_RXPRBSSEL_IN, + //----------------- Receive Ports - RX Data Path interface ----------------- + input GT0_GTRXRESET_IN, + output [31:0] GT0_RXDATA_OUT, + output GT0_RXOUTCLK_OUT, + input GT0_RXPCSRESET_IN, + input GT0_RXUSRCLK_IN, + input GT0_RXUSRCLK2_IN, + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + input GT0_GTXRXN_IN, + input GT0_GTXRXP_IN, + output GT0_RXCDRLOCK_OUT, + output GT0_RXELECIDLE_OUT, + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + input GT0_RXBUFRESET_IN, + output [2:0] GT0_RXBUFSTATUS_OUT, + //---------------------- Receive Ports - RX Equalizer ---------------------- + input GT0_RXLPMEN_IN, + //---------------------- Receive Ports - RX PLL Ports ---------------------- + output GT0_RXRESETDONE_OUT, + //----------------------------- Transmit Ports ----------------------------- + input GT0_TXUSERRDY_IN, + //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ + input [1:0] GT0_TXHEADER_IN, + input [6:0] GT0_TXSEQUENCE_IN, + //---------------- Transmit Ports - TX Data Path interface ----------------- + input GT0_GTTXRESET_IN, + input [31:0] GT0_TXDATA_IN, + output GT0_TXOUTCLK_OUT, + output GT0_TXOUTCLKFABRIC_OUT, + output GT0_TXOUTCLKPCS_OUT, + input GT0_TXPCSRESET_IN, + input GT0_TXUSRCLK_IN, + input GT0_TXUSRCLK2_IN, + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + output GT0_GTXTXN_OUT, + output GT0_GTXTXP_OUT, + input GT0_TXINHIBIT_IN, + input [4:0] GT0_TXPRECURSOR_IN, + input [4:0] GT0_TXPOSTCURSOR_IN, + input [6:0] GT0_TXMAINCURSOR_IN, + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + output GT0_TXRESETDONE_OUT, + //------------------- Transmit Ports - TX PRBS Generator ------------------- + input [2:0] GT0_TXPRBSSEL_IN, + + + //____________________________COMMON PORTS________________________________ + //-------------------- Common Block - Ref Clock Ports --------------------- + input GT0_GTREFCLK0_COMMON_IN, + //----------------------- Common Block - QPLL Ports ------------------------ + output GT0_QPLLLOCK_OUT, + input GT0_QPLLLOCKDETCLK_IN, + output GT0_QPLLREFCLKLOST_OUT, + input GT0_QPLLRESET_IN + + +); +//***************************** Parameter Declarations ************************ + parameter QPLL_FBDIV_TOP = 66; + + parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 : + (QPLL_FBDIV_TOP == 20) ? 10'b0000110000 : + (QPLL_FBDIV_TOP == 32) ? 10'b0001100000 : + (QPLL_FBDIV_TOP == 40) ? 10'b0010000000 : + (QPLL_FBDIV_TOP == 64) ? 10'b0011100000 : + (QPLL_FBDIV_TOP == 66) ? 10'b0101000000 : + (QPLL_FBDIV_TOP == 80) ? 10'b0100100000 : + (QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000; + + parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 : + (QPLL_FBDIV_TOP == 20) ? 1'b1 : + (QPLL_FBDIV_TOP == 32) ? 1'b1 : + (QPLL_FBDIV_TOP == 40) ? 1'b1 : + (QPLL_FBDIV_TOP == 64) ? 1'b1 : + (QPLL_FBDIV_TOP == 66) ? 1'b0 : + (QPLL_FBDIV_TOP == 80) ? 1'b1 : + (QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1; + +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + + wire gt0_qplloutclk_i; + wire gt0_qplloutrefclk_i; + + wire gt0_qpllclk_i; + wire gt0_qpllrefclk_i; + + +//********************************* Main Body of Code************************** + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + + assign gt0_qpllclk_i = gt0_qplloutclk_i; + assign gt0_qpllrefclk_i = gt0_qplloutrefclk_i; + + +//------------------------- GT Instances ------------------------------- + //_________________________________________________________________________ + //_________________________________________________________________________ + //GT0 (X0Y0) + + ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT # + ( + // Simulation attributes + .GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION), + .RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN), + .PCS_RSVD_ATTR_IN (48'h000000000000), + .PMA_RSV_IN (PMA_RSV_IN) + ) + gt0_gtwizard_10gbaser_i + ( + //-------------------------------- Channel --------------------------------- + .QPLLCLK_IN (gt0_qpllclk_i), + .QPLLREFCLK_IN (gt0_qpllrefclk_i), + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + .DRPADDR_IN (GT0_DRPADDR_IN), + .DRPCLK_IN (GT0_DRPCLK_IN), + .DRPDI_IN (GT0_DRPDI_IN), + .DRPDO_OUT (GT0_DRPDO_OUT), + .DRPEN_IN (GT0_DRPEN_IN), + .DRPRDY_OUT (GT0_DRPRDY_OUT), + .DRPWE_IN (GT0_DRPWE_IN), + //----------------------------- Eye Scan Ports ----------------------------- + .EYESCANDATAERROR_OUT (GT0_EYESCANDATAERROR_OUT), + //---------------------- Loopback and Powerdown Ports ---------------------- + .LOOPBACK_IN (GT0_LOOPBACK_IN), + //----------------------------- Receive Ports ------------------------------ + .RXUSERRDY_IN (GT0_RXUSERRDY_IN), + //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- + .RXDATAVALID_OUT (GT0_RXDATAVALID_OUT), + .RXGEARBOXSLIP_IN (GT0_RXGEARBOXSLIP_IN), + .RXHEADER_OUT (GT0_RXHEADER_OUT), + .RXHEADERVALID_OUT (GT0_RXHEADERVALID_OUT), + //--------------------- Receive Ports - PRBS Detection --------------------- + .RXPRBSCNTRESET_IN (GT0_RXPRBSCNTRESET_IN), + .RXPRBSERR_OUT (GT0_RXPRBSERR_OUT), + .RXPRBSSEL_IN (GT0_RXPRBSSEL_IN), + //----------------- Receive Ports - RX Data Path interface ----------------- + .GTRXRESET_IN (GT0_GTRXRESET_IN), + .RXDATA_OUT (GT0_RXDATA_OUT), + .RXOUTCLK_OUT (GT0_RXOUTCLK_OUT), + .RXPCSRESET_IN (GT0_RXPCSRESET_IN), + .RXUSRCLK_IN (GT0_RXUSRCLK_IN), + .RXUSRCLK2_IN (GT0_RXUSRCLK2_IN), + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + .GTXRXN_IN (GT0_GTXRXN_IN), + .GTXRXP_IN (GT0_GTXRXP_IN), + .RXCDRLOCK_OUT (GT0_RXCDRLOCK_OUT), + .RXELECIDLE_OUT (GT0_RXELECIDLE_OUT), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + .RXBUFRESET_IN (GT0_RXBUFRESET_IN), + .RXBUFSTATUS_OUT (GT0_RXBUFSTATUS_OUT), + //---------------------- Receive Ports - RX Equalizer ---------------------- + .RXLPMEN_IN (GT0_RXLPMEN_IN), + //---------------------- Receive Ports - RX PLL Ports ---------------------- + .RXRESETDONE_OUT (GT0_RXRESETDONE_OUT), + //----------------------------- Transmit Ports ----------------------------- + .TXUSERRDY_IN (GT0_TXUSERRDY_IN), + //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ + .TXHEADER_IN (GT0_TXHEADER_IN), + .TXSEQUENCE_IN (GT0_TXSEQUENCE_IN), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .GTTXRESET_IN (GT0_GTTXRESET_IN), + .TXDATA_IN (GT0_TXDATA_IN), + .TXOUTCLK_OUT (GT0_TXOUTCLK_OUT), + .TXOUTCLKFABRIC_OUT (GT0_TXOUTCLKFABRIC_OUT), + .TXOUTCLKPCS_OUT (GT0_TXOUTCLKPCS_OUT), + .TXPCSRESET_IN (GT0_TXPCSRESET_IN), + .TXUSRCLK_IN (GT0_TXUSRCLK_IN), + .TXUSRCLK2_IN (GT0_TXUSRCLK2_IN), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GTXTXN_OUT (GT0_GTXTXN_OUT), + .GTXTXP_OUT (GT0_GTXTXP_OUT), + .TXINHIBIT_IN (GT0_TXINHIBIT_IN), + .TXPRECURSOR_IN (GT0_TXPRECURSOR_IN), + .TXPOSTCURSOR_IN (GT0_TXPOSTCURSOR_IN), + .TXMAINCURSOR_IN (GT0_TXMAINCURSOR_IN), + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + .TXRESETDONE_OUT (GT0_TXRESETDONE_OUT), + //------------------- Transmit Ports - TX PRBS Generator ------------------- + .TXPRBSSEL_IN (GT0_TXPRBSSEL_IN) + + ); + + + //_________________________________________________________________________ + //_________________________________________________________________________ + //_________________________GTXE2_COMMON____________________________________ + + GTXE2_COMMON # + ( + // Simulation attributes + .SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION (SIM_VERSION), + + + //----------------COMMON BLOCK Attributes--------------- + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (27'h0680181), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV_IN), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (1) + + ) + gtxe2_common_0_i + ( + //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + .DRPADDR (tied_to_ground_vec_i[7:0]), + .DRPCLK (tied_to_ground_i), + .DRPDI (tied_to_ground_vec_i[15:0]), + .DRPDO (), + .DRPEN (tied_to_ground_i), + .DRPRDY (), + .DRPWE (tied_to_ground_i), + //-------------------- Common Block - Ref Clock Ports --------------------- + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN), + .GTREFCLK1 (tied_to_ground_i), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //----------------------- Common Block - QPLL Ports ------------------------ + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .QPLLLOCK (GT0_QPLLLOCK_OUT), + .QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN), + .QPLLLOCKEN (tied_to_vcc_i), + .QPLLOUTCLK (gt0_qplloutclk_i), + .QPLLOUTREFCLK (gt0_qplloutrefclk_i), + .QPLLOUTRESET (tied_to_ground_i), + .QPLLPD (tied_to_ground_i), + .QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT), + .QPLLREFCLKSEL (3'b001), + .QPLLRESET (GT0_QPLLRESET_IN), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + .REFCLKOUTMONITOR (), + //--------------------------- Common Block Ports --------------------------- + .BGBYPASSB (tied_to_vcc_i), + .BGMONITORENB (tied_to_vcc_i), + .BGPDB (tied_to_vcc_i), + .BGRCALOVRD (5'b00000), + .PMARSVD (8'b00000000), + .RCALENB (tied_to_vcc_i) + + ); + + + + +endmodule + + + diff --git a/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v b/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v new file mode 100755 index 000000000..6638ffefa --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v @@ -0,0 +1,732 @@ +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +`default_nettype wire + +`timescale 1ns / 1ps + + +//***************************** Entity Declaration **************************** + +module ten_gig_eth_pcs_pma_gtwizard_10gbaser_GT # +( + // Simulation attributes + parameter GT_SIM_GTRESET_SPEEDUP = "false", // Set to 1 to speed up sim reset; + parameter RX_DFE_KL_CFG2_IN = 32'h3008E56A, + parameter PMA_RSV_IN = 32'h00000000, + parameter PCS_RSVD_ATTR_IN = 48'h000000000000, + parameter SIM_VERSION = ("4.0") +) +( + //-------------------------------- Channel --------------------------------- + input QPLLCLK_IN, + input QPLLREFCLK_IN, + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + input [8:0] DRPADDR_IN, + input DRPCLK_IN, + input [15:0] DRPDI_IN, + output [15:0] DRPDO_OUT, + input DRPEN_IN, + output DRPRDY_OUT, + input DRPWE_IN, + //----------------------------- Eye Scan Ports ----------------------------- + output EYESCANDATAERROR_OUT, + //---------------------- Loopback and Powerdown Ports ---------------------- + input [2:0] LOOPBACK_IN, + //----------------------------- Receive Ports ------------------------------ + input RXUSERRDY_IN, + //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- + output RXDATAVALID_OUT, + input RXGEARBOXSLIP_IN, + output [1:0] RXHEADER_OUT, + output RXHEADERVALID_OUT, + //--------------------- Receive Ports - PRBS Detection --------------------- + input RXPRBSCNTRESET_IN, + output RXPRBSERR_OUT, + input [2:0] RXPRBSSEL_IN, + //----------------- Receive Ports - RX Data Path interface ----------------- + input GTRXRESET_IN, + output [31:0] RXDATA_OUT, + output RXOUTCLK_OUT, + input RXPCSRESET_IN, + input RXUSRCLK_IN, + input RXUSRCLK2_IN, + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + input GTXRXN_IN, + input GTXRXP_IN, + output RXCDRLOCK_OUT, + output RXELECIDLE_OUT, + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + input RXBUFRESET_IN, + output [2:0] RXBUFSTATUS_OUT, + //---------------------- Receive Ports - RX Equalizer ---------------------- + input RXLPMEN_IN, + //---------------------- Receive Ports - RX PLL Ports ---------------------- + output RXRESETDONE_OUT, + //----------------------------- Transmit Ports ----------------------------- + input TXUSERRDY_IN, + //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ + input [1:0] TXHEADER_IN, + input [6:0] TXSEQUENCE_IN, + //---------------- Transmit Ports - TX Data Path interface ----------------- + input GTTXRESET_IN, + input [31:0] TXDATA_IN, + output TXOUTCLK_OUT, + output TXOUTCLKFABRIC_OUT, + output TXOUTCLKPCS_OUT, + input TXPCSRESET_IN, + input TXUSRCLK_IN, + input TXUSRCLK2_IN, + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + output GTXTXN_OUT, + output GTXTXP_OUT, + input TXINHIBIT_IN, + input [4:0] TXPRECURSOR_IN, + input [4:0] TXPOSTCURSOR_IN, + input [6:0] TXMAINCURSOR_IN, + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + output TXRESETDONE_OUT, + //------------------- Transmit Ports - TX PRBS Generator ------------------- + input [2:0] TXPRBSSEL_IN + + +); + + +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + + + //RX Datapath signals + wire [63:0] rxdata_i; + wire [5:0] rxchariscomma_float_i; + wire [5:0] rxcharisk_float_i; + wire [5:0] rxdisperr_float_i; + wire [5:0] rxnotintable_float_i; + wire [5:0] rxrundisp_float_i; + + + //TX Datapath signals + wire [63:0] txdata_i; + wire [5:0] txkerr_float_i; + wire [5:0] txrundisp_float_i; + +// +//********************************* Main Body of Code************************** + + //------------------------- Static signal Assigments --------------------- + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + //------------------- GT Datapath byte mapping ----------------- + + //The GT deserializes the rightmost parallel bit (LSb) first + assign RXDATA_OUT = rxdata_i[31:0]; + + //The GT serializes the rightmost parallel bit (LSb) first + assign txdata_i = {tied_to_ground_vec_i[31:0], TXDATA_IN}; + + + + + //------------------------- GT Instantiations -------------------------- + GTXE2_CHANNEL # + ( + //_______________________ Simulation-Only Attributes __________________ + + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), + .SIM_RESET_SPEEDUP (GT_SIM_GTRESET_SPEEDUP), + .SIM_CPLLREFCLK_SEL (3'b001), + .SIM_VERSION (SIM_VERSION), + + + //----------------RX Byte and Word Alignment Attributes--------------- + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET ("FALSE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("FALSE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .SHOW_REALIGN_COMMA ("TRUE"), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RX_SIG_VALID_DLY (10), + + //----------------RX 8B/10B Decoder Attributes--------------- + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .DEC_MCOMMA_DETECT ("FALSE"), + .DEC_PCOMMA_DETECT ("FALSE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + + //----------------------RX Clock Correction Attributes---------------------- + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (19), + .CLK_COR_MIN_LAT (15), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_LEN (1), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_1_1 (10'b0000000000), + .CLK_COR_SEQ_1_2 (10'b0000000000), + .CLK_COR_SEQ_1_3 (10'b0000000000), + .CLK_COR_SEQ_1_4 (10'b0000000000), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0000000000), + .CLK_COR_SEQ_2_2 (10'b0000000000), + .CLK_COR_SEQ_2_3 (10'b0000000000), + .CLK_COR_SEQ_2_4 (10'b0000000000), + + //----------------------RX Channel Bonding Attributes---------------------- + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_LEN (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + + //-------------------------RX Margin Analysis Attributes---------------------------- + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("FALSE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER (80'h00000000000000000000), + .ES_QUAL_MASK (80'h00000000000000000000), + .ES_SDATA_MASK (80'h00000000000000000000), + .ES_VERT_OFFSET (9'b000000000), + + //-----------------------FPGA RX Interface Attributes------------------------- + .RX_DATA_WIDTH (32), + + //-------------------------PMA Attributes---------------------------- + .OUTREFCLK_SEL_INV (2'b11), + .PMA_RSV (PMA_RSV_IN), + .PMA_RSV2 (16'h2050), + .PMA_RSV3 (2'b00), + .PMA_RSV4 (32'h00000000), + .RX_BIAS_CFG (12'b000000000100), + .DMONITOR_CFG (24'h000A00), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (3'b010), + .RX_DEBUG_CFG (12'b000000000000), + .RX_OS_CFG (13'b0000010000000), + .TERM_RCAL_CFG (5'b10000), + .TERM_RCAL_OVRD (1'b0), + .TST_RSV (32'h00000000), + .RX_CLK25_DIV (7), + .TX_CLK25_DIV (7), + .UCODEER_CLR (1'b0), + + //-------------------------PCI Express Attributes---------------------------- + .PCS_PCIE_EN ("FALSE"), + + //-------------------------PCS Attributes---------------------------- + .PCS_RSVD_ATTR (PCS_RSVD_ATTR_IN), + + //-----------RX Buffer Attributes------------ + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RX_BUFFER_CFG (6'b000000), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUFRESET_TIME (5'b00001), + .RXBUF_THRESH_OVFLW (61), + .RXBUF_THRESH_OVRD ("FALSE"), + .RXBUF_THRESH_UNDFLW (4), + .RXDLY_CFG (16'h001F), + .RXDLY_LCFG (9'h030), + .RXDLY_TAP_CFG (16'h0000), + .RXPH_CFG (24'h000000), + .RXPHDLY_CFG (24'h084020), + .RXPH_MONITOR_SEL (5'b00000), + .RX_XCLK_SEL ("RXREC"), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + + //---------------------CDR Attributes------------------------- + .RXCDR_CFG (72'h0b000023ff10400020), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCDR_LOCK_CFG (6'b010101), + + //-----------------RX Initialization and Reset Attributes------------------- + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXISCANRESET_TIME (5'b00001), + .RXPCSRESET_TIME (5'b00001), + .RXPMARESET_TIME (5'b00011), + + //-----------------RX OOB Signaling Attributes------------------- + .RXOOB_CFG (7'b0000110), + + //-----------------------RX Gearbox Attributes--------------------------- + .RXGEARBOX_EN ("TRUE"), + .GEARBOX_MODE (3'b001), + + //-----------------------PRBS Detection Attribute----------------------- + .RXPRBS_ERR_LOOPBACK (1'b0), + + //-----------Power-Down Attributes---------- + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h19), + .PD_TRANS_TIME_TO_P2 (8'h64), + + //-----------RX OOB Signaling Attributes---------- + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + + //-----------RX Fabric Clock Output Control Attributes---------- + .TRANS_TIME_RATE (8'h0E), + + //------------TX Buffer Attributes---------------- + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h001F), + .TXDLY_LCFG (9'h030), + .TXDLY_TAP_CFG (16'h0000), + .TXPH_CFG (16'h0780), + .TXPHDLY_CFG (24'h084020), + .TXPH_MONITOR_SEL (5'b00000), + .TX_XCLK_SEL ("TXOUT"), + + //-----------------------FPGA TX Interface Attributes------------------------- + .TX_DATA_WIDTH (32), + + //-----------------------TX Configurable Driver Attributes------------------------- + .TX_DEEMPH0 (5'b00000), + .TX_DEEMPH1 (5'b00000), + .TX_EIDLE_ASSERT_DELAY (3'b110), + .TX_EIDLE_DEASSERT_DELAY (3'b100), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_DRIVE_MODE ("DIRECT"), + .TX_MARGIN_FULL_0 (7'b1001110), + .TX_MARGIN_FULL_1 (7'b1001001), + .TX_MARGIN_FULL_2 (7'b1000101), + .TX_MARGIN_FULL_3 (7'b1000010), + .TX_MARGIN_FULL_4 (7'b1000000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000100), + .TX_MARGIN_LOW_2 (7'b1000010), + .TX_MARGIN_LOW_3 (7'b1000000), + .TX_MARGIN_LOW_4 (7'b1000000), + + //-----------------------TX Gearbox Attributes-------------------------- + .TXGEARBOX_EN ("TRUE"), + + //-----------------------TX Initialization and Reset Attributes-------------------------- + .TXPCSRESET_TIME (5'b00001), + .TXPMARESET_TIME (5'b00001), + + //-----------------------TX Receiver Detection Attributes-------------------------- + .TX_RXDETECT_CFG (14'h1832), + .TX_RXDETECT_REF (3'b100), + + //--------------------------CPLL Attributes---------------------------- + .CPLL_CFG (24'hBC07DC), + .CPLL_FBDIV (4), + .CPLL_FBDIV_45 (5), + .CPLL_INIT_CFG (24'h00001E), + .CPLL_LOCK_CFG (16'h01E8), + .CPLL_REFCLK_DIV (1), + .RXOUT_DIV (1), + .TXOUT_DIV (1), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + + //------------RX Initialization and Reset Attributes------------- + .RXDFELPMRESET_TIME (7'b0001111), + + //------------RX Equalizer Attributes------------- + .RXLPM_HF_CFG (14'b00000011110000), + .RXLPM_LF_CFG (14'b00000011110000), + .RX_DFE_GAIN_CFG (23'h020FEA), + .RX_DFE_H2_CFG (12'b000000000000), + .RX_DFE_H3_CFG (12'b000001000000), + .RX_DFE_H4_CFG (11'b00011110000), + .RX_DFE_H5_CFG (11'b00011100000), + .RX_DFE_KL_CFG (13'b0000011111110), + .RX_DFE_LPM_CFG (16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DFE_UT_CFG (17'b10001111000000000), + .RX_DFE_VP_CFG (17'b00011111100000011), + + //-----------------------Power-Down Attributes------------------------- + .RX_CLKMUX_PD (1'b1), + .TX_CLKMUX_PD (1'b1), + + //-----------------------FPGA RX Interface Attribute------------------------- + .RX_INT_DATAWIDTH (1), + + //-----------------------FPGA TX Interface Attribute------------------------- + .TX_INT_DATAWIDTH (1), + + //----------------TX Configurable Driver Attributes--------------- + .TX_QPI_STATUS_EN (1'b0), + + //-----------------------RX Equalizer Attributes-------------------------- + .RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2_IN), + .RX_DFE_XYD_CFG (13'b0000000000000), + + //-----------------------TX Configurable Driver Attributes-------------------------- + .TX_PREDRIVER_MODE (1'b0) + + + ) + gtxe2_i + ( + + //-------------------------------- Channel --------------------------------- + .CFGRESET (tied_to_ground_i), + .CLKRSVD (4'b0000), + .DMONITOROUT (), + .GTRESETSEL (tied_to_ground_i), + .GTRSVD (16'b0000000000000000), + .QPLLCLK (QPLLCLK_IN), + .QPLLREFCLK (QPLLREFCLK_IN), + .RESETOVRD (tied_to_ground_i), + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + .DRPADDR (DRPADDR_IN), + .DRPCLK (DRPCLK_IN), + .DRPDI (DRPDI_IN), + .DRPDO (DRPDO_OUT), + .DRPEN (DRPEN_IN), + .DRPRDY (DRPRDY_OUT), + .DRPWE (DRPWE_IN), + //----------------------- Channel - Ref Clock Ports ------------------------ + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (tied_to_ground_i), + .GTREFCLK1 (tied_to_ground_i), + .GTREFCLKMONITOR (), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //------------------------------ Channel PLL ------------------------------- + .CPLLFBCLKLOST (), + .CPLLLOCK (), + .CPLLLOCKDETCLK (tied_to_ground_i), + .CPLLLOCKEN (tied_to_vcc_i), + .CPLLPD (tied_to_vcc_i), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (tied_to_ground_i), + //----------------------------- Eye Scan Ports ----------------------------- + .EYESCANDATAERROR (EYESCANDATAERROR_OUT), + .EYESCANMODE (tied_to_ground_i), + .EYESCANRESET (tied_to_ground_i), + .EYESCANTRIGGER (tied_to_ground_i), + //---------------------- Loopback and Powerdown Ports ---------------------- + .LOOPBACK (LOOPBACK_IN), + .RXPD (2'b00), + .TXPD (2'b00), + //--------------------------- PCS Reserved Ports --------------------------- + .PCSRSVDIN (16'b0000000000000000), + .PCSRSVDIN2 (5'b00000), + .PCSRSVDOUT (), + //--------------------------- PMA Reserved Ports --------------------------- + .PMARSVDIN (5'b00000), + .PMARSVDIN2 (5'b00000), + //----------------------------- Receive Ports ------------------------------ + .RXQPIEN (tied_to_ground_i), + .RXQPISENN (), + .RXQPISENP (), + .RXSYSCLKSEL (2'b11), + .RXUSERRDY (RXUSERRDY_IN), + //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- + .RXDATAVALID (RXDATAVALID_OUT), + .RXGEARBOXSLIP (RXGEARBOXSLIP_IN), + .RXHEADER ({rxheader_float_i,RXHEADER_OUT}), + .RXHEADERVALID (RXHEADERVALID_OUT), + .RXSTARTOFSEQ (), + //--------------------- Receive Ports - 8b10b Decoder ---------------------- + .RX8B10BEN (tied_to_ground_i), + .RXCHARISCOMMA (), + .RXCHARISK (), + .RXDISPERR (), + .RXNOTINTABLE (), + //----------------- Receive Ports - Channel Bonding Ports ------------------ + .RXCHANBONDSEQ (), + .RXCHBONDEN (tied_to_ground_i), + .RXCHBONDI (5'b00000), + .RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]), + .RXCHBONDMASTER (tied_to_ground_i), + .RXCHBONDO (), + .RXCHBONDSLAVE (tied_to_ground_i), + //----------------- Receive Ports - Channel Bonding Ports ----------------- + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + //----------------- Receive Ports - Clock Correction Ports ----------------- + .RXCLKCORCNT (), + //------------- Receive Ports - Comma Detection and Alignment -------------- + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCOMMADET (), + .RXCOMMADETEN (tied_to_ground_i), + .RXMCOMMAALIGNEN (tied_to_ground_i), + .RXPCOMMAALIGNEN (tied_to_ground_i), + .RXSLIDE (RXGEARBOXSLIP_IN), + //--------------------- Receive Ports - PRBS Detection --------------------- + .RXPRBSCNTRESET (RXPRBSCNTRESET_IN), + .RXPRBSERR (RXPRBSERR_OUT), + .RXPRBSSEL (RXPRBSSEL_IN), + //----------------- Receive Ports - RX Data Path interface ----------------- + .GTRXRESET (GTRXRESET_IN), + .RXDATA (rxdata_i), + .RXOUTCLK (RXOUTCLK_OUT), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (3'b010), + .RXPCSRESET (RXPCSRESET_IN), + .RXPMARESET (tied_to_ground_i), + .RXUSRCLK (RXUSRCLK_IN), + .RXUSRCLK2 (RXUSRCLK2_IN), + //---------- Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + .RXDFEAGCHOLD (tied_to_ground_i), + .RXDFEAGCOVRDEN (tied_to_ground_i), + .RXDFECM1EN (tied_to_ground_i), + .RXDFELFHOLD (tied_to_ground_i), + .RXDFELFOVRDEN (tied_to_vcc_i), + .RXDFELPMRESET (tied_to_ground_i), + .RXDFETAP2HOLD (tied_to_ground_i), + .RXDFETAP2OVRDEN (tied_to_ground_i), + .RXDFETAP3HOLD (tied_to_ground_i), + .RXDFETAP3OVRDEN (tied_to_ground_i), + .RXDFETAP4HOLD (tied_to_ground_i), + .RXDFETAP4OVRDEN (tied_to_ground_i), + .RXDFETAP5HOLD (tied_to_ground_i), + .RXDFETAP5OVRDEN (tied_to_ground_i), + .RXDFEUTHOLD (tied_to_ground_i), + .RXDFEUTOVRDEN (tied_to_ground_i), + .RXDFEVPHOLD (tied_to_ground_i), + .RXDFEVPOVRDEN (tied_to_ground_i), + .RXDFEVSEN (tied_to_ground_i), + .RXDFEXYDEN (tied_to_ground_i), + .RXDFEXYDHOLD (tied_to_ground_i), + .RXDFEXYDOVRDEN (tied_to_ground_i), + .RXMONITOROUT (), + .RXMONITORSEL (2'b00), + .RXOSHOLD (tied_to_ground_i), + .RXOSOVRDEN (tied_to_ground_i), + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + .GTXRXN (GTXRXN_IN), + .GTXRXP (GTXRXP_IN), + .RXCDRFREQRESET (tied_to_ground_i), + .RXCDRHOLD (tied_to_ground_i), + .RXCDRLOCK (RXCDRLOCK_OUT), + .RXCDROVRDEN (tied_to_ground_i), + .RXCDRRESET (tied_to_ground_i), + .RXCDRRESETRSV (tied_to_ground_i), + .RXELECIDLE (RXELECIDLE_OUT), + .RXELECIDLEMODE (2'b11), + .RXLPMHFHOLD (tied_to_ground_i), + .RXLPMHFOVRDEN (tied_to_ground_i), + .RXLPMLFHOLD (tied_to_ground_i), + .RXLPMLFKLOVRDEN (tied_to_ground_i), + .RXOOBRESET (tied_to_ground_i), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + .RXBUFRESET (RXBUFRESET_IN), + .RXBUFSTATUS (RXBUFSTATUS_OUT), + .RXDDIEN (tied_to_ground_i), + .RXDLYBYPASS (tied_to_vcc_i), + .RXDLYEN (tied_to_ground_i), + .RXDLYOVRDEN (tied_to_ground_i), + .RXDLYSRESET (tied_to_ground_i), + .RXDLYSRESETDONE (), + .RXPHALIGN (tied_to_ground_i), + .RXPHALIGNDONE (), + .RXPHALIGNEN (tied_to_ground_i), + .RXPHDLYPD (tied_to_ground_i), + .RXPHDLYRESET (tied_to_ground_i), + .RXPHMONITOR (), + .RXPHOVRDEN (tied_to_ground_i), + .RXPHSLIPMONITOR (), + .RXSTATUS (), + //---------------------- Receive Ports - RX Equalizer ---------------------- + .RXLPMEN (RXLPMEN_IN), + //---------------------- Receive Ports - RX PLL Ports ---------------------- + .RXRATE (tied_to_ground_vec_i[2:0]), + .RXRATEDONE (), + .RXRESETDONE (RXRESETDONE_OUT), + //------------ Receive Ports - RX Pipe Control for PCI Express ------------- + .PHYSTATUS (), + .RXVALID (), + //--------------- Receive Ports - RX Polarity Control Ports ---------------- + .RXPOLARITY (tied_to_ground_i), + //------------------- Receive Ports - RX Ports for SATA -------------------- + .RXCOMINITDET (), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + //----------------------------- Transmit Ports ----------------------------- + .SETERRSTATUS (tied_to_ground_i), + .TSTIN (20'b11111111111111111111), + .TSTOUT (), + .TXPHDLYTSTCLK (tied_to_ground_i), + .TXPOSTCURSOR (TXPOSTCURSOR_IN), + .TXPOSTCURSORINV (tied_to_ground_i), + .TXPRECURSOR (TXPRECURSOR_IN), + .TXPRECURSORINV (tied_to_ground_i), + .TXQPIBIASEN (tied_to_ground_i), + .TXQPISENN (), + .TXQPISENP (), + .TXQPISTRONGPDOWN (tied_to_ground_i), + .TXQPIWEAKPUP (tied_to_ground_i), + .TXSYSCLKSEL (2'b11), + .TXUSERRDY (TXUSERRDY_IN), + //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ + .TXGEARBOXREADY (), + .TXHEADER ({tied_to_ground_i,TXHEADER_IN}), + .TXSEQUENCE (TXSEQUENCE_IN), + .TXSTARTSEQ (tied_to_ground_i), + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + .TX8B10BBYPASS (tied_to_ground_vec_i[7:0]), + .TX8B10BEN (tied_to_ground_i), + .TXCHARDISPMODE (tied_to_ground_vec_i[7:0]), + .TXCHARDISPVAL (tied_to_ground_vec_i[7:0]), + .TXCHARISK (tied_to_ground_vec_i[7:0]), + //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ---------- + .TXBUFSTATUS (), + .TXDLYBYPASS (tied_to_vcc_i), + .TXDLYEN (tied_to_ground_i), + .TXDLYHOLD (tied_to_ground_i), + .TXDLYOVRDEN (tied_to_ground_i), + .TXDLYSRESET (tied_to_ground_i), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (tied_to_ground_i), + .TXPHALIGN (tied_to_ground_i), + .TXPHALIGNDONE (), + .TXPHALIGNEN (tied_to_ground_i), + .TXPHDLYPD (tied_to_ground_i), + .TXPHDLYRESET (tied_to_ground_i), + .TXPHINIT (tied_to_ground_i), + .TXPHINITDONE (), + .TXPHOVRDEN (tied_to_ground_i), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .GTTXRESET (GTTXRESET_IN), + .TXDATA (txdata_i), + .TXOUTCLK (TXOUTCLK_OUT), + .TXOUTCLKFABRIC (TXOUTCLKFABRIC_OUT), + .TXOUTCLKPCS (TXOUTCLKPCS_OUT), + .TXOUTCLKSEL (3'b010), + .TXPCSRESET (TXPCSRESET_IN), + .TXPMARESET (tied_to_ground_i), + .TXUSRCLK (TXUSRCLK_IN), + .TXUSRCLK2 (TXUSRCLK2_IN), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GTXTXN (GTXTXN_OUT), + .GTXTXP (GTXTXP_OUT), + .TXBUFDIFFCTRL (3'b100), + .TXDIFFCTRL (4'b1110), + .TXDIFFPD (tied_to_ground_i), + .TXINHIBIT (TXINHIBIT_IN), + .TXMAINCURSOR (TXMAINCURSOR_IN), + .TXPDELECIDLEMODE (tied_to_ground_i), + .TXPISOPD (tied_to_ground_i), + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + .TXRATE (tied_to_ground_vec_i[2:0]), + .TXRATEDONE (), + .TXRESETDONE (TXRESETDONE_OUT), + //------------------- Transmit Ports - TX PRBS Generator ------------------- + .TXPRBSFORCEERR (tied_to_ground_i), + .TXPRBSSEL (TXPRBSSEL_IN), + //------------------ Transmit Ports - TX Polarity Control ------------------ + .TXPOLARITY (tied_to_ground_i), + //--------------- Transmit Ports - TX Ports for PCI Express ---------------- + .TXDEEMPH (tied_to_ground_i), + .TXDETECTRX (tied_to_ground_i), + .TXELECIDLE (tied_to_ground_i), + .TXMARGIN (tied_to_ground_vec_i[2:0]), + .TXSWING (tied_to_ground_i), + //------------------- Transmit Ports - TX Ports for SATA ------------------- + .TXCOMFINISH (), + .TXCOMINIT (tied_to_ground_i), + .TXCOMSAS (tied_to_ground_i), + .TXCOMWAKE (tied_to_ground_i) + + ); + +endmodule + + diff --git a/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_block.v b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_block.v new file mode 100755 index 000000000..e15946fec --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_block.v @@ -0,0 +1,970 @@ +//----------------------------------------------------------------------------- +// Title : Block level wrapper +// Project : 10GBASE-R +//----------------------------------------------------------------------------- +// File : ten_gig_eth_pcs_pma_block.v +//----------------------------------------------------------------------------- +// Description: This file is a wrapper for the 10GBASE-R core. It contains the +// 10GBASE-R core, the transceivers and some transceiver logic. +//----------------------------------------------------------------------------- +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + +module ten_gig_eth_pcs_pma_block # + ( + parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "FALSE" + ) + ( +// input refclk_n, +// input refclk_p, + input refclk156, + input refclk156_buf, + output clk156, + output txclk322, + output rxclk322, + output dclk, + input areset, + input reset, + input txreset322, + input rxreset322, + input dclk_reset, + output txp, + output txn, + input rxp, + input rxn, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output [63:0] xgmii_rxd, + output [7:0] xgmii_rxc, + input mdc, + input mdio_in, + output mdio_out, + output mdio_tri, + input [4 : 0] prtad, + output [7 : 0] core_status, + output tx_resetdone, + output rx_resetdone, + input signal_detect, + input tx_fault, + output tx_disable); + + // Static signal Assigments + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [7:0] tied_to_vcc_vec_i; + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 8'hff; + + + wire [31:0] gt_txd; + wire [7:0] gt_txc; + + wire [31:0] gt_rxd; + wire [7:0] gt_rxc; + + reg [31:0] gt_rxd_d1; + reg [7:0] gt_rxc_d1; + + wire [15:0] gt0_drpdi_i; + wire [15:0] gt0_drpaddr_i; + wire [15:0] gt0_drpdo_i; + + wire gt0_rxgearboxslip_i; + wire drp_gnt; + wire drp_req; + + wire [2:0] gt0_loopback_i; + wire gt0_clear_rx_prbs_err_count_i; + + wire gt0_qplllock_i; + wire gt0_rxusrclk_i; + wire gt0_txusrclk_i; + wire gt0_gtrxreset_i; + wire gt0_gttxreset_i; + + reg pma_resetout_reg; + wire pma_resetout_rising; + reg pcs_resetout_reg; + wire pcs_resetout_rising; + + wire pma_resetout; + wire pcs_resetout; + + wire clk156_buf; + wire dclk_buf; + + wire gt0_rxuserrdy_i; + wire gt0_txuserrdy_i; + reg gt0_rxuserrdy_r = 1'b0; + reg gt0_txuserrdy_r = 1'b0; + wire GTTXRESET_IN; + wire GTRXRESET_IN; + wire QPLLRESET_IN; + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse; + wire mmcm_locked; + + reg [19:0] rxuserrdy_counter = 20'h0; + // Nominal wait time of 50000 UI = 757 cyles of 156.25MHz clock + localparam [19:0] RXRESETTIME_NOM = 20'h002F5; + // Maximum wait time of 37x10^6 UI = 560782 cycles of 156.25MHz clock + localparam [19:0] RXRESETTIME_MAX = 20'h89000; + + // Set this according to requirements + wire [19:0] RXRESETTIME = RXRESETTIME_NOM; + + // Aid the detection of a cable/board being pulled + reg [3:0] rx_sample = 4'b0000; // Used to monitor RX data for a cable pull + reg [3:0] rx_sample_prev = 4'b0000; // Used to monitor RX data for a cable pull + reg [19:0] cable_pull_watchdog = 20'h20000; // 128K cycles + reg [1:0] cable_pull_watchdog_event = 2'b00; // Count events which suggest no cable pull + reg cable_pull_reset = 1'b0; // This is set when the watchdog above gets to 0. + (* ASYNC_REG = "TRUE" *) + reg cable_pull_reset_reg = 1'b0; // This is set when the watchdog above gets to 0. + (* ASYNC_REG = "TRUE" *) + reg cable_pull_reset_reg_reg = 1'b0; + reg cable_pull_reset_rising = 1'b0; + reg cable_pull_reset_rising_reg = 1'b0; + + // Aid the detection of a cable/board being plugged back in + reg cable_unpull_enable = 1'b0; + reg [19:0] cable_unpull_watchdog = 20'h20000; + reg [10:0] cable_unpull_watchdog_event = 11'b0; + reg cable_unpull_reset = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg cable_unpull_reset_reg = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg cable_unpull_reset_reg_reg = 1'b0; + reg cable_unpull_reset_rising = 1'b0; + reg cable_unpull_reset_rising_reg = 1'b0; + + wire signal_detect_comb; + wire cable_is_pulled; + + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT... + assign drp_gnt = drp_req; + + ten_gig_eth_pcs_pma + ten_gig_eth_pcs_pma_core ( + .reset(reset), + .txreset322(txreset322), + .rxreset322(rxreset322), + .dclk_reset(dclk_reset), + .pma_resetout(pma_resetout), + .pcs_resetout(pcs_resetout), + .clk156(clk156), + .txusrclk2(txclk322), + .rxusrclk2(rxclk322), + .dclk(dclk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + .mdc(mdc), + .mdio_in(mdio_in), + .mdio_out(mdio_out), + .mdio_tri(mdio_tri), + .prtad(prtad), + .core_status(core_status), + .pma_pmd_type(3'b101), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den(gt0_drpen_i), + .drp_dwe(gt0_drpwe_i), + .drp_daddr(gt0_drpaddr_i), + .drp_di(gt0_drpdi_i), + .drp_drdy(gt0_drprdy_i), + .drp_drpdo(gt0_drpdo_i), + .resetdone(resetdone), + .gt_txd(gt_txd), + .gt_txc(gt_txc), + .gt_rxd(gt_rxd_d1), + .gt_rxc(gt_rxc_d1), + .gt_slip(gt0_rxgearboxslip_i), + .signal_detect(signal_detect_comb), + .tx_fault(tx_fault), + .tx_disable(tx_disable), + .tx_prbs31_en(tx_prbs31_en), + .rx_prbs31_en(rx_prbs31_en), + .clear_rx_prbs_err_count(gt0_clear_rx_prbs_err_count_i), + .loopback_ctrl(gt0_loopback_i)); + + // Make the GT Wizard output connect to the core and top level i/f + //assign Q1_CLK0_GTREFCLK_PAD_N_IN = refclk_n; + //assign Q1_CLK0_GTREFCLK_PAD_P_IN = refclk_p; + + wire gt0_txusrclk2_i; + wire gt0_rxusrclk2_i; + wire gt0_drpclk_i; + wire clkfbout; + + // + // Single ended 156MHz reference clock brought in from upper hierarchy now. + // + wire q1_clk0_refclk_i = refclk156; + + wire q1_clk0_refclk_i_bufh = refclk156_buf; + + assign txclk322 = gt0_txusrclk2_i; + assign rxclk322 = gt0_rxusrclk2_i; + assign gt0_drpclk_i = dclk; + + assign RXN_IN = rxn; + assign RXP_IN = rxp; + + wire TXN_OUT; + wire TXP_OUT; + + assign txn = TXN_OUT; + assign txp = TXP_OUT; + + wire gt0_txresetdone_i; + wire gt0_rxresetdone_i; + + (* ASYNC_REG = "TRUE" *) + reg gt0_txresetdone_i_rega = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg gt0_txresetdone_i_reg = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg gt0_rxresetdone_i_rega = 1'b0; + (* ASYNC_REG = "TRUE" *) + reg gt0_rxresetdone_i_reg = 1'b0; + + reg gt0_rxresetdone_i_regrx322 = 1'b0; + + always @(posedge clk156) + begin + if(mmcm_locked == 1'b1) begin + gt0_txresetdone_i_rega <= gt0_txresetdone_i; + gt0_txresetdone_i_reg <= gt0_txresetdone_i_rega; + gt0_rxresetdone_i_rega <= gt0_rxresetdone_i; + gt0_rxresetdone_i_reg <= gt0_rxresetdone_i_rega; + end + end + + assign resetdone = gt0_txresetdone_i_reg && gt0_rxresetdone_i_reg; + assign tx_resetdone = gt0_txresetdone_i_reg && mmcm_locked; + assign rx_resetdone = gt0_rxresetdone_i_reg && mmcm_locked; + + wire [1:0] gt0_txheader_i; + wire [6:0] gt0_txsequence_i; + wire [31:0] gt0_txdata_i; + + reg gt0_rxbufreset_i = 1'b0; + wire [2:0] gt0_rxbufstatus_i; + + assign gt0_txdata_i[0 ] = gt_txd[31]; + assign gt0_txdata_i[1 ] = gt_txd[30]; + assign gt0_txdata_i[2 ] = gt_txd[29]; + assign gt0_txdata_i[3 ] = gt_txd[28]; + assign gt0_txdata_i[4 ] = gt_txd[27]; + assign gt0_txdata_i[5 ] = gt_txd[26]; + assign gt0_txdata_i[6 ] = gt_txd[25]; + assign gt0_txdata_i[7 ] = gt_txd[24]; + assign gt0_txdata_i[8 ] = gt_txd[23]; + assign gt0_txdata_i[9 ] = gt_txd[22]; + assign gt0_txdata_i[10] = gt_txd[21]; + assign gt0_txdata_i[11] = gt_txd[20]; + assign gt0_txdata_i[12] = gt_txd[19]; + assign gt0_txdata_i[13] = gt_txd[18]; + assign gt0_txdata_i[14] = gt_txd[17]; + assign gt0_txdata_i[15] = gt_txd[16]; + assign gt0_txdata_i[16] = gt_txd[15]; + assign gt0_txdata_i[17] = gt_txd[14]; + assign gt0_txdata_i[18] = gt_txd[13]; + assign gt0_txdata_i[19] = gt_txd[12]; + assign gt0_txdata_i[20] = gt_txd[11]; + assign gt0_txdata_i[21] = gt_txd[10]; + assign gt0_txdata_i[22] = gt_txd[9 ]; + assign gt0_txdata_i[23] = gt_txd[8 ]; + assign gt0_txdata_i[24] = gt_txd[7 ]; + assign gt0_txdata_i[25] = gt_txd[6 ]; + assign gt0_txdata_i[26] = gt_txd[5 ]; + assign gt0_txdata_i[27] = gt_txd[4 ]; + assign gt0_txdata_i[28] = gt_txd[3 ]; + assign gt0_txdata_i[29] = gt_txd[2 ]; + assign gt0_txdata_i[30] = gt_txd[1 ]; + assign gt0_txdata_i[31] = gt_txd[0 ]; + assign gt0_txheader_i[0] = gt_txc[1]; + assign gt0_txheader_i[1] = gt_txc[0]; + assign gt0_txsequence_i = {1'b0, gt_txc[7:2]}; + + wire [31:0] gt0_rxdata_i; + wire [1:0] gt0_rxheader_i; + wire gt0_rxheadervalid_i; + wire gt0_rxdatavalid_i; + + assign gt_rxd[0 ] = gt0_rxdata_i[31]; + assign gt_rxd[1 ] = gt0_rxdata_i[30]; + assign gt_rxd[2 ] = gt0_rxdata_i[29]; + assign gt_rxd[3 ] = gt0_rxdata_i[28]; + assign gt_rxd[4 ] = gt0_rxdata_i[27]; + assign gt_rxd[5 ] = gt0_rxdata_i[26]; + assign gt_rxd[6 ] = gt0_rxdata_i[25]; + assign gt_rxd[7 ] = gt0_rxdata_i[24]; + assign gt_rxd[8 ] = gt0_rxdata_i[23]; + assign gt_rxd[9 ] = gt0_rxdata_i[22]; + assign gt_rxd[10] = gt0_rxdata_i[21]; + assign gt_rxd[11] = gt0_rxdata_i[20]; + assign gt_rxd[12] = gt0_rxdata_i[19]; + assign gt_rxd[13] = gt0_rxdata_i[18]; + assign gt_rxd[14] = gt0_rxdata_i[17]; + assign gt_rxd[15] = gt0_rxdata_i[16]; + assign gt_rxd[16] = gt0_rxdata_i[15]; + assign gt_rxd[17] = gt0_rxdata_i[14]; + assign gt_rxd[18] = gt0_rxdata_i[13]; + assign gt_rxd[19] = gt0_rxdata_i[12]; + assign gt_rxd[20] = gt0_rxdata_i[11]; + assign gt_rxd[21] = gt0_rxdata_i[10]; + assign gt_rxd[22] = gt0_rxdata_i[9 ]; + assign gt_rxd[23] = gt0_rxdata_i[8 ]; + assign gt_rxd[24] = gt0_rxdata_i[7 ]; + assign gt_rxd[25] = gt0_rxdata_i[6 ]; + assign gt_rxd[26] = gt0_rxdata_i[5 ]; + assign gt_rxd[27] = gt0_rxdata_i[4 ]; + assign gt_rxd[28] = gt0_rxdata_i[3 ]; + assign gt_rxd[29] = gt0_rxdata_i[2 ]; + assign gt_rxd[30] = gt0_rxdata_i[1 ]; + assign gt_rxd[31] = gt0_rxdata_i[0 ]; + assign gt_rxc = {4'b0000, gt0_rxheadervalid_i,gt0_rxdatavalid_i, gt0_rxheader_i[0], gt0_rxheader_i[1]}; + + always @(posedge rxclk322) begin + gt_rxc_d1 <= gt_rxc; + gt_rxd_d1 <= gt_rxd; + gt0_rxresetdone_i_regrx322 <= gt0_rxresetdone_i; + end + + // Asynch reset synchronizer registers + (* ASYNC_REG = "TRUE" *) + reg areset_q1_clk0_refclk_i_bufh_tmp; + (* ASYNC_REG = "TRUE" *) + reg areset_q1_clk0_refclk_i_bufh; + (* ASYNC_REG = "TRUE" *) + reg areset_gt0_rxusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg areset_gt0_rxusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg areset_clk156_tmp; + (* ASYNC_REG = "TRUE" *) + reg areset_clk156; + (* ASYNC_REG = "TRUE" *) + reg cable_pull_reset_rising_gt0_rxusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg cable_pull_reset_rising_gt0_rxusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg cable_unpull_reset_rising_gt0_rxusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg pma_resetout_rising_gt0_rxusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg pma_resetout_rising_gt0_rxusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg gt0_qplllock_i_gt0_rxusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg gt0_qplllock_i_gt0_rxusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg gt0_qplllock_i_gt0_txusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg gt0_qplllock_i_gt0_txusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg mmcm_locked_clk156_tmp; + (* ASYNC_REG = "TRUE" *) + reg mmcm_locked_clk156; + (* ASYNC_REG = "TRUE" *) + reg gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg gt0_gtrxreset_i_gt0_rxusrclk2_i; + (* ASYNC_REG = "TRUE" *) + reg gt0_gttxreset_i_gt0_txusrclk2_i_tmp; + (* ASYNC_REG = "TRUE" *) + reg gt0_gttxreset_i_gt0_txusrclk2_i; + + // Asynch reset synchronizers + always @(posedge areset or posedge q1_clk0_refclk_i_bufh) + begin + if(areset) + begin + areset_q1_clk0_refclk_i_bufh_tmp <= 1'b1; + areset_q1_clk0_refclk_i_bufh <= 1'b1; + end + else + begin + areset_q1_clk0_refclk_i_bufh_tmp <= 1'b0; + areset_q1_clk0_refclk_i_bufh <= areset_q1_clk0_refclk_i_bufh_tmp; + end + end + + always @(posedge areset or posedge gt0_rxusrclk2_i) + begin + if(areset) + begin + areset_gt0_rxusrclk2_i_tmp <= 1'b1; + areset_gt0_rxusrclk2_i <= 1'b1; + end + else + begin + areset_gt0_rxusrclk2_i_tmp <= 1'b0; + areset_gt0_rxusrclk2_i <= areset_gt0_rxusrclk2_i_tmp; + end + end + + always @(posedge areset or posedge clk156) + begin + if(areset) + begin + areset_clk156_tmp <= 1'b1; + areset_clk156 <= 1'b1; + end + else + begin + areset_clk156_tmp <= 1'b0; + areset_clk156 <= areset_clk156_tmp; + end + end + + always @(posedge cable_pull_reset_rising or posedge gt0_rxusrclk2_i) + begin + if(cable_pull_reset_rising) + begin + cable_pull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b1; + cable_pull_reset_rising_gt0_rxusrclk2_i <= 1'b1; + end + else + begin + cable_pull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b0; + cable_pull_reset_rising_gt0_rxusrclk2_i <= cable_pull_reset_rising_gt0_rxusrclk2_i_tmp; + end + end + + always @(posedge cable_unpull_reset_rising or posedge gt0_rxusrclk2_i) + begin + if(cable_unpull_reset_rising) + begin + cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b1; + cable_unpull_reset_rising_gt0_rxusrclk2_i <= 1'b1; + end + else + begin + cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp <= 1'b0; + cable_unpull_reset_rising_gt0_rxusrclk2_i <= cable_unpull_reset_rising_gt0_rxusrclk2_i_tmp; + end + end + + always @(posedge pma_resetout_rising or posedge gt0_rxusrclk2_i) + begin + if(pma_resetout_rising) + begin + pma_resetout_rising_gt0_rxusrclk2_i_tmp <= 1'b1; + pma_resetout_rising_gt0_rxusrclk2_i <= 1'b1; + end + else + begin + pma_resetout_rising_gt0_rxusrclk2_i_tmp <= 1'b0; + pma_resetout_rising_gt0_rxusrclk2_i <= pma_resetout_rising_gt0_rxusrclk2_i_tmp; + end + end + + always @(negedge gt0_qplllock_i or posedge gt0_rxusrclk2_i) + begin + if(!gt0_qplllock_i) + begin + gt0_qplllock_i_gt0_rxusrclk2_i_tmp <= 1'b0; + gt0_qplllock_i_gt0_rxusrclk2_i <= 1'b0; + end + else + begin + gt0_qplllock_i_gt0_rxusrclk2_i_tmp <= 1'b1; + gt0_qplllock_i_gt0_rxusrclk2_i <= gt0_qplllock_i_gt0_rxusrclk2_i_tmp; + end + end + + always @(negedge gt0_qplllock_i or posedge gt0_txusrclk2_i) + begin + if(!gt0_qplllock_i) + begin + gt0_qplllock_i_gt0_txusrclk2_i_tmp <= 1'b0; + gt0_qplllock_i_gt0_txusrclk2_i <= 1'b0; + end + else + begin + gt0_qplllock_i_gt0_txusrclk2_i_tmp <= 1'b1; + gt0_qplllock_i_gt0_txusrclk2_i <= gt0_qplllock_i_gt0_txusrclk2_i_tmp; + end + end + + always @(negedge mmcm_locked or posedge clk156) + begin + if(!mmcm_locked) + begin + mmcm_locked_clk156_tmp <= 1'b0; + mmcm_locked_clk156 <= 1'b0; + end + else + begin + mmcm_locked_clk156_tmp <= 1'b1; + mmcm_locked_clk156 <= mmcm_locked_clk156_tmp; + end + end + + always @(posedge gt0_gtrxreset_i or posedge gt0_rxusrclk2_i) + begin + if(gt0_gtrxreset_i) + begin + gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp <= 1'b1; + gt0_gtrxreset_i_gt0_rxusrclk2_i <= 1'b1; + end + else + begin + gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp <= 1'b0; + gt0_gtrxreset_i_gt0_rxusrclk2_i <= gt0_gtrxreset_i_gt0_rxusrclk2_i_tmp; + end + end + + always @(posedge gt0_gttxreset_i or posedge gt0_txusrclk2_i) + begin + if(gt0_gttxreset_i) + begin + gt0_gttxreset_i_gt0_txusrclk2_i_tmp <= 1'b1; + gt0_gttxreset_i_gt0_txusrclk2_i <= 1'b1; + end + else + begin + gt0_gttxreset_i_gt0_txusrclk2_i_tmp <= 1'b0; + gt0_gttxreset_i_gt0_txusrclk2_i <= gt0_gttxreset_i_gt0_txusrclk2_i_tmp; + end + end + + // Reset logic from the gtwizard top level output file.... + // Adapt the reset_counter to count clk156 ticks. + // 128 ticks at 6.4ns period will be >> 500 ns. + // Removed all 'after DLY' text. + + always @(posedge q1_clk0_refclk_i_bufh or posedge areset_q1_clk0_refclk_i_bufh) + begin + if (areset_q1_clk0_refclk_i_bufh == 1'b1) + reset_counter <= 8'b0; + else if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge q1_clk0_refclk_i_bufh) + begin + if(!reset_counter[7]) + reset_pulse <= 4'b1110; + else + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + // Delay the assertion of RXUSERRDY by the given amount + always @(posedge gt0_rxusrclk2_i or posedge gt0_gtrxreset_i_gt0_rxusrclk2_i or negedge gt0_qplllock_i_gt0_rxusrclk2_i) + begin + if(!gt0_qplllock_i_gt0_rxusrclk2_i || gt0_gtrxreset_i_gt0_rxusrclk2_i) + rxuserrdy_counter <= 20'h0; + else if (!(rxuserrdy_counter == RXRESETTIME)) + rxuserrdy_counter <= rxuserrdy_counter + 1'b1; + else + rxuserrdy_counter <= rxuserrdy_counter; + end + + assign GTTXRESET_IN = reset_pulse[0]; + assign GTRXRESET_IN = reset_pulse[0]; + + assign QPLLRESET_IN = reset_pulse[0]; + + assign gt0_rxuserrdy_i = gt0_rxuserrdy_r; + assign gt0_txuserrdy_i = gt0_txuserrdy_r; + + always @(posedge gt0_rxusrclk2_i or posedge gt0_gtrxreset_i_gt0_rxusrclk2_i) + begin + if(gt0_gtrxreset_i_gt0_rxusrclk2_i) + gt0_rxuserrdy_r <= 1'b0; + else if(rxuserrdy_counter == RXRESETTIME) + gt0_rxuserrdy_r <= 1'b1; + else + gt0_rxuserrdy_r <= gt0_rxuserrdy_r; + end + + always @(posedge gt0_txusrclk2_i or posedge gt0_gttxreset_i_gt0_txusrclk2_i) + begin + if(gt0_gttxreset_i_gt0_txusrclk2_i) + gt0_txuserrdy_r <= 1'b0; + else + gt0_txuserrdy_r <= gt0_qplllock_i_gt0_txusrclk2_i; + end + + // Create a watchdog which samples 4 bits from the gt_rxd vector and checks that it does + // vary from a 1010 or 0101 or 0000 pattern. If not then there may well have been a cable pull + // and the gt rx side needs to be reset. + always @(posedge gt0_rxusrclk2_i or posedge cable_pull_reset_rising_gt0_rxusrclk2_i) + begin + if(cable_pull_reset_rising_gt0_rxusrclk2_i) + begin + cable_pull_watchdog_event <= 2'b00; + cable_pull_watchdog <= 20'h20000; // reset the watchdog + cable_pull_reset <= 1'b0; + rx_sample <= 4'b0; + rx_sample_prev <= 4'b0; + end + else + begin + // Sample 4 bits of the gt_rxd vector + rx_sample <= gt_rxd[7:4]; + rx_sample_prev <= rx_sample; + + if(!cable_pull_reset && !cable_is_pulled && gt0_rxresetdone_i_regrx322) + begin + // If those 4 bits do not look like the cable-pull behaviour, increment the event counter + if(!(rx_sample == 4'b1010) && !(rx_sample == 4'b0101) && !(rx_sample == 4'b0000) && !(rx_sample == rx_sample_prev)) // increment the event counter + cable_pull_watchdog_event <= cable_pull_watchdog_event + 1; + else // we are seeing what may be a cable pull + cable_pull_watchdog_event <= 2'b00; + + + if(cable_pull_watchdog_event == 2'b10) // Two consecutive events which look like the cable is attached + begin + cable_pull_watchdog <= 20'h20000; // reset the watchdog + cable_pull_watchdog_event <= 2'b00; + end + else + cable_pull_watchdog <= cable_pull_watchdog - 1; + + + if(~|cable_pull_watchdog) + cable_pull_reset <= 1'b1; // Hit GTRXRESET! + else + cable_pull_reset <= 1'b0; + end + end + end + + always @(posedge clk156) + begin + if(mmcm_locked == 1'b1) begin + cable_pull_reset_reg <= cable_pull_reset; + cable_pull_reset_reg_reg <= cable_pull_reset_reg; + cable_pull_reset_rising <= cable_pull_reset_reg && !cable_pull_reset_reg_reg; + cable_pull_reset_rising_reg <= cable_pull_reset_rising; + end + end + + always @(posedge gt0_rxusrclk2_i or posedge areset_gt0_rxusrclk2_i or posedge pma_resetout_rising_gt0_rxusrclk2_i) + begin + if(areset_gt0_rxusrclk2_i || pma_resetout_rising_gt0_rxusrclk2_i) + cable_unpull_enable <= 1'b0; + else if(cable_pull_reset) // Cable pull has been detected - enable cable unpull counter + cable_unpull_enable <= 1'b1; + else if(cable_unpull_reset) // Cable has been detected as being plugged in again + cable_unpull_enable <= 1'b0; + else + cable_unpull_enable <= cable_unpull_enable; + end + + // Look for data on the line which does NOT look like the cable is still pulled + // a set of 1024 non-1010 or 0101 or 0000 samples within 128k samples suggests that the cable is in. + always @(posedge gt0_rxusrclk2_i or posedge cable_unpull_reset_rising_gt0_rxusrclk2_i) + begin + if(cable_unpull_reset_rising_gt0_rxusrclk2_i) + begin + cable_unpull_reset <= 1'b0; + cable_unpull_watchdog_event <= 11'b0; // reset the event counter + cable_unpull_watchdog <= 20'h20000; // reset the watchdog window + end + else + begin + if(!cable_unpull_reset && cable_is_pulled && gt0_rxresetdone_i_regrx322) + begin + // If those 4 bits do not look like the cable-pull behaviour, increment the event counter + if(!(rx_sample == 4'b1010) && !(rx_sample == 4'b0101) && !(rx_sample == 4'b0000) && !(rx_sample == rx_sample_prev)) // increment the event counter + cable_unpull_watchdog_event <= cable_unpull_watchdog_event + 1; + + + if(cable_unpull_watchdog_event[10] == 1'b1) // Detected 1k 'valid' rx data words within 128k words + begin + cable_unpull_reset <= 1'b1; // Hit GTRXRESET again! + cable_unpull_watchdog <= 20'h20000; // reset the watchdog window + end + else + cable_unpull_watchdog <= cable_unpull_watchdog - 1; + + if(~|cable_unpull_watchdog) + begin + cable_unpull_watchdog <= 20'h20000; // reset the watchdog window + cable_unpull_watchdog_event <= 11'b0; // reset the event counter + end + end + end + end + + always @(posedge clk156) + begin + if(mmcm_locked == 1'b1) begin + cable_unpull_reset_reg <= cable_unpull_reset; + cable_unpull_reset_reg_reg <= cable_unpull_reset_reg; + cable_unpull_reset_rising <= cable_unpull_reset_reg && !cable_unpull_reset_reg_reg; + cable_unpull_reset_rising_reg <= cable_unpull_reset_rising; + end + end + + // Create the local cable_is_pulled signal + assign cable_is_pulled = cable_unpull_enable; + + // Create the signal_detect signal as an AND of the external signal and (not) the local cable_is_pulled + assign signal_detect_comb = signal_detect && !cable_is_pulled; + + + always @(posedge areset_clk156 or posedge clk156 or negedge mmcm_locked_clk156) + begin + if(areset_clk156 || !mmcm_locked_clk156) + pma_resetout_reg <= 1'b0; + else + pma_resetout_reg <= pma_resetout; + end + + assign pma_resetout_rising = pma_resetout && !pma_resetout_reg; + + always @(posedge areset_clk156 or posedge clk156 or negedge mmcm_locked_clk156) + begin + if(areset_clk156 || !mmcm_locked_clk156) + pcs_resetout_reg <= 1'b0; + else + pcs_resetout_reg <= pcs_resetout; + end + + assign pcs_resetout_rising = pcs_resetout && !pcs_resetout_reg; + + + // Incorporate the pma_resetout_rising and cable_pull/unpull_reset_rising bits generated in code below. + assign gt0_gtrxreset_i = (GTRXRESET_IN || !gt0_qplllock_i || pma_resetout_rising || + cable_pull_reset_rising_reg || cable_unpull_reset_rising_reg) && reset_counter[7]; + assign gt0_gttxreset_i = (GTTXRESET_IN || !gt0_qplllock_i || pma_resetout_rising) && reset_counter[7]; + assign gt0_qpllreset_i = QPLLRESET_IN; + + assign gt0_rxpcsreset_i = pcs_resetout_rising; + assign gt0_txpcsreset_i = pcs_resetout_rising; + + // reset the GT RX Buffer when over/underflowing + always @(posedge gt0_rxusrclk2_i) + begin + if(gt0_rxbufstatus_i[2] == 1'b1 && gt0_rxresetdone_i_regrx322) + gt0_rxbufreset_i <= 1'b1; + else + gt0_rxbufreset_i <= 1'b0; + end + + // As generated by the GT Wizard - cut from _top level in eg design dir + ten_gig_eth_pcs_pma_GT_USRCLK_SOURCE gt_usrclk_source + ( + // IJB. Remove IBUFDS_GTE2 from 10G PHY hierarchy so that it can be shared. + // + // .Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN), + // .Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN), + // .Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i), + + .GT0_TXUSRCLK_OUT (gt0_txusrclk_i), + .GT0_TXUSRCLK2_OUT (gt0_txusrclk2_i), + .GT0_TXOUTCLK_IN (gt0_txoutclk_i), + .GT0_RXUSRCLK_OUT (gt0_rxusrclk_i), + .GT0_RXUSRCLK2_OUT (gt0_rxusrclk2_i), + .GT0_RXOUTCLK_IN (gt0_rxoutclk_i), + .DRPCLK_IN (tied_to_ground_i), + .DRPCLK_OUT () + ); + + // MMCM to generate both clk156 and dclk + MMCME2_BASE # + ( + .BANDWIDTH ("OPTIMIZED"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (4.0), + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE_F (4.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKIN1_PERIOD (6.400), + .CLKOUT1_DIVIDE (8), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .REF_JITTER1 (0.010) + ) + clkgen_i + ( + .CLKFBIN(clkfbout), + .CLKIN1(q1_clk0_refclk_i_bufh), + .PWRDWN(1'b0), + .RST(!gt0_qplllock_i), + .CLKFBOUT(clkfbout), + .CLKOUT0(clk156_buf), + .CLKOUT1(dclk_buf), + .LOCKED(mmcm_locked) + ); + +/* -----\/----- EXCLUDED -----\/----- + BUFG bufg_inst + ( + // .CE (tied_to_vcc_i), + .I (q1_clk0_refclk_i), + .O (q1_clk0_refclk_i_bufh) + ); + -----/\----- EXCLUDED -----/\----- */ + + BUFG clk156_bufg_inst + ( + .I (clk156_buf), + .O (clk156) + ); + + BUFG dclk_bufg_inst + ( + .I (dclk_buf), + .O (dclk) + ); + + // As generated by the GT Wizard - cut from _top level in eg design dir + // Use this example as a template for any updates - some signal names in + // port mappings may have been changed from the GT wizard output + ten_gig_eth_pcs_pma_gtwizard_10gbaser # + ( + .WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP) + ) + gtwizard_10gbaser_i + ( + //_____________________________________________________________________ + //_____________________________________________________________________ + // + + //-------------- Channel - Dynamic Reconfiguration Port (DRP) -------------- + .GT0_DRPADDR_IN (gt0_drpaddr_i[8:0]), + .GT0_DRPCLK_IN (gt0_drpclk_i), + .GT0_DRPDI_IN (gt0_drpdi_i), + .GT0_DRPDO_OUT (gt0_drpdo_i), + .GT0_DRPEN_IN (gt0_drpen_i), + .GT0_DRPRDY_OUT (gt0_drprdy_i), + .GT0_DRPWE_IN (gt0_drpwe_i), + //----------------------------- Eye Scan Ports ----------------------------- + .GT0_EYESCANDATAERROR_OUT (gt0_eyescandataerror_i), + //---------------------- Loopback and Powerdown Ports ---------------------- + .GT0_LOOPBACK_IN (gt0_loopback_i), + //----------------------------- Receive Ports ------------------------------ + .GT0_RXUSERRDY_IN (gt0_rxuserrdy_i), + //------------ Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- + .GT0_RXDATAVALID_OUT (gt0_rxdatavalid_i), + .GT0_RXGEARBOXSLIP_IN (gt0_rxgearboxslip_i), + .GT0_RXHEADER_OUT (gt0_rxheader_i), + .GT0_RXHEADERVALID_OUT (gt0_rxheadervalid_i), + //--------------------- Receive Ports - PRBS Detection --------------------- + .GT0_RXPRBSCNTRESET_IN (gt0_clear_rx_prbs_err_count_i), + .GT0_RXPRBSERR_OUT (), + .GT0_RXPRBSSEL_IN ({rx_prbs31_en,2'b00}), + //----------------- Receive Ports - RX Data Path interface ----------------- + .GT0_GTRXRESET_IN (gt0_gtrxreset_i), + .GT0_RXDATA_OUT (gt0_rxdata_i), + .GT0_RXOUTCLK_OUT (gt0_rxoutclk_i), + .GT0_RXPCSRESET_IN (gt0_rxpcsreset_i), + .GT0_RXUSRCLK_IN (gt0_rxusrclk_i), + .GT0_RXUSRCLK2_IN (gt0_rxusrclk2_i), + //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ + .GT0_GTXRXN_IN (RXN_IN), + .GT0_GTXRXP_IN (RXP_IN), + .GT0_RXCDRLOCK_OUT (), + .GT0_RXELECIDLE_OUT (), + .GT0_RXLPMEN_IN (1'b0), + //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- + .GT0_RXBUFRESET_IN (gt0_rxbufreset_i), + .GT0_RXBUFSTATUS_OUT (gt0_rxbufstatus_i), + //---------------------- Receive Ports - RX PLL Ports ---------------------- + .GT0_RXRESETDONE_OUT (gt0_rxresetdone_i), + //----------------------------- Transmit Ports ----------------------------- + .GT0_TXUSERRDY_IN (gt0_txuserrdy_i), + //------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ + .GT0_TXHEADER_IN (gt0_txheader_i), + .GT0_TXSEQUENCE_IN (gt0_txsequence_i), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .GT0_GTTXRESET_IN (gt0_gttxreset_i), + .GT0_TXDATA_IN (gt0_txdata_i), + .GT0_TXOUTCLK_OUT (gt0_txoutclk_i), + .GT0_TXOUTCLKFABRIC_OUT (gt0_txoutclkfabric_i), + .GT0_TXOUTCLKPCS_OUT (gt0_txoutclkpcs_i), + .GT0_TXPCSRESET_IN (gt0_txpcsreset_i), + .GT0_TXUSRCLK_IN (gt0_txusrclk_i), + .GT0_TXUSRCLK2_IN (gt0_txusrclk2_i), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GT0_GTXTXN_OUT (TXN_OUT), + .GT0_GTXTXP_OUT (TXP_OUT), + .GT0_TXINHIBIT_IN (tx_disable), + .GT0_TXPRECURSOR_IN (5'b0), + .GT0_TXPOSTCURSOR_IN (5'b0), + .GT0_TXMAINCURSOR_IN (7'b0), + //--------------------- Transmit Ports - TX PLL Ports ---------------------- + .GT0_TXRESETDONE_OUT (gt0_txresetdone_i), + //------------------- Transmit Ports - TX PRBS Generator ------------------- + .GT0_TXPRBSSEL_IN ({tx_prbs31_en,2'b00}), + + + + //____________________________COMMON PORTS________________________________ + //-------------------- Common Block - Ref Clock Ports --------------------- + .GT0_GTREFCLK0_COMMON_IN (q1_clk0_refclk_i), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (gt0_qplllock_i), + .GT0_QPLLLOCKDETCLK_IN (tied_to_ground_i), + .GT0_QPLLREFCLKLOST_OUT (), + .GT0_QPLLRESET_IN (gt0_qpllreset_i) + + ); + + +endmodule + + + diff --git a/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_mod.v b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_mod.v new file mode 100755 index 000000000..9c3a1c70b --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_mod.v @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------------- +// Title : Verilog component declaration for block level 10GBASE-R core +// Project : 10 Gigabit Ethernet PCS PMA Core +// File : ten_gig_eth_pcs_pma_mod.v +// Author : Xilinx Inc. +// Description: This module holds the top level component declaration for the +// 10Gb/E PCS/PMA core. +//--------------------------------------------------------------------------- +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + +module ten_gig_eth_pcs_pma +( + input reset, + input txreset322, + input rxreset322, + input dclk_reset, + output pma_resetout, + output pcs_resetout, + input clk156, + input txusrclk2, + input rxusrclk2, + input dclk, + + input [63 : 0] xgmii_txd, + input [7 : 0] xgmii_txc, + output [63 : 0] xgmii_rxd, + output [7 : 0] xgmii_rxc, + + input mdc, + input mdio_in, + output mdio_out, + output mdio_tri, + input [4 : 0] prtad, + output [7 : 0] core_status, + input [2 : 0] pma_pmd_type, + output drp_req, + input drp_gnt, + output drp_den, + output drp_dwe, + output [15:0] drp_daddr, + input drp_drdy, + input [15:0] drp_drpdo, + output [15:0] drp_di, + + output [31 : 0] gt_txd, + output [7 : 0] gt_txc, + input [31 : 0] gt_rxd, + input [7 : 0] gt_rxc, + output gt_slip, + + input resetdone, + output tx_prbs31_en, + output rx_prbs31_en, + output clear_rx_prbs_err_count, + output [2 : 0] loopback_ctrl, + + input signal_detect, + input tx_fault, + output tx_disable); + +endmodule diff --git a/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf new file mode 100644 index 000000000..3d339df04 --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf @@ -0,0 +1,85 @@ +## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +####################################################################### +# Clock frequencies/periods and clock management # +# # +####################################################################### +#NET "*gt0_rxoutclk_i" TNM_NET="rxoutclk"; +#TIMESPEC "TS_rxoutclk" = PERIOD "rxoutclk" 3103 ps; +#NET "*gt0_txoutclk_i" TNM_NET="txoutclk"; +#TIMESPEC "TS_txoutclk" = PERIOD "txoutclk" 3103 ps; +# Edit these constraints to select the correct transceiver for your design +#INST *gtxe2_i LOC=GTXE2_CHANNEL_X0Y12; +#INST *gtxe2_i LOC=GTXE2_CHANNEL_X0Y0; +#INST "*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0"; +# JAB moved this to individual port ucfs in top level +#INST "*port0/*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y0; +#INST "*port0/*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y0"; +#INST "*port1/*gtxe2_i" LOC=GTXE2_CHANNEL_X0Y4; +#INST "*port1/*gtxe2_common_0_i" LOC = "GTXE2_COMMON_X0Y1"; + +NET "*cable_pull_reset" MAXDELAY = 2.0 ns; +NET "*cable_unpull_reset" MAXDELAY = 2.0 ns; + +################################################################## +# Elastic Buffer-related constraints # +################################################################## +NET "*elastic_buffer_i*rd_truegray" MAXDELAY = 6.0 ns; +NET "*elastic_buffer_i?can_insert_wra" TIG; +NET "*wr_gray*" MAXDELAY = 6.0 ns; +NET "*rd_lastgray*" MAXDELAY = 6.0 ns; +################################################################### +NET "*sfp_clk" TNM_NET="refclk"; +NET "*clk156_buf*" TNM_NET="clk156"; +NET "*rxclk322" TNM_NET="rxusrclk2"; +NET "*txclk322" TNM_NET="txclk322"; + +TIMESPEC "TS_rxusrclk2_to_clk156" = FROM rxusrclk2 TO clk156 TIG; +TIMESPEC "TS_rxusrclk2_to_txclk322" = FROM rxusrclk2 TO txclk322 TIG; +TIMESPEC "TS_clk156_to_txclk322" = FROM clk156 TO txclk322 TIG; +TIMESPEC "TS_clk156_to_refclk" = FROM clk156 TO refclk TIG; +TIMESPEC "TS_txclk322_to_clk156" = FROM txclk322 TO clk156 TIG; +TIMESPEC "TS_rxusrclk2_to_refclk" = FROM rxusrclk2 TO refclk TIG; diff --git a/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v new file mode 100644 index 000000000..446fb035b --- /dev/null +++ b/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v @@ -0,0 +1,276 @@ +//----------------------------------------------------------------------------- +// Title : Example Design level wrapper +// Project : 10GBASE-R +//----------------------------------------------------------------------------- +// File : ten_gig_eth_pcs_pma_example_design.v +//----------------------------------------------------------------------------- +// Description: This file is a wrapper for the 10GBASE-R core; it contains all +// of the clock buffers required for implementing the block level +//----------------------------------------------------------------------------- +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + +// +// NOTE!: Modified example design to create x300 top level +// for this IP block. +// +module ten_gig_eth_pcs_pma_x300_top + ( +// input refclk_p, +// input refclk_n, + input refclk156, + input refclk156_buf, + output clk156, + input reset, + input [63 : 0] xgmii_txd, + input [7 : 0] xgmii_txc, + output reg [63 : 0] xgmii_rxd, + output reg [7 : 0] xgmii_rxc, +// output xgmii_rx_clk, //IJB + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4 : 0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable); + + // Signal declarations + wire clk156; + + // Sync the global reset to the relevant clocks + reg core_reset_tx; + reg core_reset_rx; + reg txreset322; + reg rxreset322; + reg dclk_reset; + + reg core_reset_tx_tmp; + reg core_reset_rx_tmp; + reg txreset322_tmp; + reg rxreset322_tmp; + reg dclk_reset_tmp; + + (* KEEP = "true" *) + wire txclk322; + wire rxclk322; + wire dclk; + + wire tx_resetdone_int; + wire rx_resetdone_int; + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + wire mdio_out_int; + wire mdio_tri_int; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + //synthesis attribute async_reg of core_reset_tx_tmp is "true"; + //synthesis attribute async_reg of core_reset_tx is "true"; + //synthesis attribute async_reg of core_reset_rx_tmp is "true"; + //synthesis attribute async_reg of core_reset_rx is "true"; + always @(posedge reset or posedge clk156) + begin + if(reset) + begin + core_reset_tx_tmp <= 1'b1; + core_reset_tx <= 1'b1; + core_reset_rx_tmp <= 1'b1; + core_reset_rx <= 1'b1; + end + else + begin + // Hold core in reset until everything else is ready... +// IJB. Per AR# 53443 changed these lines: +// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset || +// tx_fault || !(signal_detect) ); + core_reset_tx_tmp <= (!(tx_resetdone_int) || reset); + + core_reset_tx <= core_reset_tx_tmp; +// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || +// tx_fault || !(signal_detect) ); + core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || !(signal_detect)); + + core_reset_rx <= core_reset_rx_tmp; + end + end + + //synthesis attribute async_reg of txreset322_tmp is "true"; + //synthesis attribute async_reg of txreset322 is "true"; + always @(posedge reset or posedge txclk322) + begin + if(reset) + begin + txreset322_tmp <= 1'b1; + txreset322 <= 1'b1; + end + else + begin + txreset322_tmp <= core_reset_tx; + txreset322 <= txreset322_tmp; + end + end + + //synthesis attribute async_reg of rxreset322_tmp is "true"; + //synthesis attribute async_reg of rxreset322 is "true"; + always @(posedge reset or posedge rxclk322) + begin + if(reset) + begin + rxreset322_tmp <= 1'b1; + rxreset322 <= 1'b1; + end + else + begin + rxreset322_tmp <= core_reset_rx; + rxreset322 <= rxreset322_tmp; + end + end + + //synthesis attribute async_reg of dclk_reset_tmp is "true"; + //synthesis attribute async_reg of dclk_reset is "true"; + always @(posedge reset or posedge dclk) + begin + if(reset) + begin + dclk_reset_tmp <= 1'b1; + dclk_reset <= 1'b1; + end + else + begin + dclk_reset_tmp <= core_reset_rx; + dclk_reset <= dclk_reset_tmp; + end + end + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + // Add a pipeline to the mdio outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + end + + // Instantiate the 10GBASE-R Block Level + + ten_gig_eth_pcs_pma_block # ( + .EXAMPLE_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware + ten_gig_eth_pcs_pma_block + ( +// .refclk_n(refclk_n), +// .refclk_p(refclk_p), + .refclk156(refclk156), + .refclk156_buf(refclk156_buf), + .clk156(clk156), + .txclk322(txclk322), + .rxclk322(rxclk322), + .dclk(dclk), + .areset(reset), + .reset(core_reset_tx), + .rxreset322(rxreset322), + .txreset322(txreset322), + .dclk_reset(dclk_reset), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc), + .mdio_in(mdio_in), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .tx_disable(tx_disable)); + + // assign core_clk156_out = clk156; + + // Not needed in X300 +/* -----\/----- EXCLUDED -----\/----- + + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr( + .Q(xgmii_rx_clk), + .D1(1'b1), + .D2(1'b0), + .C(clk156), + .CE(1'b1), + .R(1'b0), + .S(1'b0)); + + -----/\----- EXCLUDED -----/\----- */ + +endmodule diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf index b638b2c99..c31a525f7 100644 --- a/fpga/usrp3/top/x300/timing.ucf +++ b/fpga/usrp3/top/x300/timing.ucf @@ -1,28 +1,32 @@ NET "FPGA_CLK_p" TNM_NET = "FPGA_CLK_p"; -TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50 %; +TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50%; NET "FPGA_CLK_n" TNM_NET = "FPGA_CLK_n"; -TIMESPEC "TS_FPGA_CLK_n" = PERIOD "FPGA_CLK_n" 5000 ps HIGH 50 %; +TIMESPEC TS_FPGA_CLK_n = PERIOD "FPGA_CLK_n" TS_FPGA_CLK_p HIGH 50%; -NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK"; -TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %; +NET "FPGA_REFCLK_10MHz_p" TNM_NET = "FPGA_REFCLK_10MHz_p"; +TIMESPEC "TS_FPGA_REFCLK_10MHz_p" = PERIOD "FPGA_REFCLK_10MHz_p" 100 ns HIGH 50%; -#NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P"; -#TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 8333 ps HIGH 50 %; +NET "FPGA_REFCLK_10MHz_n" TNM_NET = "FPGA_REFCLK_10MHz_n"; +TIMESPEC TS_FPGA_REFCLK_10MHz_n = PERIOD "FPGA_REFCLK_10MHz_n" TS_FPGA_REFCLK_10MHz_p HIGH 50%; -#NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P"; -#TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 8333 ps HIGH 50 %; +NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK"; +TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %; NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P"; TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 5000 ps HIGH 50 %; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING; +NET "DB0_ADC_DCLK_N" TNM_NET = DB0_ADC_DCLK_N; +TIMESPEC TS_DB0_ADC_DCLK_N = PERIOD "DB0_ADC_DCLK_N" TS_DB0_ADC_DCLK_P HIGH 50%; NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P"; TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 5000 ps HIGH 50 %; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING; +NET "DB1_ADC_DCLK_N" TNM_NET = DB1_ADC_DCLK_N; +TIMESPEC TS_DB1_ADC_DCLK_N = PERIOD "DB1_ADC_DCLK_N" TS_DB1_ADC_DCLK_P HIGH 50%; NET "bus_clk" TNM = bus_clk_grp; NET "ioport2_clk" TNM = ioport2_clk_grp; @@ -38,4 +42,4 @@ TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_cl # to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent, # lock the locations of the MMCM and BUFG to generate radio_clk. INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0; -INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8; \ No newline at end of file +INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8; diff --git a/fpga/usrp3/top/x300/x300.ucf b/fpga/usrp3/top/x300/x300.ucf index ab7c65c98..e73c58e20 100644 --- a/fpga/usrp3/top/x300/x300.ucf +++ b/fpga/usrp3/top/x300/x300.ucf @@ -7,15 +7,15 @@ ## SFP Lanes # SFP clock pins now come from their own ucf files. See _10ge.ucf, _1ge.ucf, and _cpri.ucf -NET SFP0_RX_n LOC = AA3; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP0_RX_p LOC = AA4; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP0_TX_n LOC = Y1; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP0_TX_p LOC = Y2; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP1_RX_n LOC = T5; #IJB. NOTE this signal prefixed SFP2 on schematics -NET SFP1_RX_p LOC = T6; #IJB. NOTE this signal prefixed SFP2 on schematics -NET SFP1_TX_n LOC = P1; #IJB. NOTE this signal prefixed SFP2 on schematics -NET SFP1_TX_p LOC = P2; #IJB. NOTE this signal prefixed SFP2 on schematics - +# NOTE: In the schematic SFP0 signals are prefixed SFP1 and SFP1 signals are prefixed SFP2 +NET SFP0_RX_n IOSTANDARD = LVDS | LOC = AA3; +NET SFP0_RX_p IOSTANDARD = LVDS | LOC = AA4; +NET SFP0_TX_n IOSTANDARD = LVDS | LOC = Y1; +NET SFP0_TX_p IOSTANDARD = LVDS | LOC = Y2; +NET SFP1_RX_n IOSTANDARD = LVDS | LOC = T5; +NET SFP1_RX_p IOSTANDARD = LVDS | LOC = T6; +NET SFP1_TX_n IOSTANDARD = LVDS | LOC = P1; +NET SFP1_TX_p IOSTANDARD = LVDS | LOC = P2; ## ADC 0 NET DB0_ADC_DA0_N IOSTANDARD = LVDS_25 | LOC = L27; diff --git a/fpga/usrp3/top/x300/x300_10ge.ucf b/fpga/usrp3/top/x300/x300_10ge.ucf index c16bd5350..474cc48b9 100644 --- a/fpga/usrp3/top/x300/x300_10ge.ucf +++ b/fpga/usrp3/top/x300/x300_10ge.ucf @@ -1,2 +1,7 @@ -NET XG_CLK_p IOSTANDARD = LVDS_25 | LOC = R8; -NET XG_CLK_n IOSTANDARD = LVDS_25 | LOC = R7; +NET XG_CLK_p IOSTANDARD = LVDS_25 | LOC = R8; +NET "XG_CLK_p" TNM_NET = XG_CLK_p; +TIMESPEC TS_XG_CLK_p = PERIOD "XG_CLK_p" 6400 ps HIGH 50%; + +NET XG_CLK_n IOSTANDARD = LVDS_25 | LOC = R7; +NET "XG_CLK_n" TNM_NET = XG_CLK_n; +TIMESPEC TS_XG_CLK_n = PERIOD "XG_CLK_n" TS_XG_CLK_p HIGH 50%; diff --git a/fpga/usrp3/top/x300/x300_1ge.ucf b/fpga/usrp3/top/x300/x300_1ge.ucf index acd376251..bdcff1201 100644 --- a/fpga/usrp3/top/x300/x300_1ge.ucf +++ b/fpga/usrp3/top/x300/x300_1ge.ucf @@ -1,2 +1,7 @@ -NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8; -NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7; +NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8; +NET "ETH_CLK_p" TNM_NET = ETH_CLK_p; +TIMESPEC TS_ETH_CLK_p = PERIOD "ETH_CLK_p" 8 ns HIGH 50%; + +NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7; +NET "ETH_CLK_n" TNM_NET = ETH_CLK_n; +TIMESPEC TS_ETH_CLK_n = PERIOD "ETH_CLK_n" TS_ETH_CLK_p HIGH 50%; -- cgit v1.2.3 


-CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 
-
-                Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
-                Version: 1.1
-                Release: ISE 14.2 / Vivado 2012.2
-                Release Date: July 25, 2012
-
---------------------------------------------------------------------------------
-
-Table of Contents
-
-1. INTRODUCTION 
-2. DEVICE SUPPORT    
-3. NEW FEATURES HISTORY   
-4. RESOLVED ISSUES 
-5. KNOWN ISSUES & LIMITATIONS 
-6. TECHNICAL SUPPORT & FEEDBACK
-7. CORE RELEASE HISTORY 
-8. LEGAL DISCLAIMER 
-
---------------------------------------------------------------------------------
- 
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
-solution. For the latest core updates, see the product page at:
-
-   www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm 
-
-................................................................................
-
-
-2. DEVICE SUPPORT
-
-
-  2.1 ISE 
-   
-    The following device families are supported by the core for this release.
-    
-    
-    All 7 Series devices
-    Zynq-7000 devices
-    All Virtex-6 devices
-    All Spartan-6 devices
-  
-  
-  2.2 Vivado 
-  
-    All 7 Series devices
-    Zynq-7000 devices
-
-................................................................................
-
-
-3. NEW FEATURES HISTORY
-
-
-  3.1 ISE 
-  
-    - First release
-    - ISE 14.2 software support
-  
-  
-  3.2 Vivado
-  
-    - First release
-    - 2012.2 software support
-
-................................................................................
-
-
-4. RESOLVED ISSUES 
-
-
-  4.1 ISE 
-
-    - N/A
-
-
-  4.2 Vivado 
-
-    - N/A
-
-
-................................................................................
-
-
-5. KNOWN ISSUES & LIMITATIONS
-
-
-  5.1 ISE 
-
-    - N/A
-  
-  
-  5.2 Vivado 
-
-    - N/A
-
-
-The most recent information, including known issues, workarounds, and
-resolutions for this version is provided in the IP Release Notes User Guide
-located at 
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
-
-................................................................................
-
-
-6. TECHNICAL SUPPORT & FEEDBACK
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.  
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-................................................................................
-
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-07/25/2012  Xilinx, Inc.  1.1          First release; ISE 14.2 and Vivado 2012.2 support.
-04/24/2012  Xilinx, Inc.  1.1          First release; ISE 14.1 and Vivado 2012.1 support.
-================================================================================
-
-................................................................................
-
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
-
-  This file contains confidential and proprietary information
-  of Xilinx, Inc. and is protected under U.S. and
-  international copyright and other intellectual property
-  laws.
-
-  DISCLAIMER
-  This disclaimer is not a license and does not grant any
-  rights to the materials distributed herewith. Except as
-  otherwise provided in a valid license issued to you by
-  Xilinx, and to the maximum extent permitted by applicable
-  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-  (2) Xilinx shall not be liable (whether in contract or tort,
-  including negligence, or under any other theory of
-  liability) for any loss or damage of any kind or nature
-  related to, arising under or in connection with these
-  materials, including for any direct, or any indirect,
-  special, incidental, or consequential loss or damage
-  (including loss of data, profits, goodwill, or any type of
-  loss or damage suffered as a result of any action brought
-  by a third party) even if such damage or loss was
-  reasonably foreseeable or Xilinx had been advised of the
-  possibility of the same. 
-
-  CRITICAL APPLICATIONS
-  Xilinx products are not designed or intended to be fail-
-  safe, or for use in any application requiring fail-safe
-  performance, such as life-support or safety devices or
-  systems, Class III medical devices, nuclear facilities,
-  applications related to the deployment of airbags, or any
-  other applications that could lead to death, personal
-  injury, or severe property or environmental damage
-  (individually and collectively, "Critical 
-  Applications"). Customer assumes the sole risk and 
-  liability of any use of Xilinx products in Critical 
-  Applications, subject only to applicable laws and 
-  regulations governing limitations on product liability. 
- 
-  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-  PART OF THIS FILE AT ALL TIMES.
-
-

-CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 
-
-                Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
-                Version: 1.1
-                Release: ISE 14.2 / Vivado 2012.2
-                Release Date: July 25, 2012
-
---------------------------------------------------------------------------------
-
-Table of Contents
-
-1. INTRODUCTION 
-2. DEVICE SUPPORT    
-3. NEW FEATURES HISTORY   
-4. RESOLVED ISSUES 
-5. KNOWN ISSUES & LIMITATIONS 
-6. TECHNICAL SUPPORT & FEEDBACK
-7. CORE RELEASE HISTORY 
-8. LEGAL DISCLAIMER 
-
---------------------------------------------------------------------------------
- 
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
-solution. For the latest core updates, see the product page at:
-
-   www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm 
-
-................................................................................
-
-
-2. DEVICE SUPPORT
-
-
-  2.1 ISE 
-   
-    The following device families are supported by the core for this release.
-    
-    
-    All 7 Series devices
-    Zynq-7000 devices
-    All Virtex-6 devices
-    All Spartan-6 devices
-  
-  
-  2.2 Vivado 
-  
-    All 7 Series devices
-    Zynq-7000 devices
-
-................................................................................
-
-
-3. NEW FEATURES HISTORY
-
-
-  3.1 ISE 
-  
-    - First release
-    - ISE 14.2 software support
-  
-  
-  3.2 Vivado
-  
-    - First release
-    - 2012.2 software support
-
-................................................................................
-
-
-4. RESOLVED ISSUES 
-
-
-  4.1 ISE 
-
-    - N/A
-
-
-  4.2 Vivado 
-
-    - N/A
-
-
-................................................................................
-
-
-5. KNOWN ISSUES & LIMITATIONS
-
-
-  5.1 ISE 
-
-    - N/A
-  
-  
-  5.2 Vivado 
-
-    - N/A
-
-
-The most recent information, including known issues, workarounds, and
-resolutions for this version is provided in the IP Release Notes User Guide
-located at 
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
-
-................................................................................
-
-
-6. TECHNICAL SUPPORT & FEEDBACK
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.  
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-................................................................................
-
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-07/25/2012  Xilinx, Inc.  1.1          First release; ISE 14.2 and Vivado 2012.2 support.
-04/24/2012  Xilinx, Inc.  1.1          First release; ISE 14.1 and Vivado 2012.1 support.
-================================================================================
-
-................................................................................
-
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
-
-  This file contains confidential and proprietary information
-  of Xilinx, Inc. and is protected under U.S. and
-  international copyright and other intellectual property
-  laws.
-
-  DISCLAIMER
-  This disclaimer is not a license and does not grant any
-  rights to the materials distributed herewith. Except as
-  otherwise provided in a valid license issued to you by
-  Xilinx, and to the maximum extent permitted by applicable
-  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-  (2) Xilinx shall not be liable (whether in contract or tort,
-  including negligence, or under any other theory of
-  liability) for any loss or damage of any kind or nature
-  related to, arising under or in connection with these
-  materials, including for any direct, or any indirect,
-  special, incidental, or consequential loss or damage
-  (including loss of data, profits, goodwill, or any type of
-  loss or damage suffered as a result of any action brought
-  by a third party) even if such damage or loss was
-  reasonably foreseeable or Xilinx had been advised of the
-  possibility of the same. 
-
-  CRITICAL APPLICATIONS
-  Xilinx products are not designed or intended to be fail-
-  safe, or for use in any application requiring fail-safe
-  performance, such as life-support or safety devices or
-  systems, Class III medical devices, nuclear facilities,
-  applications related to the deployment of airbags, or any
-  other applications that could lead to death, personal
-  injury, or severe property or environmental damage
-  (individually and collectively, "Critical 
-  Applications"). Customer assumes the sole risk and 
-  liability of any use of Xilinx products in Critical 
-  Applications, subject only to applicable laws and 
-  regulations governing limitations on product liability. 
- 
-  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-  PART OF THIS FILE AT ALL TIMES.
-
-


-CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1 
-
-                Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
-                Version: 1.1
-                Release: ISE 14.2 / Vivado 2012.2
-                Release Date: July 25, 2012
-
---------------------------------------------------------------------------------
-
-Table of Contents
-
-1. INTRODUCTION 
-2. DEVICE SUPPORT    
-3. NEW FEATURES HISTORY   
-4. RESOLVED ISSUES 
-5. KNOWN ISSUES & LIMITATIONS 
-6. TECHNICAL SUPPORT & FEEDBACK
-7. CORE RELEASE HISTORY 
-8. LEGAL DISCLAIMER 
-
---------------------------------------------------------------------------------
- 
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
-solution. For the latest core updates, see the product page at:
-
-   www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm 
-
-................................................................................
-
-
-2. DEVICE SUPPORT
-
-
-  2.1 ISE 
-   
-    The following device families are supported by the core for this release.
-    
-    
-    All 7 Series devices
-    Zynq-7000 devices
-    All Virtex-6 devices
-    All Spartan-6 devices
-  
-  
-  2.2 Vivado 
-  
-    All 7 Series devices
-    Zynq-7000 devices
-
-................................................................................
-
-
-3. NEW FEATURES HISTORY
-
-
-  3.1 ISE 
-  
-    - First release
-    - ISE 14.2 software support
-  
-  
-  3.2 Vivado
-  
-    - First release
-    - 2012.2 software support
-
-................................................................................
-
-
-4. RESOLVED ISSUES 
-
-
-  4.1 ISE 
-
-    - N/A
-
-
-  4.2 Vivado 
-
-    - N/A
-
-
-................................................................................
-
-
-5. KNOWN ISSUES & LIMITATIONS
-
-
-  5.1 ISE 
-
-    - N/A
-  
-  
-  5.2 Vivado 
-
-    - N/A
-
-
-The most recent information, including known issues, workarounds, and
-resolutions for this version is provided in the IP Release Notes User Guide
-located at 
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
-
-................................................................................
-
-
-6. TECHNICAL SUPPORT & FEEDBACK
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.  
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-................................................................................
-
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-07/25/2012  Xilinx, Inc.  1.1          First release; ISE 14.2 and Vivado 2012.2 support.
-04/24/2012  Xilinx, Inc.  1.1          First release; ISE 14.1 and Vivado 2012.1 support.
-================================================================================
-
-................................................................................
-
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
-
-  This file contains confidential and proprietary information
-  of Xilinx, Inc. and is protected under U.S. and
-  international copyright and other intellectual property
-  laws.
-
-  DISCLAIMER
-  This disclaimer is not a license and does not grant any
-  rights to the materials distributed herewith. Except as
-  otherwise provided in a valid license issued to you by
-  Xilinx, and to the maximum extent permitted by applicable
-  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-  (2) Xilinx shall not be liable (whether in contract or tort,
-  including negligence, or under any other theory of
-  liability) for any loss or damage of any kind or nature
-  related to, arising under or in connection with these
-  materials, including for any direct, or any indirect,
-  special, incidental, or consequential loss or damage
-  (including loss of data, profits, goodwill, or any type of
-  loss or damage suffered as a result of any action brought
-  by a third party) even if such damage or loss was
-  reasonably foreseeable or Xilinx had been advised of the
-  possibility of the same. 
-
-  CRITICAL APPLICATIONS
-  Xilinx products are not designed or intended to be fail-
-  safe, or for use in any application requiring fail-safe
-  performance, such as life-support or safety devices or
-  systems, Class III medical devices, nuclear facilities,
-  applications related to the deployment of airbags, or any
-  other applications that could lead to death, personal
-  injury, or severe property or environmental damage
-  (individually and collectively, "Critical 
-  Applications"). Customer assumes the sole risk and 
-  liability of any use of Xilinx products in Critical 
-  Applications, subject only to applicable laws and 
-  regulations governing limitations on product liability. 
- 
-  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-  PART OF THIS FILE AT ALL TIMES.
-
-